JPH08162456A - Method of manufacturing bump - Google Patents

Abstract

PURPOSE: To cut down the bump manufacturing steps by a method wherein wiring is formed on a scribe line simultaneously using a wiring layer so as to electrically and commonly connect the whole pads of all LSI chips on a wafer. CONSTITUTION: Within a reticle 10, during the manufacturing step of forming pads, wirings are formed even on a scribe line 12. Next, through the intermediary of wiring 14 formed on this scribe line 12, all pads 18 of all LSI 16 in the reticle 10 are commonly connected. The mask patterns are repeatedly transferred on the wafer using this reticle 10. Through these procedures, all pads 18 of all LSI chips 16 on the wafer can be commonly connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bump formed on a pad for bonding an LSI chip, and more particularly, to an under bump which has been conventionally required for forming a bump.・ Metal (Under Bu
mp Metal: hereinafter referred to as UBM) and a bump manufacturing method capable of simplifying the bump forming process.

[0002]

2. Description of the Related Art Conventionally, in order to connect an LSI chip to an external device, pads of the LSI chip and leads of a lead frame have been bonded one by one with wires. Therefore, there is a problem in that it takes more time and labor for an LSI chip having multiple terminals, and it is necessary to consider that the wire must be floated. So L
Form bumps (projection electrodes) on the pads of the SI chip,
A method of directly bonding the pads of the LSI chip and the leads of the lead frame or the copper foil pattern of the tape carrier such as TAB at once is used.

For example, in the sectional process diagrams of FIGS. 9A to 9F, the above-mentioned bumps selectively passivate the passivation film 28 formed on the surface of the wafer 20 as shown in FIG. 9A. The pad 18 is opened to expose only the surface of the pad 18, the UBM 52 is formed on the entire surface of the wafer 20 as shown in FIG. 9B, and the bump 18 is formed as shown in FIG. 9C. A photoresist 32 is formed in a region other than the above, and a bump 34 is formed on the pad 18 by using an electrolytic plating method as shown in FIG.
The photoresist 32 is removed as shown in FIG.
As shown in FIG. 9F, it is formed by etching and removing the UBM 52 formed in the region other than the pad 18.

Here, aluminum is generally used as the pad material, and gold (Au), solder (Pb-Sn), or the like is used as the bump material. On the other hand, for the UBM material, for example, titanium / tungsten (TiW) and gold are generally used in a laminated structure. Note that the UBM material formed on the pad side is a material having good adhesion to aluminum, such as titanium nitride (Ti).
N), titanium / tungsten, titanium (Ti), etc. are similarly used. Similarly, for the UBM material formed on the bump side,
For example, in the case of a gold bump, a material having good adhesion to gold is used, and in the case of a solder bump, a material having good adhesion to solder is used.

The reason why the UBM 52 described above is formed between the pad 18 and the bump 34 is that the pad 18 and the bump 34 are formed.
This is to improve the adhesiveness with. That is, since the pad material aluminum and the bump material gold or solder have poor adhesion, they are formed as an adhesion layer for connecting the bumps 34 to the pads 18. Another reason is that it is used as a common electrode when the bumps 34 are formed on the pads 18 by the electrolytic plating method. That is, in order to form the bumps 34 on the pads 18 using the electrolytic plating method, it is necessary to form electrodes and supply electricity.
Electroplating electrodes are formed on each LSI chip to form bumps 3
Since forming 4 is very inefficient, the UBM 52 is formed over the entire wafer to serve as a common electrode.

Therefore, the pad (material) and the bump (material)
It is not necessary to form the UBM 52 as long as they have adhesion and can be used as a common electrode for connecting all the pads 18 and performing electroplating. However, in the conventional bump manufacturing method, since the UBM 52 is required to form the bump 34 on the pad 18, the step of forming the UBM 52 cannot be omitted, and the material cost and the forming time for that are inevitably extra. There was a problem of this.

[0007]

The object of the present invention is, in view of the problems based on the above-mentioned prior art, to form a layer having adhesion to bumps and forming an antireflection film when forming a pad. By using the outermost wiring layer to connect all pads via scribe lines, the UBM forming step can be omitted when forming bumps, and cost and time can be saved. To provide a method.

[0008]

In order to achieve the above object, the present invention provides a wiring layer having a layer having an adhesion to bumps and serving as an antireflection film on the entire surface of a wafer as an outermost layer. Then, the wiring layer is patterned to form at least a pad for each LSI chip formed on the wafer, and a wiring is formed on the scribe line and between the scribe line and the pad. Then, all pads of all LSI chips on the wafer are electrically connected via the wiring on the scribe line, and then a passivation film is formed on the entire surface of the wafer, and then the passivation film is formed. After patterning the film to expose at least all the pads and form a photoresist on the entire surface of the wafer, Patterning the photoresists, the exposed all pads to supply electricity to all said pad via a wiring on the scribe line,
The present invention provides a bump manufacturing method characterized in that the photoresist is removed after forming bumps on all the pads by an electrolytic plating method.

Here, in the patterning step of the passivation film, it is preferable to expose all the pads and all the wirings on the scribe line.

Further, it is preferable that the entire surface of the wafer is etched back to remove the wiring on the scribe line.

Further, the LSI chip is preferably separated by completely removing a region that is less than the width of the scribe line and greater than the width of the wiring on the scribe line.

[0012]

The method of manufacturing a bump according to the present invention, when the pad is formed by using the wiring layer having the adhesion to the bump and having the layer serving as the antireflection film as the outermost layer, that is, the pad. In the step of forming the same, the wiring is formed on the scribe line at the same time by using the same wiring layer, and all the L formed on the wafer are connected via the wiring on the scribe line.
All the pads of the SI chip are electrically connected in common. That is, since the surface of the pad has adhesiveness with the bump and all the pads are commonly connected through the wiring on the scribe line, the passivation film is selectively opened to open all the pads. After exposing the surface,
Electricity can be supplied to all the pads via the wiring on the scribe line, and bumps can be formed on all the pads by using the electrolytic plating method. Also, the wiring on the scribe line should be separated so as to completely remove the area larger than the wiring width when the LSI chips are individually separated, or the wiring should be etched back before the LSI chips are individually separated. The individual LSI chips can be electrically separated by removing them. Therefore, according to the bump forming method of the present invention, the antireflection film, which is the outermost layer of the pad, can play the role of the UBM, so that the UBM forming step and the UBM etching step, which are conventionally required, can be performed. Can be omitted, so that the bump manufacturing process can be shortened by one or two steps,
It is possible to reduce the manufacturing cost and process time involved in manufacturing the bump.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The bump manufacturing method of the present invention will be described in detail below with reference to the preferred embodiments shown in the accompanying drawings.

The bump manufacturing method of the present invention makes it possible to omit the step of forming the UBM formed between the pads when the bumps are formed on the pads. As already described in the prior art, the role of the UBM required when forming bumps on pads is to improve the adhesion between the pads and the bumps, and to serve as a common electrode for electrolytic plating. Is. That is, if the pad can play these two roles, it is not necessary to form the UBM when forming the bump.

A bonding method using bumps was developed because the manufacturing process was 2.0-1. In the age of the rule of several μm, the wiring and the pad were made of aluminum alone, that is, the pad material aluminum and the bump material gold and solder did not adhere to each other. Therefore, the UBM was inevitably necessary. It was On the other hand, when the manufacturing process is miniaturized to about 0.8 to 0.6 μm rule as in the present case, wiring and wiring and Since the pad itself is inferior in durability as an LSI chip when made of aluminum alone, for example, a laminated structure such as a titanium film, a titanium-nitride film, an aluminum-copper alloy (Al-Cu) wiring and a titanium-nitride film from the lower layer. Is used.

Here, an example of a process of forming a wiring having a laminated structure will be described with reference to the sectional process drawings shown in FIGS. In the following description, for example, FIG.
As shown in (a), an N well region 54 and a P well region 56 are formed in the wafer, and these regions 54, 5 are formed.
6 includes a P-type MOS transistor and an N-type M, respectively.
In order to form the OS transistor, each region 5
4 and 56, a source region 58, a drain region 60 and a gate electrode 62 are formed, an interlayer insulating film 64 is further formed on the entire surface of the wafer, and a lower wiring 36 is formed on the interlayer insulating film. Continue the explanation.

First, as shown in FIG. 5A, an interlayer insulating film 22 which is flattened by using, for example, three layers is formed on the lower wiring 36, and the interlayer insulating film 22 is selectively etched. Then, a connection hole 38 for connecting the lower layer wiring 36 and the upper layer wiring is opened, and the lower layer wiring 36 is formed on the bottom surface of the connection hole 38.
Of the interlayer insulating film 22 after exposing a part of the surface of
A titanium film having a film thickness of 500 Å is formed on the side wall of the connection hole 38 and the surface of the lower wiring 36 exposed on the bottom surface of the connection hole 38 by, for example, sputtering, and a titanium nitride film having a film thickness of 1000 Å is formed on the titanium film. The formed barrier metal (adhesion layer) 40 is formed.

Subsequently, as shown in FIG. 5B, an aluminum / copper alloy wiring 42 is formed on the barrier metal (adhesion layer) 40 by sputtering, for example, to a thickness of 8000 Å, and the aluminum / copper alloy wiring 42 is formed. A titanium nitride film having a film thickness of 230 Å is formed on the above, and this is used as the antireflection film 44. Finally, as shown in FIG. 5C, a photoresist 26 is formed on the antireflection film 44, and the barrier metal (adhesion layer) 4 formed on the interlayer insulating film 22.
0, aluminum / copper alloy wiring 42 and antireflection film 4
The upper layer wiring 46 having the laminated structure of 4 is selectively removed by etching to complete the formation process of the upper layer wiring 46.

In the above-mentioned upper wiring 46, the lower titanium film and titanium nitride film are the upper wiring 46.
Used as an adhesion layer 40 such as a barrier metal 40 for preventing a spike current from the lower layer wiring 36 to the lower layer wiring 36 or a tungsten plug embedded in the connection hole 38, and the uppermost titanium nitride film is formed by a photolithography technique. It is a film used as the antireflection film 44 when patterning is performed by using. The material of the antireflection film 44 is not limited, and any material may be used as long as it does not reflect the exposure light of the light source used for the stepper device and has good adhesion to the wiring layer. In addition to the nitride, for example, titanium / tungsten, titanium alone, silicon, nickel, etc. are used.

The upper wiring 46 is formed by laminating the barrier metal (adhesion layer) 40, the wiring layer 42, and the antireflection film 44 in this order from the lower side, but these are not particularly limited and may be, for example, If the material of the wiring layer 42 can play the role of the barrier metal (adhesion layer) 40, the barrier metal (adhesion layer) 40 is not necessary. Similarly, the material of the wiring layer 42 plays the role of the antireflection film 44. If possible, the antireflection film 44 is not necessary. That is, if the material of the wiring layer 42 can play the roles of the barrier metal (adhesion layer) 40 and the antireflection film 44, the barrier metal (adhesion layer) 40 and the antireflection film 44 are not necessary, and the wiring layer Only the layers are acceptable. The wiring layer 42 does not have to have a three-layer structure, and may have any number of layers.

As described above, at present, the wiring generally has a laminated structure, and the material of the antireflection film 44 used as the outermost layer of the upper wiring 46 is between the pad and the bump. Since the same material as the UBM to be formed can be used, the adhesion between the pad and the bump can be improved by using the antireflection film 44 formed on the surface of the pad as the UBM. That is, when the pad is formed or when the antireflection film 44 on the surface of the pad is formed, all the LSIs formed on the wafer are simultaneously formed.
If all pads of the chip can be commonly connected, this antireflection film 44 can be used as a common electrode when bumps are formed on the pads by the electrolytic plating method, so that the UBM forming step is omitted. can do.

Here, FIG. 6 is a schematic plan view of an example of a wafer on which an LSI chip is formed. This wafer 2
As shown in 0, one wafer 20 usually has the same L
The mask pattern of the SI chip 16 is repeatedly transferred. This is because the mask pattern, which is the design data, is enlarged to a size several times larger than that of the four LSs as shown in FIG.
This is because the original plate (reticle) 48 having the mask pattern of the I-chip 16 is created, and the mask pattern drawn on the reticle 48 is directly reduced and projected (stepper system) on the wafer 20. The reticle 4 shown in FIG.
In FIG. 8, a cross-shaped area separating the LSI chip 16 and the LSI chip 16 is a scribe line 12, and its width is about 100 μm.

FIGS. 8A and 8B are a schematic plan view of an example of an LSI chip and an enlarged plan view of a pad portion thereof, respectively. As shown in FIG. 8A, the area of the pad 18 is generally formed on the outer peripheral portion of the LSI chip 16. In addition, as shown in FIG.
Each pad 18 is opened while being connected to the internal circuit 50. Also, each LSI chip 1
Since 6 is separated along the scribe line 12, there is normally nothing on the scribe line 12. Therefore, in the bump manufacturing method of the present invention, all the pads 18 of all the LSI chips 16 formed on the wafer 20 are commonly connected through the scribe line 12 to perform the UBM forming process. Omit it,
Bumps are formed on the pads 18.

FIG. 1 is a schematic plan view of an embodiment of a reticle to which the bump forming method of the present invention is applied. This reticle 10 simultaneously forms wirings on the scribe line 12 during the manufacturing process for forming pads, and all the LSI chips in the reticle 10 are laid through the wirings 14 formed on the scribe line 12. All 16 pads 1
8 are commonly connected. In the illustrated example, only the pads 18 of the upper and lower LSI chips 16 are commonly connected, but it is natural that all the pads 18 of all other LSI chips 16 are commonly connected. Further, by repeatedly transferring the mask pattern onto the wafer 20 using this reticle 10, all pads 18 of all LSI chips 16 on the wafer 20 can be commonly connected.

Here, when the mask pattern is repeatedly transferred onto the wafer 20 using the reticle 10, the misalignment is as small as 0 in the case of the current stepper device. It is several μm. As described above, since the width of the scribe line 12 is usually about 100 μm, if the wiring 14 of, for example, about 60 μm is formed on the scribe line 12, all the pads 18 of all the LSI chips 16 are definitely connected in common. be able to. Further, when forming the wiring 14 on the scribe line 12, it is preferable to form an electrode on a region of the wafer where the LSI chip 16 is not formed and connect the electrode to the wiring 14 on the scribe line 12. . With this configuration, when the bump is formed on the pad 18 using the electroplating method, electricity can be easily supplied through this electrode.

As described above, at the same time when the pad 18 is formed, the wiring 14 is formed on the scribe line 12, and all the LSI chips 16 on the wafer 20 are connected via the wiring 14 on the scribe line 12. By connecting the pad 18 in common, L
A passivation film that serves as a protective film for the SI chip 16 is formed, and the surface of all the pads 18 is exposed by etching this, and a photoresist is formed on the entire surface of the wafer 20. This is patterned and the surface of all the pads 18 is formed. 1 exposed to expose the scribe line 12
Electricity is supplied to all the pads 18 of all the LSI chips 16 through the pad 4, and the pads 18 are formed using the electrolytic plating method.
Since the bumps can be formed on the pads 18, the bumps can be formed on the pads 18 without forming the UBM.

For use as a common electrode for electrolytic plating, it is desirable to use a wiring material having a sufficiently low resistance so as not to cause a voltage drop between the central portion and the peripheral portion of the wafer. Further, in order to supply electricity to the wiring 14 on the scribe line 12, the passivation film is etched to expose the surfaces of all the pads 18, and at the same time, the electrode portion or the scribe line 12 described above is exposed.
It is preferable to expose a part or all of the upper wiring 14. Further, although an example in which the reticle 10 includes four LSI chips 16 is shown, the number of LSI chips 16 formed in the reticle 10 is not particularly limited.

In the wafer in which the bumps are formed on the pads 18 in this manner, all the LSI chips 16 are commonly connected by the wirings 14 formed on the scribe lines 12, so a probe test is performed in the wafer state. It cannot be done or operated. However, when all the pads 18 are exposed by etching the passivation film, all the wirings 14 on the scribe lines 12 are exposed at the same time, and bumps are formed on the pads 18 in the same manner as in the conventional UBM etching process. After forming,
By removing the wiring 14 on the scribe line 12 by etching, all the LSI chips 16 and all the pads 18 are electrically separated at the stage when all the manufacturing steps of the LSI chip 16 are completed. As in the conventional case, it is possible to perform a probe test or the like on each LSI chip 16 in a wafer state.

Even if the wiring on the scribe line 12 is not removed by etching, when dicing to individually separate the LSI chips 16 formed on the wafer,
The width of the wiring 14 on the scribe line 12 is wider than the width of the scribe line 12, that is, the width of the wiring 14 on the scribe line 12 or more is completely scraped off. By disconnecting, all the LSI chips 16 are disconnected and all the pads 18 are also electrically disconnected.
It can be used exactly as before. In this case, in a state where the LSI chips 16 are individually separated,
Alternatively, a test or the like can be performed after the LSI chip 16 is assembled, and two steps of the UBM forming step and the UBM etching step can be omitted.

Next, FIGS. 2 (a) to 2 (d) and 3 (e) to
The method for manufacturing the bump of the present invention will be described more specifically with reference to the sectional process diagrams shown in (g) and FIGS. 4 (h) to (j).

First, as shown in FIG. 2A, after forming an interlayer insulating film 22 on the wafer 20, this is selectively etched to expose the scribe line 12. Subsequently, as shown in FIG. 2B, after the wiring layer 24 is deposited on the entire surface of the wafer 20, a photoresist 26 is formed on the wiring layer 24 as shown in FIG. 2C. Then, the wiring layer 24 is selectively etched to form the wiring 14 on the internal wiring, the pad 18 and the scribe line 12, as shown in FIG. At this stage, each pad 18 is connected to the internal circuit, and the wafer 20 is connected via the wiring 14 on the scribe line 12.
All pads 18 of all LSI chips 16 formed above are commonly connected. Then, as shown in FIG. 3E, the passivation film 2 is formed on the entire surface of the wafer 20.
8 is formed, a photoresist 30 is formed on the passivation film 28 as shown in FIG.
As shown in FIG. 3G, the passivation film 28 is etched to form the pad 18 and the scribe line 12.
The entire upper wiring 14 is exposed. Then, FIG. 4 (h)
As shown in FIG. 4, a photoresist 32 is formed in a region other than the pad 18, and as shown in FIG. 4I, electricity is supplied to all the pads 18 via the wiring 14 on the scribe line 12 to perform electrolysis. After the bumps 34 are formed on the pads 18 by using the plating method, the photoresist 32 is removed.
Finally, as shown in FIG. 4 (j), the bumps 34 and the wirings 14 on the scribe lines 12 are etched back,
The wiring 14 on the scribe line 12 is removed, and the manufacturing process of the bump 34 is completed.

[0032]

As described above in detail, in the bump manufacturing method of the present invention, in the step of forming the pad, the wiring having the adhesion to the bump and the layer serving as the antireflection film is the outermost layer. A layer is formed and patterned to form pads, and wiring is also formed on the scribe line using the same wiring layer to electrically connect all pads of all LSI chips formed on the wafer. After connecting in common, a photoresist is formed on the entire surface of the wafer, and this is patterned to expose only the surface of all pads, and all the LSI chips on the wafer are exposed through the wiring on the scribe line. Electricity is supplied to the pads, and bumps are formed on all the pads by electrolytic plating. Therefore, according to the bump forming method of the present invention,
Since the UBM forming step and the UBM etching step can be omitted, the bump manufacturing cost and manufacturing step can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic plan view of an embodiment of a reticle to which the bump manufacturing method of the present invention is applied.

2A to 2D are cross-sectional process diagrams of an embodiment of the bump manufacturing method of the present invention.

3 (e) to (g) are cross-sectional process diagrams of an embodiment of the bump manufacturing method of the present invention.

4 (h) to (j) are sectional process drawings of an embodiment of the bump manufacturing method of the present invention.

5A to 5C are cross-sectional process diagrams of an example of a process of forming a wiring having a laminated structure.

FIG. 6 is a schematic plan view of an example of a wafer on which an LSI chip is formed.

FIG. 7 is a schematic plan view of an example of a reticle.

8A and 8B are a schematic plan view of an example of an LSI chip and an enlarged plan view of a pad portion thereof, respectively.

9A to 9F are sectional process drawings of an example of a conventional bump manufacturing method.

[Explanation of symbols]

 10, 48 Reticle 12 Scribe line 14 Wiring 16 LSI chip 18 Pad 20 Wafer 22, 64 Interlayer insulating film 24 Wiring layer 26, 30, 32 Photoresist 28 Passivation film 34 Bump 36 Lower layer wiring 38 Connection hole 40 Barrier metal (adhesion layer) 42 Aluminum / Copper Wiring 44 Antireflection Film 46 Upper Layer Wiring (Layered Wiring) 50 Internal Circuit 52 UBM (Under Bump Metal) 54 N Well Region 56 P Well Region 58 Source Region 60 Drain Region 62 Gate Electrode

Claims (3)

[Claims] 1. A wiring layer is formed on the entire surface of a wafer, the wiring layer having adhesion to bumps and having a layer serving as an antireflection film as an outermost layer, and subsequently, the wiring layer is patterned,
At least a pad is formed for each LSI chip formed on the wafer, and wiring is formed on the scribe line and between the scribe line and the pad, and on the wafer via the wiring on the scribe line. Electrically connecting all the pads of all the LSI chips, then forming a passivation film on the entire surface of the wafer, and subsequently patterning the passivation film to expose at least all the pads, After forming a photoresist on the entire surface of the wafer, patterning the photoresist to expose all the pads, and supplying electricity to all the pads through the wiring on the scribe line, and electroplating. After forming bumps on all the pads by the method, Method for manufacturing a bump and removing the strike. 2. The bump forming method according to claim 1, further comprising etching back the entire surface of the wafer to remove the wiring on the scribe line. 3. The method for forming bumps according to claim 1, wherein the LSI chip is separated by completely removing a region equal to or smaller than the width of the scribe line and equal to or larger than the width of the wiring on the scribe line.