JPH08154108A - Automatic frequency control circuit - Google Patents

Abstract

PURPOSE: To improve the pull-in accuracy of an automatic frequency control circuit and to prevent erroneous pull-in. CONSTITUTION: This automatic frequency control circuit of a quasisynchronous demodulator is provided with a first digital frequency discriminator 10 for fine adjustment whose accuracy of frequency analysis is relatively high and frequency analysis speed is relatively slow for inputting digital signals from an orthogonal transformer 1 discriminating the frequency and performing smoothing, a second digital frequency discriminator 11 for coarse adjustment whose accuracy of the frequency analysis is relatively low and frequency analysis speed is relatively fast for inputting the digital signals, a pull-in state detection part 12 for inputting the digital signals, detecting synchronization symbols, detecting the pull-in state of the frequency and judging the changeover of a switch 9. A control signal adjustment part switches input signals to a variable frequency oscillator 2 for the change of the output signals of the first digital type frequency discriminator 10 or the second digital type frequency discriminator 11 corresponding to the frequency pull-in state and changes the frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to an automatic frequency control circuit of a receiver using a plurality of subcarrier signals, but it can be applied to a single carrier signal. An example of the field of use is a digital MCA system.

[0002]

2. Description of the Related Art In land mobile communications, multi-valued QAM (Quadrature Amplitude Modulation: Quadrature A) is used to make effective use of frequencies.
mplitude modulation) method has been proposed. In this land mobile communication QAM, quasi-synchronous demodulation is generally performed in which the carrier is not reproduced on the receiver side and detection is performed based on a local signal oscillator that operates independently on the receiver side. In this quasi-synchronous demodulation, there is a frequency offset between the local oscillators on the transmitter side and the receiver side. In order to remove this offset, the AFC (Automatic Fr.
equency Controller) is used.

FIG. 34 is a diagram showing an example of a conventional automatic frequency control circuit which doubles as an analog type frequency discriminator and a digital type frequency discriminator. The same reference numerals or symbols used throughout the drawings are the same components. As shown in the figure, the automatic frequency control circuit pulls in the local oscillation frequency with respect to the frequency of the received signal. The input signal having the frequency deviation of the local oscillation frequency with respect to the frequency of the received signal is input to the I-axis signal and the Q-axis signal. An orthogonal transformer 1 for performing orthogonal transformation to separate into a signal and a signal is provided. The variable frequency oscillator 2 is connected to the quadrature converter 1 and converts directly to the base band, or once converted to the intermediate frequency and then converted to the base band. Further, the loop filter 3 connected to the variable frequency oscillator 2 is composed of a low pass filter having a constant time constant and extracts a DC component. The orthogonal frequency converter 1 is provided with an analog frequency discriminator 4. Furthermore, an A / D converter 5 (Analog to
A digital converter) and a digital type frequency discriminator 6 are provided. Further, the pull-in state detector 7 provided in the orthogonal converter 1 adds a known signal to the beginning of a slot which is a transfer unit called a sync symbol in M16QAM, for example. To detect. The output of the digital type frequency discriminator 6 has a D / A converter 8 (Digital to Analog Con
verter) is provided. The switch 9 for selectively connecting the outputs of the analog type frequency discriminator 4 and the D / A converter 8 to the input of the loop filter 3 is switched by the pull-in state detector 7 to change the output of the analog type frequency discriminator 4 from the output. It is realized by holding. In the analog type frequency discriminator 4 and the digital type discriminator 6, the polarities of the outputs thereof change between positive and negative as the center frequency deviates from the center of the S-shaped characteristic of the discriminator. As described above, the analog type frequency discriminator 4 and the digital type frequency discriminator 6 are selectively used because the analog type frequency discriminator 4 has a fast pull-in but low precision, and the digital type frequency discriminator 6 has a slow pull-in but has a low precision. Since it is good, the analog type frequency discriminator 4 first pulls in the coarse adjustment, and the digital type frequency discriminator 6 pulls in the fine adjustment when it is pulled in to some extent.

[0004]

By the way, the resonance circuit used for the analog type frequency discriminator 4 is generally within a range of a normal operating temperature (for example, -20 ° to 60 ° C) ± 10.
It has a temperature characteristic of 0 ppm. For example, if the resonance circuit has a temperature characteristic of ± 300 ppm when discrimination processing is performed at a relatively low intermediate frequency of 20 MHz, a deviation of up to 6 kHz will occur even in the absence of noise, and there will be a difference of about 10 and several kHz. It is out of the practical range for mobile communication with the band. Therefore, when using a very low intermediate frequency of 455 kHz, the resonance circuit becomes ± 300p.
Assuming that it has pm temperature characteristics, the maximum deviation is 140
Although it becomes about Hz, after passing the normal bandpass filter,
It is often input to the discrimination circuit, and the deviation of the center frequency in the normal operating temperature range of the band-pass filter generally used in the 455 kHz band is ± 1 kHz or more. Due to this influence, the maximum deviation of the discrimination frequency is It becomes 500Hz or more. However, this value has a maximum deviation of 200 to 300 Hz in mobile communication of a relatively narrow band,
Since it is desired to achieve the accuracy of the digital type frequency discriminator within ± 100 Hz, there is a problem that it cannot be said to be a sufficient value for coarse frequency adjustment. Furthermore, since a device different from the digital processing part is required, it is inevitable that the device becomes large and expensive.

Next, in the pull-in state detector 7, even if the frequency deviation of the sync symbol is large, it is detected, which causes erroneous pull-in. If the threshold value of the sync symbol is decreased to avoid erroneous pull-in, the detection characteristic is improved. There is a problem of deterioration. Here, the synchronization symbol is
This is a known signal for acquiring reception synchronization, and is added to the beginning of the slot that is the transfer unit. When this problem is achieved, it is desired to reduce the circuit size and bit error rate.

Accordingly, the present invention has been made in view of the above problems.
An object of the present invention is to provide an automatic frequency control circuit which can improve the pulling-in accuracy at the time of coarse adjustment, prevent erroneous pulling-in, downsize the circuit, and reduce the bit error rate.

[0007]

In order to solve the above problems, the present invention provides an automatic frequency control circuit having the following configuration. That is, in the automatic frequency control circuit of the quasi-synchronous demodulator, a quadrature converter that performs a quadrature conversion to a base band in which the center of the frequency component of the input signal that is a composite signal of a plurality of subcarriers is 0 Hz, and the frequency is controlled by the control signal. And a variable frequency oscillator for controlling and supplying an oscillating output to the quadrature converter. The first digital type frequency discriminator inputs the digital signal obtained by converting the output of the orthogonal transformer and performs frequency discrimination to smooth the result. However, the frequency analysis is relatively high in accuracy and the frequency analysis is performed. The speed is relatively slow and it is used for fine adjustment. The second digital type frequency discriminator inputs the digital signal obtained by converting the output of the orthogonal transformer, performs frequency discrimination, and smoothes the result.
It is used for coarse tuning, which has relatively low frequency analysis accuracy and relatively high frequency analysis speed. The switch switches between the first digital type frequency discriminator and the second digital type frequency discriminator and converts the output signal thereof into an analog signal to be a control signal of the variable frequency oscillator. The pull-in state detection unit receives the digital signal obtained by converting the output of the orthogonal transformer, detects the sync symbol, detects the pull-in state of the frequency from this detection, and determines the switch switching from this state. The control signal adjusting unit supplies the variable frequency oscillator to the variable frequency oscillator according to the change of the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator according to the frequency pulling state of the pulling state detecting unit. The frequency of the output signal is changed by switching the input signal.

The control signal adjusting section responds to a change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator in accordance with the frequency pulling state of the pulling state detecting section. The response time of the input signal to the variable frequency oscillator may be switched. The control signal adjustment unit is configured to change the output frequency of the first digital frequency discriminator or the second digital frequency discriminator according to the frequency pull-in state of the pull-in state detector. The frequency of the output signal is changed by switching the input signal to the first digital frequency discriminator or the second digital type frequency discriminator.
The response time of the input signal to the variable frequency oscillator may be switched in response to the change in the output signal of the digital frequency discriminator.

The first digital frequency discriminator is
Frequency discrimination of frequency deviation may be performed using only known symbols having a constant amplitude. The first digital frequency discriminator may discriminate the frequency deviation based on the signal point arrangement of known symbols in each subcarrier and the arrangement in the slots.

The second digital frequency discriminator is
A plurality of subcarrier separation units for extracting a band substantially equal to the bandwidth of the information transmitted on each carrier, with the vicinity of the center of each subcarrier converted to the base band being 0 Hz, and each output of the plurality of subcarrier separation units May be provided with a frequency discriminating section for discriminating frequency around 0 Hz, and a switch for selectively selecting the output of the frequency discriminating section.

The second digital frequency discriminator is
Two bands that are narrower than the bandwidth of the input signal near the upper end and the lower end of the frequency component of the signal converted to the base band are extracted so that their centers are 0 Hz. 2
It may be provided with one spectrum separating section, two frequency discriminating sections for discriminating the respective outputs of the respective spectrum separating sections around 0 Hz, and a switch for selectively selecting the two outputs of the frequency discriminating section. .

The pull-in state detecting section outputs the control signal of the variable frequency oscillator from the second digital type frequency discriminator to the first signal when a predetermined time has elapsed after detecting the known symbol.
The switch may be switched so as to be the output of the digital type frequency discriminator. Even if the pull-in state detecting unit switches the switch so that the control signal of the variable frequency oscillator becomes the output of the first digital type frequency discriminator from the second digital type frequency discriminator when the synchronization symbol is detected a certain number of times. Good.

The pull-in state detecting unit detects a known symbol, and when the absolute value of the vector rotation between two or more known symbols is less than a fixed value, the control signal of the variable frequency oscillator outputs the second digital frequency signal. The switch may be switched from the discriminator to the output of the first digital frequency discriminator. The quadrature converter may convert the signal to an intermediate frequency and then to a base band.

[0014]

According to the automatic frequency control circuit of the present invention, since the second digital type frequency discriminator is used for coarse adjustment, frequency discrimination accuracy and speed can be improved. Since no special device is required as the second digital type frequency discriminator, it is possible to achieve miniaturization and low cost as compared with the conventional one. The input signal to the variable frequency oscillator is switched according to the change in the output signal of the first digital frequency discriminator or the second digital frequency discriminator according to the frequency pull-in state of the pull-in state detector. By changing the frequency that is the output signal, the frequency variable width at the time of coarse adjustment is f
If W is the frequency variable width fL during fine adjustment, the minimum control frequency width is switched at the ratio of fW: fL, and the higher the detection accuracy of the pull-in state, the higher the precision control becomes possible, and the resolution Since a low D / A converter can be used, high frequency accuracy can be achieved at low cost.

The control signal adjusting section responds to a change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator in accordance with the frequency pulling state of the pulling state detecting section. By switching the response time of the input signal to the variable frequency oscillator, that is, by increasing the integration time constant during fine adjustment, making the change in the control signal slower than during coarse adjustment, and changing the frequency change per hour. As a result, the adverse effect on the bit error rate due to the digital modulated wave can be reduced. Also,
It can be realized with a simple configuration.

The control signal adjusting section is responsive to a change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator according to the frequency pulling state of the pulling state detecting section. The frequency of the output signal is changed by switching the input signal to the variable frequency oscillator, and the variable according to the change of the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator. By switching the response time of the input signal to the frequency oscillator, the higher the detection accuracy of the pull-in state is, the more accurate control becomes possible, and the adverse effect on the bit error rate due to the digital modulation wave can be reduced. . Further, it can be realized with a simple configuration.

The first digital type frequency discriminator is
By performing frequency discrimination of frequency deviation using only known symbols with constant amplitude, it is possible to remove the modulation signal, which has been a hindrance to accuracy improvement, and it becomes possible to easily process only the information according to frequency deviation. It was The first digital type frequency discriminator discriminates the frequency deviation based on the signal point arrangement of the known symbols on each sub-carrier and the arrangement in the slot, thereby facilitating the frequency discrimination processing of the frequency deviation. Become.

In the second digital frequency discriminator, 0H is generated near the center of each subcarrier converted into the base band.
A band substantially equal to the bandwidth of information transmitted by each carrier is extracted as z, each output of the plurality of subcarrier separation units is frequency discriminated around 0 Hz, and the output of the frequency discrimination unit is alternatively selected. By doing so, the pulling speed can be increased.

In the second digital type frequency discriminator, two bands narrower than the bandwidth of the input signal are located at the centers near the upper end and the lower end of the frequency component of the signal converted to the base band. The output of each spectrum separation unit is extracted so as to be 0 Hz, and each output of each spectrum separation unit is subjected to frequency discrimination around 0 Hz, and two outputs of the frequency discrimination unit are selected alternatively, whereby the pull-in can be speeded up. .

The pull-in state detection unit further detects a synchronization symbol when a predetermined time has elapsed after detecting the synchronization symbol and when the synchronization symbol is detected a predetermined number of times, and a vector between two or more synchronization symbols. When the absolute value of rotation is less than a certain value, the control signal of the variable frequency oscillator is switched from the second digital type frequency discriminator to the output of the first digital type frequency discriminator, thereby deteriorating the synchronization detection. It also prevents erroneous pull-in.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an automatic frequency control circuit according to an embodiment of the present invention. As shown in the figure, first, the digital type frequency discriminator (fine adjustment) 10 corresponds to the digital frequency discriminator 6 of FIG. 34 and has a built-in loop filter. Along with this, a configuration different from that of FIG. 34, that is, a digital type frequency discriminator (coarse adjustment) 1
1. The pull-in state detection unit 12 will be described. In addition,
The digital type frequency discriminator (fine adjustment) 10, the digital type frequency discriminator (coarse adjustment) 11, and the pull-in state detection unit 12 are configured by a DSP (Digital Signal Processor), and the digital type frequency discriminator (coarse adjustment) 11 is provided separately. It is possible to reduce the size and cost without the need for a device.

The input signal to the orthogonal transformer 1 will be described. FIG. 2 is a diagram showing a spectrum arrangement of M16QAM as an example of a modulation signal using four carriers. As shown in this figure, the subcarrier 1 has a frequency of −6.75 kHz.
z, subcarrier 2 is −2.25 kHz, subcarrier 3 is +
2.25 kHz, subcarrier 2 has a frequency arrangement of +6.75 kHz.

FIG. 3 is a diagram showing the arrangement of symbol signals of each subcarrier. As shown in the figure, each subcarrier has a synchronization symbol, a pilot symbol, and a data symbol, and the symbol rate is 4 kHz. Here, the synchronization symbol and pilot symbol have different phases but the same amplitude. FIG. 4 is a diagram showing the digital type frequency discriminator (fine adjustment) 10 of FIG. As shown in the figure, the digital type frequency discriminator (fine adjustment) 10 performs frequency discrimination processing only on the synchronization symbol 2 and the pilot symbol shown in FIG. does not process. In this way, if the modulation component is considered as a kind of fading during tracking that performs fine adjustment, this will be removed, so that it is possible to prevent variations in tracking characteristics. Further, since the calculation process may be performed for each synchronization symbol and pilot symbol, the processing amount can be reduced.

Next, in the configuration, the digital type frequency discriminator (fine adjustment) 10 has two subcarrier separating units 101 for separating the subcarriers 1 and 4 or the subcarriers 2 and 3. FIG. 5 is a diagram showing the subcarrier separation unit 101 of FIG. As shown in the figure, the subcarrier separation unit 101 includes a multiplication unit 501 and a subcarrier local oscillation unit 502, and converts an input signal so that the frequency center of the subcarrier is 0 Hz.

Next, the two low pass filters 102 connected to the subsequent stage of the sub-carrier separation unit 101 remove the converted high frequency components. FIG. 6 shows the symbol reverse rotation unit 1 of FIG.
It is a figure which shows 03. As shown in the figure, each of the two symbol inverse rotation units 103 has a multiplication unit 503 and a known symbol inverse rotation vector generation unit 504.

FIG. 7 is a diagram for explaining the operation of the symbol reverse rotation unit 103 of FIG. As shown in this figure (a), the phase of the synchronization symbol 2 of each subcarrier 1 and 4 is -112.5.
And + 112.5 °, as shown in FIG.
The phase of the pilot symbols of each subcarrier 1 and 4 is -2.
They are 2.5 ° and + 22.5 °. Symbol reverse rotation unit 10
3 rotates the sync symbol 2 of each sub-carrier 1 and 4 in the opposite direction to match the I-axis. Similarly, as shown in the figure (c), the phases of the synchronization symbols 2 of the subcarriers 2 and 3 are -157.5 ° and + 157.5 °, respectively.
As shown in, the phase of the pilot symbols of each subcarrier 2 and 3 is -112.5 ° and + 112.5 °. The symbol reverse rotation unit 103 rotates the synchronization symbol 2 of each subcarrier 2 and 3 in the opposite direction so that the synchronization symbol 2 coincides with the I axis.

Next, a digital type frequency discriminator (fine adjustment)
10 has an addition unit 104 that adds the outputs of the two symbol inverse rotation units 103. If there is no phase error between the synchronization symbol 2 and the pilot symbol, the output of the adder 104 is zero. FIG. 8 is a diagram for explaining the output of the addition diagram 104 in FIG. The two vector signals OA and OB output from the reverse rotation unit 103 are affected by noise. The output of the addition unit 104 is a vector OC that can detect the rotation polarity more accurately from the vectors OA and OB.

Next, a digital type frequency discriminator (fine adjustment)
10 has a frequency discriminating unit 105 of the direct cross product type, which is connected to the adding unit 104, and has a phase error of 2πΔ.
Discriminate f. The frequency discriminating unit 105 has two delay units 505 and 50 for delaying one clock τ.
6. I-axis signal or Q delayed by one clock
Two multiplication units 507 and 508 for multiplying the axis signal and the undelayed Q-axis signal or I-axis signal, respectively, and a subtraction unit 50 for calculating an output difference between the two multiplication units 507 and 508.
8 and a polarity determination unit 509 that determines the polarity of the output of the subtraction unit 508.

Next digital frequency discriminator (fine adjustment) 1
0 is a random walk filter 106 that constitutes the loop filter 3 connected to the output of each frequency discriminating unit 105.
And an up / down counter 107. The random walk filter 106 has an internal register, which is “0” in the initial state, and when a + signal is input for each clock signal, the internal register is incremented by “+1”, − When a (minus) signal is input, the internal register is counted down by "-1" for each clock signal. The random walk filter 106 further has a threshold value ± TH, and when the count value C of the internal register is lower than −TH, DOWN.
The signal ("-1") is output and the internal register is cleared. When the count value C exceeds TH, the UP signal (“+1”) is output and the internal register is cleared.
In this way, the frequency polarity signal is smoothed. The up / down counter 107 connected to the random walk filter receives “+” in the plus direction each time the UP signal is input.
The count value is incremented by 1 ", the count value is decremented by" -1 "in the minus direction each time the DOWN signal is input, and the count value is changed from a predetermined initial value to a large or small value according to the output of the random walk filter 106. The D / A converter 8 connected to the up / down counter 107 converts the digital value of the count of the up / down counter 107 into an analog voltage, and controls the frequency of the variable frequency oscillator 2 based on the converted analog voltage. Here, the higher the converted analog voltage is, the lower the frequency is, and the lower the converted analog voltage is, the higher the frequency is controlled to form the negative feedback loop.

FIG. 10 is a graph showing the pull-in characteristic of the digital frequency type discriminator (fine adjustment) 10 of FIG. As shown in this figure, it is clear that even under the conditions of fading and noise, it is surely pulled in and the followability is excellent.
FIG. 11 shows the digital type frequency discriminator (fine adjustment) 10 of FIG.
It is a figure which shows another example of. As shown in the figure, the subcarriers 1 and 4 or the subcarriers 2 and 3 are alternately switched to 4
Calculation processing is performed for each symbol, but the amount of rotation is ±
Since it can detect up to 180 °, ± 4kHz / 4/2 = ±
It is possible to pull up to 500 Hz, and the accuracy can be improved compared to the conventional case.

FIG. 12 is a diagram showing the digital type frequency discriminator (coarse adjustment) 11 of FIG. As shown in the figure, the digital type frequency discriminator (fine adjustment) 10 includes a subcarrier 1,
Four subcarrier separation units 201 for separating 2, 3 and 4
And four low-pass filters 2 that are connected to the subsequent stage of the subcarrier separation unit 201 and remove the converted high-frequency components.
02, a frequency discriminating unit 203 which is connected to the low-pass filter 202 and is of a direct cross product type, and a switch 204 for selecting the output of the four frequency discriminating units 204,
It has a random walk filter 206 and an up / down counter 207 that constitute the loop filter 3 connected to the subsequent stage of the switch 204. Here, the configurations of the subcarrier separating unit 201, the frequency discriminating unit 203 and the like are the same as those of the subcarrier 101 and the frequency discriminating unit 105 shown in FIG.

FIG. 13 is a diagram showing the frequency relationship of FIG. The operation of an example of outputting the polarity of the output of the frequency discriminating unit 203 to the loop filter 3 will be described with reference to this figure. FIG.
3 (a) shows the spectrum of the modulated signal only, and FIG.
(B) ,,, indicate the band characteristics of each subcarrier. FIG. 13C shows the spectrum of the input signal after each subcarrier separation. The output of each frequency discriminating unit 203 is shown in FIG.
This corresponds to the area of the four shaded areas in 3 (c). On the other hand, since the noise component is ,, in FIG. 13B, the value corresponding to the noise ratio of the frequency discrimination unit 203 is 1.
The value is smaller than / 3 by the amount of a, b, and c in the figure, which is larger than the conventional value of 1/15. Therefore, the pull-in time is shortened. Even if there is no noise, the shaded area becomes a little less than four times, so that the speed can be increased.

Further, it becomes strong against erroneous pull-in due to a strong signal of the adjacent channel. Note that the subcarrier separation unit 201 in FIG. 12 is also required for signal demodulation itself (not shown) in M16QAM, and thus can be used in common with this. Further, if the frequency discriminating unit 203, the switch 204, the loop filter 3 and the like are realized by the calculation of the processor, the increase in the calculation amount of the automatic frequency control circuit with respect to the processing amount of the demodulation unit is slight.

As a modification of FIG. 12, the order of the switch 204 and the loop filter 3 can be exchanged. Up to this point, the speed-up of the automatic frequency control circuit for a plurality of sub-carriers has been described, but when it is applied to a single-carrier modulation method, it is considered that the drop of the spectrum in the band is not smoothed. , The reduction of the noise band becomes available as follows.

FIG. 14 is a diagram showing another modification of FIG. In this figure, the difference from the configuration of FIG. 12 is a spectrum separation section 301. This spectrum separation unit 301
Is two bands narrower than the bandwidth of the input signal near the upper end and near the lower end of the frequency component of the signal converted into the base band by the orthogonal transformer 1, so that the center of each band is 0 Hz. To do. The two frequency discriminators 302 in the subsequent stage of each spectrum separation unit 301 discriminate frequency with 0 Hz as the center. The switch 303 selectively selects the outputs of the two frequency discriminators 202, as in FIG.
Switch sequentially, and then add.

FIG. 15 is a diagram showing the frequency relationship of FIG. As shown in the figure, as in the above description, the value corresponding to the ratio of the output of the frequency discriminator 302 to the noise is 2/15 (≈0.13) in the conventional method, 1
/ 6 (≈0.17), indicating that the pull-in time can be improved when there is a lot of noise. It should be noted that when the amount of noise is small, the present embodiment alone has an adverse effect, but by combining with the conventional technique, it is possible to speed up the pull-in in the entire C / N range.

The configuration and effects will be described in detail below with reference to computer simulation examples. The simulation used M16QAM as an example of four subcarriers. The main parameters of the simulation are shown in Table 1 below.

[0038]

[Table 1] Next, the result of the simulation will be described. FIG. 16 is a graph showing the pull-in characteristic in the case of the conventional analog type frequency discriminator 4 of FIG. As shown in this figure, in the conventional analog type frequency discriminator 4, the deviation of the local frequency is large, and it is difficult to keep it within the target deviation (approximately ± 100 Hz).

FIG. 17 is a graph showing the pull-in characteristic when the automatic frequency control is calculated with the subcarrier separation signal according to the embodiment of the present invention. This figure (a) shows the pull-in characteristic when only the subcarrier 1 separation is used. In this case, it takes 0.80 seconds to reach the range of approximately ± 100 Hz. This figure (b) shows the pull-in characteristic when only the subcarrier 2 separation is used. In this case, approximately ± 100Hz
It takes 0.68 seconds to reach the range. This figure (c) shows the pull-in characteristic when only the subcarrier 3 separation is used. In this case, it takes 0.83 seconds to reach the range of approximately ± 100 Hz. This figure (d) shows the pull-in characteristic when only the subcarrier 4 separation is used.
In this case, it takes 0.41 seconds to reach the range of approximately ± 100 Hz. Therefore, no matter which subcarrier is used, the pulling-in is faster than in the conventional case, and thus it may be alternatively selected. Furthermore, you may switch sequentially. In this case, there is an effect that the amount of calculation becomes relatively smaller. The reason why the drawing-in time is the shortest in the figure (d) is as follows.

FIG. 18 is a diagram showing the frequency relationship between the input signal and the baseband signal. This is because the local frequency is shifted upward due to the input signal as shown in the figure, and the spectrum on one side is deleted. Subcarrier separation 1 to 3
Part of the input signal spectrum of the input signal spectrum of the sub-carrier separations 2 to 4 is shifted into the band of. Therefore, if the subcarrier 4 separation is used, the pull-in can be speeded up.

However, this is the case where the local frequency is biased to the upper side, and it is not known which one is actually biased. Therefore, in one sample, by adding the rotation direction output between the samples to the loop filter 3 in combination with the subcarrier 1 separation and the subcarrier 4 separation, the local frequency deviation above and below can be pulled in quickly. ,
Will be possible.

FIG. 19 shows a subcarrier 1 separated signal and a subcarrier 4
It is a figure which shows the pull-in characteristic at the time of switching combining with a separation signal. As shown in this figure, approximately ± 100 Hz
It takes 0.29 seconds to reach the range. FIG.
Even with 7 (d), pulling in becomes a little faster. It is also possible to sequentially switch between the separation of subcarrier 1 and the separation of subcarrier 4. In this case, the pull-in time is slightly longer than the above, but the amount of calculation is relatively small.

FIG. 20 shows subcarrier 1 separated signal, subcarrier 2
It is a graph which shows a pull-in characteristic at the time of switching by combining a separation signal, a subcarrier 3 separation signal, and a subcarrier 4 separation signal. As shown in this figure, it takes 0.18 seconds to reach the range of approximately ± 100 Hz. FIG. 17
Due to (d), pulling in becomes a little faster. However, the calculation amount is relatively larger than that in the case of FIG. 34, but the pull-in reduction ratio is small.

Although the simulation of the modification of FIG. 14 is omitted, this effect can be similarly explained.
FIG. 21 is a diagram for explaining the pull-in state detection unit 12 of FIG. As shown in the figure, the rotation complex vector calculation unit 80
Then, EXP (jω _s · n · T _M ) is calculated. Here, EXP (x) means the low e to the power of x of natural logarithm, j means an imaginary unit, ω _s : angular frequency serving as a base of each subcarrier, n: variable, T _M : sampling period (T _M = T _S / K _S , T _S : symbol transfer interval, K _S : constant).

[0045] The complex conjugate unit 81, a complex conjugate of the rotating complex vector computing unit 80, that is, EXP (-jω _s · n ·
T _M ) is calculated. The multiplication means 82 multiplies the sampling data from the A / D converter 5 and the output of the complex conjugate section 81. The multiplication result is input to the low pass filter 84. In the low pass filter 84, signal processing having a base band filter characteristic is performed.

The multiplying means 86 multiplies the output of the low-pass filter 84 and the rotating complex vector calculator 80. The multiplication result s ′ ₃ (p + 2k) is stored as a sample selection. In the multiplying means 83, the sampling data from the A / D converter 5 which inputs s (t) is multiplied by the rotating complex vector calculating section 80. The multiplication result is input to the low pass filter 85. The low pass filter 85 performs signal processing having a base band filter characteristic.

The multiplication means 87 multiplies the output of the low pass filter 85 and the complex conjugate section 81.
The multiplication result s ′ ₂ (p + 2k) is stored as a sample selection. In the rotation complex vector calculation unit 90, EXP (3
jω _s · n · T _M ) is calculated.

In the complex conjugate section 91, the complex conjugate section of the rotation complex vector calculation section 90, that is, EXP (-3jω _s ·
n · T _M ) is calculated. In the multiplication means 92, the A /
The sampling data from the D converter 5 and the complex conjugate unit 91 are multiplied. The multiplication result is input to the low pass filter 94. The low pass filter 94 performs signal processing having a base band filter characteristic.

The multiplying means 96 multiplies the output of the low-pass filter 94 and the rotating complex vector 90. The multiplication result s ′ ₄ (p + 2k) is stored as a sample selection. In the multiplication means 93, the sampling data from the A / D converter 5 and the rotation complex vector calculation unit 9 are used.
Multiplication with 0 is performed. The multiplication result is input to the low pass filter 95. The low-pass filter 95 performs signal processing having baseband filter characteristics.

In the multiplication means 97, the output of the low pass filter 95 and the complex conjugate 91 are multiplied. The multiplication result s ′ ₁ (p + 2k) is stored as a sample selection. Similarly, the multiplication results s ′ ₃ (p + k), s ′
₂ (p + k), s ′ ₄ (p + k), s ′ ₁ (p + k), the multiplication results s ′ ₃ (p), s ′ ₂ (p), s ′ ₄ (p), s ′
Find and memorize ₁ (p).

In the cancellation rotation calculation unit 401, each of the above powers is
Angular frequency cancellation rotation and phase cancellation in calculation results
The rotation is multiplied as follows to obtain the synchronization symbol.
Remember According to the M16QAM communication protocol, each slot is
Three sync symbols F1, F2, F3 are added to the beginning of the
The phase of the synchronization symbol F1 in the subcarrier order.
Ψ₁₁, Ψ₁₂, Ψ₁₃, Ψ₁₄, Sync symbol F₂, F₃The sub
The phase of carrier order is Ψ_{twenty one}, Ψ _{twenty two}, Ψ_{twenty three}, Ψ_{twenty four}, Ψ₃₁, Ψ
₃₂, Ψ₃₃, Ψ₃₄And

F33 = s ′ ₃ (p + 2k) · EXP (−2jω _s · T _S ) · EXP (−Ψ ₃₃ ) F32 = s ′ ₂ (p + 2k) · EXP (2jω _s · T _S ) · EXP (−Ψ) _{32) F34 = s '4 (} p + 2k) · EXP (-6jω s · T S) · EXP (-Ψ 34) F31 = s' 1 (p + 2k) · EXP (6jω s · T S) · EXP (-Ψ 31 _{) F23 = s '3 (p} + k) · EXP (-jω s · T S) · EXP (-Ψ 23) F22 = s' 2 (p + k) · EXP (jω s · T S) · EXP (-Ψ 22) F24 = s ′ ₄ (p + k) · EXP (−3jω _s · T _S ) / EXP (−Ψ ₂₂ ) F21 = s ′ ₁ (p + k) · EXP (3jω _s · T _S ) · EXP (−Ψ ₂₂ ) F13 = S ′ ₃ (p) · EXP (−Ψ ₁₃ ) F12 = s ′ ₂ (p) · EXP (−Ψ ₁₂ ) F14 = s ′ ₄ (p) · EXP (−Ψ ₁₄ ) F11 = s ′ ₁ ( p) ・ EXP (-Ψ ₁₁ ) The straight-line equal-interval computing unit 402 obtains the parameter eij indicating the straight-line regular intervals on the complex plane of the fading component as follows.

D1 ² = abs (F11) ² + abs (F12) ² + abs (F1
3) ² + abs (F14) ² D2 ² = abs (F21) ² + abs (F22) ² + abs (F23) ² + abs (F2
4) ² D3 ² = abs (F31) ² + abs (F32) ² + abs (F33) ² + abs (F3
^{4) 2 Δaa1 = F12-F11} , Δaa2 = F13-F12, Δaa3 = F14-F13, Δ 2 aa1 = Δaa2-Δaa1 Δ 2 aa2 = Δaa3-Δaa2 Δbb1 = F22-F21, Δbb2 = F23-F22, Δbb3 = F24 ^{-F23, Δ 2 bb1 = Δbb2-} Δbb1 Δ 2 bb2 = Δbb3-Δbb2 Δcc1 = F32-F31, Δcc2 = F33-F32, Δcc3 = F34-F33, Δ 2 cc1 = Δcc2-Δcc1 Δ 2 cc2 = Δcc3-Δcc2 e11 ^{2 = abs (Δ 2 aa1)} 2 / D1 2 e12 2 = abs (Δ 2 aa2) 2 / D1 2 e21 2 = abs (Δ 2 bb1) 2 / D2 2 e22 2 = abs (Δ 2 bb2) 2 / D2 ² e31 ² = abs (Δ ² cc1) ² / D3 ² e32 ² = abs (Δ ² cc2) ² / D3 ² where abs (A) means the absolute value of the complex vector A. Assuming that the fading components for each subcarrier are exactly linearly spaced on the complex plane, the above parameters eij =
It becomes 0, and when it deviates from the straight-line equidistant relationship, the parameter eij takes a positive value.

In the level judgment unit 403, the constant storage unit 40
Constant α stored in 4²And the straight-line interval calculator 402
Parameter e11 obtained from², E12², E21², E22²,
e31 ², E32²Is the constant α²Less than
Otherwise, it outputs a signal that the synchronization has been detected. Add
Value is constant α²If not less than
Do not force In this way, the synchronization symbol detection threshold value α
By making it smaller, it is necessary to reduce false pull-in.
is there. However, by reducing the threshold value α, the following
The trade-off relationship that the synchronization detection characteristics deteriorate
Will occur.

FIG. 22 is a graph showing the synchronization detection characteristic. This figure (a) shows the synchronous detection characteristic in the state without fading and noise, and this figure (b) shows the synchronous detection characteristic in the state with fading and noise. Considering this figure, the detection threshold value α = 0.4 to 0.5 is considered appropriate, but with this α,
Even if the frequency deviation is 500 Hz or more, the probability of synchronous detection is high, and this synchronous detection method is used as it is for switching between the digital type frequency discriminator (fine adjustment) 10 and the digital type frequency discriminator (coarse adjustment) 11. Is dangerous.

Therefore, the timer 40 is added to the level decision unit 403.
5 is provided, and when a certain time has elapsed since the synchronization was first detected, it is considered that the synchronization has followed, the level determination unit 403 outputs a synchronization detection signal, and switches the switch 9. The set time of the timer 405 is set to a fixed time in consideration of the pull-in characteristics of FIGS. FIG. 23 is a diagram showing a modification of FIG. As shown in the figure, a counter 406 is provided in the level determination unit 403, and the level determination unit 403 regards the counter 406 as a follow-up state after a fixed number of synchronization detections.
Then, the synchronization detection signal is output from the switch and the switch 9 is switched. The reason for this counter 406 is that it is possible that the state will suddenly deteriorate after the first synchronization detection. In this case, it is expected that it will take a longer time than the example of FIG. 21 until the tracking state determination.

FIG. 24 is a diagram showing a rotation angle determination unit 407 between synchronization symbols which is another modification of FIG. In order to increase the reliability of the synchronization detection, as shown in the figure, the frequency deviation when the synchronization is detected is canceled by the cancellation rotation calculation unit 401.
Inferred from the vector rotation amount between the synchronization symbols 1-2 and 2-3, if there is a large deviation, a synchronization symbol rotation angle determination unit 407 is provided that keeps the drawing state without setting the tracking state. It should be noted that various modifications such as which sample to take and addition of a plurality of samples are possible. Here, the dividers 601 and 6 of the inter-synchronization symbol rotation angle determination unit 407.
02 has two vectors a + jb and c + j
If d, then division is performed as follows.

V = (c + jd) / (a + jb) = {(ac + bd) + j (ad-bc)} / (a ² + b ² ) The declination calculators 603 and 604 obtain the declination of v as follows. . ARG = tan ⁻¹ {(ad−bc) / (ac + bd)} The absolute value conversion units 605 and 606 take the absolute value of the ARG. The comparison units 608 and 609 compare the reference rotation angle r stored in the storage unit 607 with the outputs of the absolute value conversion units 605 and 606. The logical product section 610 which obtains the logical product of the outputs of the comparison sections 608 and 609 and the determination result of the level determination section 403 is provided only when the frequency deviation when the level determination section 403 performs synchronization detection is smaller than the rotation angle r. Level determination unit 4
A sync detection signal is output to the switch 03 to switch the switch 9.

FIG. 25 is a graph showing the synchronization detection rate when α is fixed in the middle of 0.4 and 0.5 and the reference rotation angle r is used as a parameter. This figure (a) shows the synchronous detection characteristic in the state without fading and noise, and this figure (b) shows the synchronous detection characteristic in the state with fading and noise. This figure (a)
Then, it can be understood that the case where the frequency deviation is large can be reliably rejected if the reference rotation angle r is appropriately set. This figure (b)
Then, it can be understood that the harmful follow-up determination can be set to 0 when the frequency deviation is 500 Hz or more, although the detection rate is slightly reduced at the reference rotation angle r × 2.

In the above ARG equation, it is not necessary to obtain a ² + b ² . Therefore, the conjugate complex number on one side may be multiplied instead of division. In this case, since it is sufficient to know the absolute value of the rotation angle, either conjugate may be multiplied. next,
Since the absolute value of the declination angle is determined to be the reference rotation angle r, it is not necessary to directly obtain the declination angle. It can be easily obtained by modifying the following formula.

−r <tan ⁻¹ {(ad−bc) / (ac + bd)} <r ↓ tan (−r) <(ad−bc) / (ac + bd) <tan (r) ↓ (ac + bd) tan (− r) <(ad-bc) <(ac + bd) tan (r) tan is an odd function, so ↓ ABS (ad-bc) <(ac + bd) tan (r) The amount of calculation can be reduced from these modifications, and after synchronization detection Since only one processing is required, the load is light and the implementation is easy.

FIG. 25 is a graph for explaining an example of the pull-in effect according to this embodiment. As shown in the figure, at the traveling speed of 100 km / h, the initial deviation of the frequency can be pulled from 1500 Hz to ± 62.5 Hz within 450 ms. By the way, in such a frequency control circuit,
The outputs of these frequency discriminators (fine adjustment, coarse adjustment) 10 and 11 pass through the D / A converter 8 and become the control signal of the variable frequency oscillator 2. Now consider the input signal considering a digital MCA system. Carrier frequency is 1500 MH
If the deviation is ± 1 ppm in z, the frequency variable width of the variable frequency oscillator needs to be about 4 kHz. When this is controlled using a relatively inexpensive 8-bit D / A converter, the minimum control frequency width is about 16 Hz. With this,
As shown in FIG. 1, even if the frequency discriminating method is switched, the frequency actually fluctuates at intervals of about 16 Hz, so that high-precision fine adjustment cannot be performed. Therefore, considering the fine adjustment, if the resolution of the D / A converter is increased, or if the D / A converters having different resolutions for the coarse adjustment and the fine adjustment are separately prepared, the device becomes large in size. There is a problem that it leads to higher prices.
Therefore, a low-resolution D / A converter can be used to adjust the frequency roughly.
Fine tuning needs to be possible at a small size and a low price as follows. Further, in a digitally modulated wave receiving apparatus using this method, if the frequency is changed stepwise at this frequency interval, the bit error rate is deteriorated.

FIG. 27 is a diagram showing an automatic frequency control circuit according to another embodiment of the present invention. In this figure, what differs from the configuration shown in FIG. 1 is that instead of the D / A converter 8, the first
D / A converter (during coarse adjustment) 14 and second D / A converter (during fine adjustment) 15, one of which is the first D / A converter (during coarse adjustment) 14 and the second D / A A resistor 16 (during coarse adjustment) and a resistor 17 connected to the output side of the A converter (during fine adjustment) 15, respectively
(During fine adjustment) and the pull-in state detection unit 12 outputs the output of the switch 9 to either the first D / A converter (during coarse adjustment) 14 or the second D / A converter (during fine adjustment) 15. A switch 18 for switching connection to the side, and the other of the resistor (during coarse adjustment) 16 and the resistor (during fine adjustment) 17 are connected to the input side, and the control signal adjusting unit 13 is connected to the variable frequency converter 2 on the output side. is there. Here, the first D / A converter (during coarse adjustment) 14 and the second D / A converter
Both D / A converters (during fine adjustment) 15 are inexpensive 8-bit digital / analog converters. If the resistance values of the resistance (during coarse adjustment) 16 and the resistance (during fine adjustment) 17 are R1 and R2, then R1≤R2.

FIG. 28 is a diagram showing the control signal adjusting section 13 of FIG. As shown in the figure, the control signal adjusting unit 13
Is a comparator 21 including an operational amplifier having a non-inverting terminal to which the reference voltage Vref is input, an inverting terminal to which the other of the resistors 16 and 17 is connected, and an output side connected to the variable frequency oscillator 2, and an inverting input terminal of the comparator 21. A capacitor 22 located between the outputs and a resistor connected in parallel with this capacitor 22.
It consists of 2 and 3. The control signal adjusting unit 13 constitutes an inverting amplifier together with a resistor (during coarse adjustment) 16 and a resistor (during fine adjustment) 17, and amplifies by switching the resistance values of the resistor (during coarse adjustment) 16 and the resistor (during fine adjustment) 17. The degree varies. That is, the amplification degree (during coarse adjustment) when connected to the resistor (during coarse adjustment) 16 is set to be larger than the amplification degree (during fine adjustment) when connected to the resistance (during fine adjustment) 17. This is because R1≤R2.

FIG. 29 shows the D / A converters 14 and 15 of FIG.
FIG. 6 is a diagram showing an output versus frequency change amount of FIG. As shown in the figure, the output voltage range of the D / A converter (during coarse adjustment) 14 and the D / A converter (during fine adjustment) 15 is the minimum voltage Vmin-
It is the maximum voltage Vmax, and the input voltage range of the variable frequency oscillator 2 during the rough adjustment is from V2 to V1 with respect to the reference voltage Vref.
And the output frequency is f2 to f1. At the time of fine adjustment, the input voltage range of the variable frequency oscillator 2 is V4 to V3 with respect to the reference voltage Vref, and its output frequency is f4 to f3.

In this way, D / is adjusted between the coarse adjustment and the fine adjustment.
A converter (during coarse adjustment) 14, D / A converter (during fine adjustment) 15
The inclination of the frequency of the variable frequency oscillator 2 with respect to the output voltage of 1 is switched between the pull-in time and the follow-up time. That is, assuming that the frequency variable width during coarse adjustment is fW and the frequency variable width during fine adjustment is fL, the minimum control frequency width is switched at a ratio of fW: fL, and the higher the detection accuracy of the pull-in state, the higher the accuracy. Can be controlled. Furthermore, since a D / A converter with low resolution can be used, high frequency accuracy can be achieved at low cost. In this case, 8-bit D
Two A / A converters will be used, but an 8-bit D
Compared to the case where two A / A converters (during coarse adjustment) and 16-bit D / A converters (during fine adjustment) are used, the cost is very low.

Further, the control signal adjusting section 13 has an integrating function by the capacitor 22, and the digital modulation wave which is the step-like output waveform of the D / A converters 14 and 15 becomes gentle. For this reason, it is possible to prevent the deterioration of the bit error with respect to the stepwise frequency change. Note that in FIG. 27, two D
Although the / A converters 14 and 15 are used, the output of the switch 9 is input to one D / A converter, and the resistors 16 and 17 are connected to the output side of the D / A converter by the pull-in state detection unit 12. Alternatively, they may be connected so as to be selected alternatively. In this case, a holding unit for holding the output voltage of the D / A converter is required when the resistors 16 and 17 are switched, but the number of D / A converters is one and the configuration is simpler.

FIG. 30 is a diagram showing an automatic frequency control circuit according to another embodiment of the present invention. As shown in FIG.
A control signal adjusting unit 13 is provided between the D / A converter 8 and the variable frequency oscillator 2. FIG. 31 is a diagram showing the control signal adjusting unit 13 of FIG. The control signal adjustment unit 13 shown in the figure
Is a comparator 21 including an operational amplifier having a non-inverting terminal to which the reference voltage Vref is input, an inverting terminal to which the D / A converter 8 is connected via a resistor, and an output side which is connected to the variable frequency oscillator 2.
A capacitor 22 located between the inverting input terminal and the output of the comparator 21, a resistor 23 connected in parallel with the capacitor 22, and a capacitor 24 connected in parallel.
And a switch 25 for disconnecting the connection of the capacitor 24 to the capacitor 22 by the pull-in state detecting unit 12.

FIG. 32 is a diagram for explaining the signal waveforms of each part of the control signal adjusting section 13 of FIG. As shown in this figure, the solid line is the output signal waveform of the D / A converter 8, that is, the input signal waveform of the control signal adjustment unit 13, and the dotted line A is the control signal adjustment unit during rough adjustment, that is, when the switch 25 is OFF. 13 is an output signal waveform of No. 13. The dotted line B is the output signal waveform of the control signal adjusting unit 13 during fine adjustment, that is, when the switch 25 is ON. In this way, the control signal adjusting unit 13 increases the integration time constant by the capacitors 22 and 24 at the time of fine adjustment, and makes the change of the control signal gentler than that at the time of coarse adjustment.
By switching the frequency change per time, the adverse effect on the bit error rate due to the digital modulation wave can be reduced. Further, it can be realized with a simple configuration.

FIG. 33 is a diagram showing a combination of the control signal adjusting section 13 of FIGS. 28 and 31. By performing the combination shown in this figure, frequency control with high accuracy and high performance becomes possible.

[0071]

As described above, according to the present invention, since the second digital type frequency discriminator is provided for coarse adjustment, the frequency discrimination accuracy and speed can be improved. Since no special device is required as the second digital type frequency discriminator, it is possible to achieve miniaturization and low cost as compared with the conventional one. At the same time, the input signal to the variable frequency oscillator is switched according to the change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator according to the frequency pull-in state of the pull-in state detector. Since the frequency that is the output signal is changed, the higher the detection accuracy of the pull-in state, the higher the accuracy of control that becomes possible,
Furthermore, since a D / A converter with low resolution can be used,
High frequency accuracy can be achieved at low cost. The response time of the input signal to the variable frequency oscillator is switched according to the change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator according to the frequency pulling state of the pulling state detection unit. Therefore, the adverse effect on the bit error rate due to the digital modulation wave can be reduced. Further, it can be realized with a simple configuration. Depending on the frequency pull-in state of the pull-in state detector, the input signal to the variable frequency oscillator is switched according to the change in the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator , The response time of the input signal to the variable frequency oscillator is switched with respect to the change of the output signal of the first digital type frequency discriminator or the second digital type frequency discriminator. The higher the detection accuracy of, the more accurate control becomes possible, and the adverse effect on the bit error rate due to the digital modulation wave can be reduced.
When a certain time has passed since the sync symbol was detected,
When the sync symbol is detected a certain number of times, and when the sync symbol is detected and the absolute value of the vector rotation between two or more sync symbols is less than a certain value, the control signal of the variable frequency oscillator is the second digital frequency discrimination. By switching from the device to the output of the first digital frequency discriminator, it is possible to prevent the deterioration of synchronization detection and prevent erroneous pull-in.

[Brief description of drawings]

FIG. 1 is a diagram showing an automatic frequency control circuit according to an embodiment of the present invention.

FIG. 2 shows M as an example of a modulation signal using four subcarriers.
It is a figure which shows the spectrum arrangement of 16QAM.

FIG. 3 is a diagram showing an arrangement of symbol signals of subcarriers.

4 is a digital frequency discriminator (fine adjustment) 10 of FIG.
FIG.

5 is a diagram showing a subcarrier separation unit 101 of FIG.

6 is a diagram showing a symbol reverse rotation unit 103 of FIG. 4;

FIG. 7 is a diagram for explaining the operation of the symbol reverse rotation unit 103 in FIG.

FIG. 8 is a diagram illustrating an output of an addition unit 104 in FIG.

9 is a diagram showing the frequency discriminating unit 105 of the direct cross product system of FIG.

10 is a digital frequency discriminator (fine adjustment) 1 of FIG.
It is a figure which shows the pull-in characteristic of 0.

FIG. 11 is a digital type frequency discriminator (fine adjustment) 1 of FIG.
It is a figure which shows another example of 0.

12 is a digital frequency discriminator (coarse adjustment) 1 of FIG.
It is a figure which shows 1.

FIG. 13 is a diagram showing the frequency relationship of FIG. 12;

FIG. 14 is a diagram showing another modification of FIG. 12;

15 is a diagram showing the frequency relationship of FIG.

16 is a graph showing the pull-in characteristic in the case of the conventional analog type frequency discriminator 4 of FIG.

FIG. 17 is a graph showing a pull-in characteristic when automatic frequency control is calculated using a subcarrier separation signal according to an embodiment of the present invention.

FIG. 18 is a diagram showing a frequency relationship between an input signal and a baseband signal.

FIG. 19 is a diagram showing a pull-in characteristic when switching is performed in combination with a subcarrier 1 separated signal and a subcarrier 4 separated signal.

FIG. 20 shows a subcarrier 1 separated signal, a subcarrier 2 separated signal,
It is a graph which shows the pull-in characteristic at the time of switching by combining the subcarrier 3 separated signal and the subcarrier 4 separated signal.

21 is a diagram illustrating the pull-in state detection unit 12 in FIG.

FIG. 22 is a graph showing synchronization detection characteristics.

FIG. 23 is a diagram showing a modification of FIG. 21.

FIG. 24 is a diagram showing another modification of FIG. 21.

FIG. 25 is a graph showing a synchronization detection rate when α = 0.45 is fixed and the reference rotation angle r is used as a parameter.

FIG. 26 is a graph illustrating an example of a pull-in effect according to the present embodiment.

FIG. 27 is a diagram showing an automatic frequency control circuit according to another embodiment of the present invention.

28 is a diagram showing the control signal adjusting unit 13 of FIG. 27. FIG.

FIG. 29 is a diagram showing outputs of the D / A converters 14 and 15 of FIG. 28 versus frequency change amount.

FIG. 30 is a diagram showing an automatic frequency control circuit according to another embodiment of the present invention.

31 is a diagram showing the control signal adjustment unit 13 of FIG. 30. FIG.

32 is a diagram for explaining signal waveforms of respective parts of the control signal adjusting unit 13 of FIG. 31.

FIG. 33 is a diagram showing an example of a combination of the control signal adjusting section 13 of FIGS. 28 and 31.

FIG. 34 is a diagram showing an example of a conventional automatic frequency control circuit that also serves as an analog type frequency discriminator and a digital type frequency discriminator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Quadrature converter 2 ... Variable frequency oscillator 9, 103, 203 ... Switch 10 ... 1st digital type discriminator (fine adjustment) 11 ... 2nd digital type discriminator (coarse adjustment) 12 ... Entrainment state detection part 13 ... Control signal adjusting unit 101 ... Sub-carrier separating unit 102, 202 ... Frequency discriminating unit 201 ... Spectrum separating unit

Claims (11)

[Claims] 1. An automatic frequency control circuit for a quasi-synchronous demodulator, comprising an orthogonal transformer (1) for orthogonally transforming a frequency component of an input signal, which is a composite signal of a plurality of subcarriers, into a base band having a center of 0 Hz. A variable frequency oscillator (2) for controlling a frequency with a control signal and supplying an oscillation output to the orthogonal transformer (1), and a digital signal of a frequency deviation generated at the time of conversion of the orthogonal transformer (1) are inputted, A first digital frequency discriminator (10) for fine adjustment, which has a relatively high frequency analysis accuracy and a relatively slow frequency analysis speed, which performs frequency discrimination to smooth the result, and the orthogonal transformer. The digital signal of the frequency deviation generated at the time of conversion of (1) is input and frequency discrimination is performed to smooth the result. However, the accuracy of frequency analysis is relatively low and the frequency analysis speed is relatively fast. Second digital-type frequency discriminator (11), said first digital-type frequency discriminator (10) and the second
Switch (9) for switching the digital type frequency discriminator (11), converting the output signal to an analog signal, and using it as a control signal for the variable frequency oscillator (2)
And a digital signal in which the output of the quadrature converter (1) has been converted, the known state is detected by detecting a known symbol, and a decision is made to switch the switch (9) according to the detected state. The first digital frequency discriminator (1) according to the frequency pull-in state of the state detector (12) and the pull-in state detector (12).
0) or a change of the output signal of the second digital type frequency discriminator (11), the control signal adjusting unit () for changing the frequency of the output signal by switching the input signal to the variable frequency oscillator (2). 13) An automatic frequency control circuit comprising: 2. The control signal adjusting section (13), according to the frequency pull-in state of the pull-in state detecting section (12), the first digital type frequency discriminator (10) or the second digital type frequency discriminator. The response time of the input signal to the variable frequency oscillator (2) is switched with respect to the change of the output signal of the discriminator (11).
The automatic frequency control circuit described in. 3. The control signal adjusting unit (13), according to the frequency pull-in state of the pull-in state detecting unit (12), the first digital type frequency discriminator (10) or the second digital type frequency discriminator. In response to a change in the output signal of the discriminator (11), the frequency of the output signal is changed by switching the input signal to the variable frequency oscillator (2), and at the same time, the first digital frequency discriminator (10). Alternatively, the response time of the input signal to the variable frequency oscillator (2) is switched with respect to the change of the output signal of the second digital type frequency discriminator (11). Frequency control circuit. 4. Automatic according to claim 1, characterized in that the first digital frequency discriminator (10) discriminates the frequency deviations using only known symbols of constant amplitude. Frequency control circuit. 5. The first digital frequency discriminator (10) performs frequency discrimination of frequency deviation based on signal point arrangement of known symbols in each subcarrier and arrangement in slots. The automatic frequency control circuit according to claim 4. 6. The second digital frequency discriminator (11) extracts a band substantially equal to the bandwidth of information transmitted by each carrier with 0 Hz near the center of each sub-carrier converted into a base band. A plurality of sub-carrier separation units (201), and outputs of each of the plurality of sub-carrier separation units (201) at 0 Hz.
Frequency discriminating unit (203) for discriminating frequency around
The automatic frequency control circuit according to claim 1, further comprising: a switch (204) for selectively selecting an output of the frequency discriminating unit (203). 7. The second digital frequency discriminator (11) divides two bands narrower than the bandwidth of the input signal near the upper end and the lower end of the frequency component of the signal converted into the base band. , So that the center of each is 0 Hz 2
One spectrum separation unit (301) and output of each spectrum separation unit (301) are set to 0H.
Two frequency discriminators (3
02) and a switch (303) for selectively selecting the two outputs of the frequency discriminating unit (302).
The automatic frequency control circuit according to claim 1. 8. The control signal of the variable frequency oscillator (2) is transmitted from the second digital type frequency discriminator (11) to the first pull-in state detector (12) when a predetermined time has elapsed after the known symbol is detected. The automatic frequency control circuit according to claim 1, wherein the switch (9) is switched so as to output the digital type frequency discriminator (10). 9. The pull-in state detecting section (12) outputs a control signal of a variable frequency oscillator (2) from a second digital frequency discriminator (11) to a first digital type when a known symbol is detected a predetermined number of times. Frequency discriminator (10)
The automatic frequency control circuit according to claim 1, characterized in that the switch (9) is switched so as to obtain the output of. 10. The control unit for a variable frequency oscillator (2), wherein the pull-in state detector (12) detects a known symbol, and when the absolute value of vector rotation between two or more known symbols is less than a certain value. Automatic according to claim 1, characterized in that the switch (9) is switched such that the signal is the output of the first digital frequency discriminator (11) from the second digital frequency discriminator (11). Frequency control circuit. 11. The automatic frequency control circuit according to claim 1, wherein the quadrature converter (1) converts into an intermediate frequency and then into a base band.