KR0162437B1 - Frequency a.f.t device & method of digital satellite broadcasting receiver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital satellite broadcasting receiver. In the related art, the IF frequency is distorted due to the thermal noise of a satellite antenna and a low-noise block-down amplifier. This imbalance causes distortion of the demodulated I and Q signals, and to solve the problem, when the saw filter is used over a wide band, the distortion of the signal is reduced, but the penetration of neighboring interference and noise increases, and thus transmission is performed. There is a problem that the signal is degraded due to a large number of bits in which an error of a digital signal is generated.

Therefore, in the present invention, in view of such a problem, the saw filter is not necessarily used as a wide bandwidth, and if the IF signal is larger than a specific reference value, the RF local oscillation frequency of the BS tuner is controlled to be smaller, whereas the IF signal is smaller than the specific reference value. If it is small, the RF side oscillation frequency of the BS tutor is controlled to be large so as to be fixed at a desired value so that it is always a constant IF frequency.If the IF frequency is determined to be fast, the RF side oscillation frequency of the BS tutor is controlled to be slow. If the IF frequency is determined to be slow, the RF local oscillation frequency of the BS tuner is controlled to be fast and fixed at a desired speed so that the constant IF frequency is solved the conventional problem.

Description

Frequency automatic fine tuning device and method of digital satellite broadcasting receiver

1 is an internal block diagram of a typical digital satellite broadcasting receiver.

2 is a diagram showing characteristics of a SAW filter and a rising cosine filter at an accurate IF carrier frequency.

3 is a diagram showing characteristics of a saw filter and a rising cosine filter at an IF carrier frequency shifted by Δ.

4 is an internal block diagram showing a digital satellite broadcasting receiver to which the present invention is automatically adjusted.

FIG. 5 shows the operational flow of the FIG. 4 microcomputer.

6 is an internal block diagram showing another embodiment of the digital satellite broadcasting receiver to which the present invention is automatically adjusted.

FIG. 7 shows the operational flow of the FIG. 6 microcomputer.

* Explanation of symbols for main parts of the drawings

100: BS tuner 110: signal separation unit

120: analog / digital conversion unit 130: matching filter unit

140: voltage controlled oscillator 150: divider

160: phase error detection unit 170: loop filter

180: counter 190: reset unit

200: comparison unit 210: correction signal generator

220: microcomputer 300: subtraction part

400: voltage discriminating unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital satellite broadcasting receiver, and in particular, an automatic frequency tuning device for a digital satellite broadcasting receiver capable of fine tuning of frequency by converting PLL data when there is a change in RF frequency input to the receiver. It is about.

As shown in FIG. 1, a general digital satellite broadcasting receiver receives BS data of the microcomputer 220 and converts an RF signal into an intermediate frequency signal (IF), and the BS tuner ( The intermediate frequency signal IF output from 100 is mixed with the output of the consonant voltage controlled oscillator 140 separated into I and Q signals, Wow Input the signal separation unit 110 for outputting a signal, the analog / digital conversion unit 120 for converting the output of the signal separation unit 110 into a digital signal, and the output of the analog / digital conversion unit 120 A matching filter unit 130 for demodulating and outputting I and Q signals, a phase error detection unit 160 for detecting phase errors of the I and Q signals output from the matching filter unit 130, and the phase error detection unit A loop filter 170 which receives the output of the output 160 and the output of the correction signal generator 210 and adds the sum of the outputs of the correction signal generator 210 and the output of the loop filter 170 according to the output of the loop filter 170. Of the voltage controlled oscillator 140 and the divider 150 that receives the output of the voltage controlled oscillator 140 and divides N, and the output and reset unit 190 of the divider 150. A counter 180 for receiving a reset signal and counting frequencies for each reference section; The reset unit 190 generating a reset signal every quasi-section, the comparison unit 200 receiving the outputs of the counter 180 and the reset unit 190 and determining the magnitude of the counter value; The correction signal generator 210 receives the discrimination signal of the comparator 200 and generates a correction signal according to the input signal, and the microcomputer 220 collectively controls the system.

The RF signal passing through the low noise block down amplifier (LNB) of the satellite antenna is input to the BS tuner 100 and the channel to be received by the PEL data output from the microcomputer 220 is tuned to the intermediate frequency signal (IF). ) Is converted into the signal separation unit 110 is input.

The signal separation unit 110 receives the intermediate frequency signal IF, divides it into I and Q signals, mixes the 90 ° phase shifted signal output from the voltage controlled oscillator 140, and Wow The signal is output, and these two signals are input to the analog / digital converter 120 and converted into digital data.

So converted Wow The digital data of the signal is applied to the matching filter unit 130 and filtered. The matching filter unit 130 provides a Root Raised Cosine Filter characteristic corresponding to a filter (not shown) on the transmitting side. By filtering, the final I and Q signals are demodulated and output.

In such a digital satellite receiver, frequency automatic adjustment is performed as follows.

The I and Q signals output from the matching filter unit 130 are input to the phase error detection unit 160 to detect phase errors of the two signals and are applied to the loop filter 170, and the loop filter 170 corrects the correction signal. The phase error is corrected by the correction signal of the generator 210 and then applied as a control signal of the voltage controlled oscillator 140.

On the other hand, the output signal of the voltage controlled oscillator 140 is divided by N by the division unit 150 and input to the clock input terminal of the counter 180 to be reset by the reset signal of the reset unit 190 Frequency counting is performed until the next reset time, and the reset unit 190 generates a reset signal for each reference section by the reference section signal RP output from the microcomputer 220.

Therefore, the comparator 200 receives the reset signal of the reset unit 190 as the determination start signal and outputs the frequency counting value output from the counter 180 and the upper range preset by the microcomputer 220. The value DU and the lower range value DL are compared to determine whether the frequency counting value at the end of every reference section is greater or less than the upper range value DU and the lower range value DL. The correction signal generator 210 outputs the correction signal.

When the frequency counting value is less than the lower range value DL, the correction signal generator 210 outputs the correction signal in the direction of raising the frequency to the loop filter 170, while the frequency counting value is the upper range. If greater than the value DU, the correction signal in the direction of lowering the frequency is output to the loop filter 170.

Then, the loop filter 170 receives the signal for the phase error output from the phase error detection unit 160 and the correction signal of the correction signal generator 210, sums it, and then changes the voltage to a constant DC voltage. By controlling the control oscillator 140, the I and Q signals having the phase error corrected by following the change in the IF frequency are demodulated.

On the other hand, Figure 2 and Figure 3 shows the filter characteristics of the transmitting and receiving side, the rising cosine filter on the transmitting side is a filter that optimally cuts out the digital data signal to be modulated and sent, the saw filter (SAW FILTER: Surface A) Wave) is a filter that filters the IF-converted signal in the BS tuner 100. FIG. 2 shows the filter characteristics when the carrier is an accurate IF frequency carrier, and shows an accurate IF frequency without a frequency error when the RF signal is converted into an IF signal. When converted into, demodulation is possible with I and Q signals without any problem, but as shown in FIG. 3, the IF frequency is shifted by Δ due to the thermal noise of the satellite antenna and LNB. Even if the signal is generated and follows the change of the IF frequency by the correction signal, the gain characteristics of the filter are unbalanced, resulting in distortion of the demodulated I and Q signals.

On the other hand, when the saw filter is used in a wide band, such distortion is reduced, but a problem of deterioration of the signal due to increased penetration of adjacent interference or noise, etc. occurs.

Accordingly, the present invention does not necessarily use the saw filter in a wideband in view of such a problem, and if the IF signal is larger than a specific reference value, the RF local oscillation frequency of the BS tuner is controlled to be smaller, whereas the IF signal is smaller than the specific reference value. If it is small, the purpose is to control the local oscillation frequency of the RF side of the BS tuner to be large and to fix it at a desired value so that the IF frequency is always constant.

In addition, if the IF frequency is determined to be fast, the RF local oscillation frequency of the BS tuner is controlled to be slow. On the other hand, if the IF frequency is determined to be slow, the RF local oscillation frequency of the BS tuner is controlled to be fast. Another purpose is to make the IF frequency, and the operation and effect of the present invention having such a purpose will be described in detail.

As shown in FIG. 4, the frequency automatic fine tuning apparatus of the digital satellite broadcasting receiver of the present invention receives BS data of the microcomputer 220 and converts an RF signal into an intermediate frequency signal IF. ), The intermediate frequency signal IF output from the BS tuner 100 is separated into I and Q signals, and then mixed with the output of the voltage controlled oscillator 140. Wow Input the signal separation unit 110 for outputting a signal, the analog / digital conversion unit 120 for converting the output of the signal separation unit 110 into a digital signal, and the output of the analog / digital conversion unit 120 A matching filter unit 130 for demodulating and outputting I and Q signals, a phase error detection unit 160 for detecting phase errors of the I and Q signals output from the matching filter unit 130, and the phase error detection unit A loop filter 170 that receives the output of the output 160 and the output of the correction signal generator 120 and adds the sum of the outputs of the correction signal generator 120 and the output of the loop filter 170 according to the output of the loop filter 170. Of the voltage controlled oscillator 140 and the divider 150 that receives the output of the voltage controlled oscillator 140 and divides N, and the output and reset unit 190 of the divider 150. A counter 180 for receiving a reset signal and counting frequencies for each reference section; The reset unit 190 generating a reset signal every quasi-section, the comparison unit 200 receiving the outputs of the counter 180 and the reset unit 190 and determining the magnitude of the counter value; In the digital satellite broadcasting receiver comprising the correction signal generator 210 for receiving the discrimination signal of the comparator 200 and generating a correction signal according thereto, and the microcomputer 220 for overall control of the system, Whether the frequency counting value of the counter 180 is large or small based on the center frequency data (DIF) value received from the output of the counter 180 and the output of the reset unit 190 and output from the microcomputer 220. It further comprises a subtractor 300 for discriminating and outputting the discrimination value thereof to the microcomputer 220.

On the other hand, the automatic frequency tuning method of the digital satellite broadcasting receiver of the present invention reads the determination value of the subtractor, and if it is determined that the value is 0, the first process of fixing and outputting the PL data to the current value; A second step of determining whether the value is positive if it is determined not to be zero by the process; and if it is determined that the value of the subtracting part is positive by the second step, decrease the PEL data by one step and then A third process of inputting again, a fourth process of fixing the PL data to a current value if it is determined to be 0 or a negative result and returning to the third process if it is positive; If it is determined that the determination value is negative, the fifth step of increasing the PEL data by one step and inputting the determination value of the subtractor again, and the determination result of the fifth step 0 Alternatively, if it is determined that the number is positive, the PEL data is fixed to the current value, and if the number is negative, the sixth process returns to the fifth process.

Thus, the present invention will be described in detail with reference to FIG. 4 and FIG. Since the basic structure and operation is the same as in the prior art will be described in detail with respect to the added portion in the present invention.

The frequency counting value for the reference section output from the counter 180 and the reset signal for each reference section output from the reset unit 190 are input to the subtraction unit 300 and set by the microcomputer 220. Frequency data (DIF) is received.

Accordingly, when the reset signal is activated, the subtraction unit 300 receives a frequency counting value and performs a subtraction function. The subtraction is performed by subtracting the center frequency data DIF value from the frequency counting value.

Thus, by comparing the frequency counting value and the center frequency data DIF for each reference section, it is determined whether the frequency counting value is larger or smaller than the center frequency data DIF and inputs the discrimination value to the microcomputer 220 again. Done.

Thus, the microcomputer 220 controls the PEL data input to the BS tuner 100 based on the discrimination value to prevent signal distortion of the demodulated I and Q. It demonstrates in detail with reference to FIG.

FIG. 5 is a diagram illustrating the operation of the microcomputer. When the determination value of the subtractor 300 is read, and the value is 0, it is determined that there is no transition of the IF frequency and the PEL data is fixed at the current value.

On the other hand, if the discrimination value is not 0, it is determined whether it is positive or negative. If it is positive, since the IF frequency is larger than the center frequency data (DIF), the PEL data is reduced by one step so that the local oscillation frequency of the BS tuner 100 becomes smaller. After that, the determination value is read again from the subtraction unit 300, and if the value is 0 or negative, the PEL data is fixed at the current value. If the determination value is positive, the PEL data is decreased by one step. Return to the routine.

In addition, if the determination value of the first subtractor 300 is negative, the frequency of the IF is smaller than the center frequency data DIF, and the PEL data is increased by one step in the direction of increasing the local oscillation frequency of the BS tuner 100. After that, the determination value is read again, and if the value is 0 or positive, the PL data is fixed at the value. If the determination value is negative again, the routine returns to the routine of incrementing the PI data by one step.

This automatically adjusts to always have a constant IF frequency for the RF frequency transition.

FIG. 6 is a diagram illustrating another embodiment of the present invention. The BS tuner 100 converts an RF signal into an intermediate frequency signal IF by receiving PEL data of the microcomputer 220 and the BS tuner 100. After separating the intermediate frequency signal (IF) output from the I and Q signal and then mixing with the output of the voltage controlled oscillator 140 accordingly Wow Input the signal separation unit 110 for outputting a signal, the analog / digital conversion unit 120 for converting the output of the signal separation unit 110 into a digital signal, and the output of the analog / digital conversion unit 120 A matching filter unit 130 for demodulating and outputting I and Q signals, a phase error detection unit 160 for detecting phase errors of the I and Q signals output from the matching filter unit 130, and the phase error detection unit A loop filter 170 which receives the output of the output 160 and the output of the correction signal generator 210 and adds the sum of the outputs of the correction signal generator 210 and the output of the loop filter 170 according to the output of the loop filter 170. Of the voltage controlled oscillator 140 and the divider 150 that receives the output of the voltage controlled oscillator 140 and divides N, and the output and reset unit 190 of the divider 150. A counter 180 for receiving a reset signal and counting frequencies for each reference section; The reset unit 190 generating a reset signal every quasi-section, the comparison unit 200 receiving the outputs of the counter 180 and the reset unit 190 and determining the magnitude of the counter value; In the digital satellite broadcasting receiver comprising the correction signal generator 210 for receiving the discrimination signal of the comparator 200 and generating a correction signal according thereto, and the microcomputer 220 for overall control of the system, The voltage discriminating unit 400 which receives the DC voltage of the loop filter 170 and compares it with the reference voltage Vref determines whether the DC voltage is large or small and outputs the determination value to the microcomputer 220. It will be configured to include more, it will be described in detail with reference to FIG.

The voltage discriminator 400 receives a DC voltage output from the loop filter 170 and compares it with a reference voltage Vref corresponding to an IF frequency. When the DC voltage is greater than the reference voltage Vref, a high potential signal is obtained. Is output to the microcomputer 220, on the other hand, if less than the reference voltage (Vref) outputs a low potential signal to the microcomputer 220 to control the PEL data applied to the BS tuner 100.

The operation of the microcomputer 220 will be described in detail with reference to FIG.

The microcomputer 220 receives the discrimination value output from the voltage determining unit 400 and determines whether the signal is a low potential signal or a high signal. If the signal is a high potential signal, the IF frequency is fast, so that the BS tuner ( Reduce the PL data by one step to slow down the local oscillation frequency of 100).

After receiving the determination value of the voltage determination unit 400 again, if it is determined that the signal is a low potential, the current PEL data value is fixed, and if the high potential signal is continuously input, it means that the IF frequency is still fast, so again PEL Return to the routine that decrements the data one step.

On the other hand, if the first discrimination value is a low potential signal, the IF frequency is slow, so the PLL data is increased by one step so that the local oscillation frequency of the BS tuner 100 is increased.

After receiving the determination value of the voltage determination unit 400 again, if it is determined that it is a high potential signal, the current PEL data value is fixed. If the low potential signal is continuously input, it means that the IF frequency is still low. Return to the routine that increments the data by one step.

Therefore, this also automatically adjusts so that the IF frequency is always constant with respect to the transition of the RF frequency.

As described above, the present invention has an effect of demodulating stable I and Q signals by maintaining a constant IF frequency even when the frequency shifted RF frequency is input without using the saw filter as a wide bandwidth.

Claims (4)

BS tuner for receiving RF data of microcomputer and converting RF signal into intermediate frequency signal, and separating intermediate frequency signal outputted from BS tuner into I and Q signals and mixing with output of voltage controlled oscillator. Wow A signal separation unit for outputting a signal, an analog / digital conversion unit for converting the output of the signal separation unit into a digital signal, a matching filter unit for receiving the output of the analog / digital conversion unit and demodulating and outputting I and Q signals; A phase error detection unit for detecting a phase error of the I and Q signals output from the matching filter unit, a loop filter which receives the output of the phase error detection unit and the output of the correction signal generator, adds them, and converts them into a constant DC voltage; The voltage controlled oscillator for receiving the output of the loop filter and outputting the voltage controlled oscillation according to the output of the loop filter; A counter for receiving a signal and frequency counting for each reference section, the reset unit for generating a reset signal for each reference section, and the car And a comparator for receiving the output of the control unit and the reset unit and determining the magnitude of the counter value, the compensating signal generator for receiving the discrimination signal of the comparator and generating a correction signal according to the comparator; In the digital satellite broadcasting receiver composed of a microcomputer, it is determined whether the frequency counting value of the counter is large or small based on the center frequency data value outputted from the microcomputer by receiving the output of the counter and the reset unit. And a subtractor for outputting the value to the microcomputer. A first step of reading the subtractor's determination value and determining that the value is 0, and fixing and outputting the PL data to the current value; and determining whether the value is positive if it is determined not to be zero by the first step. A second step of reducing the PL data by one step if the determination value of the subtraction part is positive by the second step and the second step, and receiving the determination value of the subtraction part again; If it is determined that the number is negative, the PEL data is fixed to the current value, and if the number is positive, the fourth step of returning to the third process and if the determination result determined by the second process is negative, increases the PEL data by one step. After the fifth step of inputting the subtraction part again and the determination result of the fifth step is 0 or positive, the PEL data is fixed to the current value. And a sixth step of returning to the fifth step if the number is zero. BS tuner that receives RF data of microcomputer and converts RF signal into intermediate frequency signal, and divides intermediate frequency signal outputted from BS tuner into I and Q signal, and then mixes with output of voltage controlled oscillator. Wow A signal separation unit for outputting a signal, an analog / digital conversion unit for converting the output of the signal separation unit into a digital signal, a matching filter unit for receiving the output of the analog / digital conversion unit and demodulating and outputting I and Q signals; A phase error detection unit for detecting a phase error of the I and Q signals output from the matching filter unit, a loop filter which receives the output of the phase error detection unit and the output of the correction signal generator, adds them, and converts them into a constant DC voltage; The voltage controlled oscillator for receiving the output of the loop filter and outputting the voltage controlled oscillation according to the output of the loop filter, a divider for dividing N by receiving the output of the voltage controlled oscillator, and resetting the output and reset of the divider. A counter for receiving a signal and frequency counting for each reference section, the reset unit for generating a reset signal for each reference section, and the car And a comparator for receiving the output of the control unit and the reset unit and determining the magnitude of the counter value, the compensating signal generator for receiving the discrimination signal of the comparator and generating a correction signal according to the comparator; A digital satellite broadcasting receiver comprising a microcomputer, the apparatus further comprising: a voltage discriminating unit configured to determine whether the DC voltage is large or small by receiving the DC voltage of the loop filter and comparing it with a reference voltage, and output a determination value thereof to the microcomputer. Frequency automatic fine tuning device of a digital satellite broadcasting receiver, characterized in that configured by. A first step of determining whether the signal is a low potential signal or a high potential signal by receiving the determination value of the voltage discriminator; and a second step of reducing the PEL data by one step if it is determined that the high potential signal is obtained by the first step; After performing the second process, the input value of the voltage discriminator is input again to determine whether it is a high potential signal or a low potential signal. If the signal is low potential, the PEL data is fixed to the current value. A third process of returning to the second process, a fourth process of increasing PEL data by one step if it is determined that the signal is low potential by the first process, and a determination value of the voltage discriminator after performing the fourth process. After re-input, it is determined whether the signal is high or low potential, and if the signal is high potential, the PEL data is fixed to the current value. A fourth process of the fifth process of how automatic frequency fine adjustment of the digital satellite broadcasting receiver, comprising a step of returning to the operation.