JPH08154083A - Code division multiple connection receiver - Google Patents

Abstract

PURPOSE: To embody a code division multiple connection receiver with high performance based on a CDMA communication system. CONSTITUTION: A multiplier 31 multiplies a reception signal IN and a PN code S 35 for every chip. A correlation device 32 accumulates the multiplication result of the multiplier 31 and calculates a correlation value S 32. A power comparator 33 compares the correlation value S 32 and a threshold. After a search controller 34 records the correlation value S 32 and the phase difference information corresponding to the correlation value S 32 in all the phase space of the PN code 35, the controller 34 selects the phase difference information S 34b corresponding to the synchronized location of the PN code of the reception signal IN and the PN code 35 from the recorded phase difference information. A multiplier 41 multiplies the reception signal IN and a second PN code S 44 for every chip. The correlation device 42 accumulates the multiplication result of the multiplier 41 and calculates a correlation value S 42. A demodulator 43 performs a phase correction for the correlation value S 42 and demodulates the reception signal IN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to code division multiple access (Co
The present invention relates to a code division multiple access receiving apparatus on the receiving side in a mobile communication system based on a de division multiple access (hereinafter referred to as CDMA) communication system.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Kazuo Terada, "Digital Mobile Communication Technology", First Edition, 1988, February 25, 1988, published by Japan Industrial Technology Center, p.125 In the CDMA communication described in the above reference, the same pseudo on the transmitting side and the receiving side is used. Since data is spread and despread using a random signal (Peseudo Noise, hereinafter referred to as PN code), synchronization between the PN code included in the received signal and the PN code generated by the receiving station is important. That is,
Only when the PN code included in the received signal and the PN code generated in the receiving station match, the demodulation is accurately performed. Therefore, on the receiving side of the CDMA communication, it is necessary to grasp the accurate synchronization position of the PN code at the initial stage of the communication, and the synchronization acquisition circuit does this. The PN code is a sequence of numbers having a value of +1 or -1, and a time width having the value of +1 or -1 is called a chip.

In the synchronization acquisition circuit, the received signal is multiplied by the PN code for each chip and added to obtain the correlation value. In an ideal state, a high correlation value is obtained only when the PN code of the received signal and the PN code generated by the receiving station match, and the correlation value becomes close to 0 when even one chip deviates. In an actual synchronization acquisition circuit, the PN code of the received signal and the PN code generated by the receiving station are correlated while shifting the phase, and the position where the correlation value exceeds the threshold is taken as the synchronization position, and the phase corresponding to the synchronization position is taken. Demodulate with. As a method of shifting the phase, there are a method of waiting with a constant PN code, such as a matched filter, and a method of shifting the phase of the PN code generated by the receiving station, such as sliding correlation. When there is a possibility that the synchronization position slightly fluctuates, a phase tracking circuit such as a delay lock loop (hereinafter referred to as DLL) is used.

FIG. 2 is a block diagram showing a configuration example of a conventional code division multiple access receiver. This code division multiple access receiver is composed of a synchronization acquisition circuit 10 and a demodulation circuit 20. The synchronization acquisition circuit 10 includes a multiplier 11, a correlator 12, a power comparator 13, a search controller 14, and a PN code generator 15. The multiplier 11 inputs the received signal IN and the PN code S15 from the first input terminal and the second input terminal, respectively, and inputs the PN code S15.
It has a function of performing multiplication for each chip. Multiplier 11
The output side of is connected to the input side of the correlator 12. The correlator 12 accumulates the multiplication results from the multiplier 11 and indicates a correlation value S1 indicating the degree of correlation between the received signal IN and the PN code S15.
It has the function of calculating 2. The output side of the correlator 12 is connected to the input side of the power comparator 13. The power comparator 13 compares the correlation value S12 with a threshold value,
It has a function of outputting the correlation value S12 when the correlation value S12 is equal to or more than the threshold value. The output side of the power comparator 13 is
It is connected to the input side of the search controller 14.

The search controller 14 determines that the synchronization is obtained when the correlation value S12 is input from the power comparator 13, outputs the control signal S14, and outputs the PN code S15 generated by the PN code generator 15. It has the function of fixing the phase. The output side of the search controller 14 is connected to the input side of the PN code generator 15. The PN code generator 15 has a function of outputting the PN code S15 and outputting the PN code S15 whose phase is fixed when the control signal S14 is input. The output side of the PN code generator 15 is connected to the second input terminal of the multiplier 11. The demodulation circuit 20 includes a multiplier 21, a correlator 22, and a demodulator 2.
Equipped with 3. The multiplier 21 has a function of inputting the received signal IN and the PN code S15 from the first input terminal and the second input terminal, respectively, and performing multiplication. The output side of the multiplier 21 is connected to the input side of the correlator 22.
The correlator 22 accumulates the multiplication results of the multiplier 21 and indicates a correlation value S2 indicating the degree of correlation between the received signal IN and the PN code S15.
It has the function of outputting 2. The output side of the correlator 22 is connected to the input side of the demodulator 23. Demodulator 23
Has a function of phase-correcting the correlation value S22 and demodulating the received signal IN. The synchronization acquisition circuit 10 and the demodulation circuit 20 are digital signal processors (hereinafter referred to as DSP) which are program-controlled.
It is also possible to configure.

Next, the operation of FIG. 2 will be described. In the synchronization acquisition circuit 10, the received signal IN is multiplied by the PN code S15 for each chip by the multiplier 11, and the multiplication result is accumulated by the correlator 12 to obtain the correlation value S12. The power comparator 13 compares the correlation value S12 with a threshold value. The search controller 14 controls the synchronization acquisition circuit 10 based on the comparison result from the power comparator 13. That is, the correlation value S12
Is smaller than the threshold value, the matched filter continues the correlation as it is, and if it is the sliding correlation, the correlation is continued while shifting the phase of the PN code S15 of the PN code generator 15. When the correlation value S12 becomes equal to or more than the threshold value, it is determined that the synchronization is obtained, and the search controller 14 fixes the phase of the PN code S15 generated by the PN code generator 15 and ends the synchronization acquisition operation. The demodulation circuit 20 starts demodulation at the same time as the end of the synchronization acquisition operation. That is, the PN code S15 whose phase is fixed at the synchronization position and the reception signal IN are multiplied by the multiplier 21, the correlation is obtained by the correlator 22, and the demodulator 23 demodulates.

[0007]

However, the conventional code division multiple access receiver of FIG. 2 has the following problems. That is, in mobile communication, generally, a radio signal transmitted from a transmitting side is reflected by a building or the like to become a multipath and reaches a receiving side. Therefore, on the receiving side, there are a plurality of synchronization positions, but in the conventional synchronization acquisition method, synchronization is achieved at the moment when the correlation value S12 becomes equal to or greater than the threshold value, and the acquisition operation ends. However, even if there is a synchronization position after which a higher correlation value can be obtained, detection becomes impossible. However, the higher the correlation value, the SN of the signal
Since the ratio is good and the reliability of the data is high, it is necessary to detect the synchronization position where a higher correlation value can be obtained, in order to realize a higher performance receiver. Also, the propagation phase and delay time of the multipath signal are corrected and added by the demodulator,
When a method called RAKE that obtains larger power is applied, the conventional synchronization acquisition method requires a synchronization acquisition circuit for each multipath, resulting in a large circuit scale. For example, when adding three multipaths, three synchronization acquisition circuits are prepared and different synchronization positions are searched for.

[0008]

In order to solve the above problems, the first invention is based on a code division multiple access communication system in which signals modulated by spread spectrum are multiplexed in the same frequency band for communication. The code division multiple access receiving apparatus provided on the receiving side of the mobile communication system is provided with the following means. That is, a first multiplication means configured to multiply a first PN code and a reception signal in the baseband band, which are configured with a fixed chip row pattern and are repeated for each code length, for each chip; Counting means for counting the pulse for each chip and clearing with the code length of the first PN code, and sequentially generating the first PN code while shifting the phase based on the phase difference information and the count value of the counting means. A first PN code generation means, and a first accumulation for accumulating multiplication results of the first multiplication means to calculate a first correlation value indicating a degree of correlation between the received signal and the first PN code. Means for comparing the first correlation value with a threshold value and outputting the correlation value when the first correlation value is greater than or equal to the threshold value, the count value of the counting means and the first value PN code The difference between the chip number and the PN code included in the received signal and the PN code generated by the receiving side is used as the phase difference information, and the next phase difference information of the phase difference information corresponding to the correlation value output from the comparison means. Is transmitted to the first PN code generating means, and the correlation value which is equal to or more than the threshold value in the entire phase space of the first PN code and the phase difference information corresponding to the correlation value are recorded, Selection means for selecting the phase difference information corresponding to the synchronization position between the PN code of the received signal and the PN code generated by the receiving side from the phase difference information.

Further, in this code division multiple access receiver, a second PN code is generated at a phase based on the phase difference information corresponding to the synchronization position selected by the selecting means and the count value of the counting means. Second PN code generating means, second multiplying means for multiplying the received signal by the second PN code on a chip-by-chip basis, and accumulating multiplication results of the second multiplying means to accumulate the received signal and the received signal. Second PN
Second accumulating means for calculating a second correlation value representing the degree of correlation with the code, and a demodulator for phase-correcting the second correlation value for demodulation are provided.

[0010]

According to the present invention, since the code division multiple access receiver is constructed as described above, the received signal is multiplied by the first PN code by each chip by the first multiplication means. The multiplication result of the first multiplying means is accumulated by the first accumulating means, and the first expressing the degree of correlation between the received signal and the first PN code.
It becomes the correlation value of. The first correlation value is compared with the threshold value by the comparison means, and when the first correlation value is equal to or larger than the threshold value, the correlation value is output from the comparison means. On the other hand, the pulse of the received signal is counted for each chip by the counting means and cleared by the code length of the first PN code. The first PN
The code is generated by the first PN code generating means while shifting the phase based on the phase difference information and the count value of the counting means. The phase difference information next to the phase difference information corresponding to the correlation value output from the comparing means is sent to the first PN code generating means by the selecting means, and the first P
After the correlation value equal to or more than a threshold value and the phase difference information corresponding to the correlation value are recorded in the entire phase space of the N code, the PN code of the received signal and the PN code generated by the receiving side are recorded from the recorded phase difference information. The phase difference information corresponding to the synchronization position of is selected.

Next, the second PN code is generated by the second PN code generating means while shifting the phase based on the phase difference information corresponding to the synchronization position selected by the selecting means and the count value of the counting means. It The received signal is the second
Is multiplied by the second PN code chip by chip by the multiplying means, and the multiplication result of the second multiplying means is accumulated by the second accumulating means to represent the degree of correlation between the received signal and the second PN code. It is calculated as a correlation value of 2. The second correlation value is phase-corrected and demodulated by the demodulator. Therefore, the selecting means can select an accurate synchronization position between the PN code included in the received signal and the PN code generated by the receiving side. Further, since the selecting means selects a plurality of synchronization positions, it can be easily applied to the RAKE system. Therefore, the above problem can be solved.

[0012]

1 is a block diagram showing an example of the configuration of a code division multiple access receiving apparatus showing an embodiment of the present invention. This code division multiple access receiver is composed of a synchronization acquisition circuit 30 and a demodulation circuit 40. The synchronization acquisition circuit 30 includes a multiplier 31 which is a first multiplication means, a correlator 32 which is a first accumulation means, a power comparator 33 which is a comparison means, a search controller 34 which is a selection means, and a first pseudo. It is provided with a PN code generator 35 which is a code generating means and a signal counter 36 which is a counting means. The multiplier 31 inputs the received signal IN and the first PN code S35, which is, for example, a sequence of 128 consecutive numbers having a value of +1 or -1, from the first input terminal and the second input terminal, respectively. It has a function of multiplying each chip of the PN code S35.
The output side of the multiplier 31 is connected to the input side of the correlator 32. The correlator 32 has a function of accumulating the multiplication results of the multiplier 31 to calculate the correlation value S32. Correlator 32
The output side of is connected to the input side of the power comparator 33. The power comparator 33 has a function of comparing the correlation value S32 with a threshold value. The output side of the power comparator 33 is connected to the input side of the search controller 34. Here, the PN code S35 is composed of, for example, 128 chips, and the chip numbers 1 to 1 are sequentially arranged from the beginning of the PN code S35.
128 is assigned.

In the search controller 34, the signal counter 36
Difference between the count value of the PN code and the chip number of the PN code S35, the PN code and the PN code S3 included in the reception signal IN.
5, the phase difference information S34a next to the phase difference information corresponding to the correlation value S32 is used as the PN code generator 35.
And the phase difference information corresponding to the correlation value S32 and the correlation value S32 are sent to the chip numbers 1 to 1 of the PN code S35.
After recording in the entire phase space corresponding to 28, the phase difference information S34b corresponding to the synchronization position between the PN code of the received signal IN and the PN code S35 is recorded from the recorded phase difference information.
Has the function of selecting. First search controller 34
The output terminal of is connected to the first input terminal of the PN code generator 35. The PN code generator 35 has a function of generating the PN code S35 while shifting the phase based on the phase difference information S34a and the count value of the counting means 36. The output side of the PN code generator 35 is connected to the second input terminal of the multiplier 31. The reception signal IN is input to the input side of the signal counter 36. The signal counter 36 has a function of counting the pulse of the reception signal IN for each chip and clearing it with the code length of the PN code S35. The output side of the signal counter 36 is connected to the second input terminal of the PN code generator 35.

The demodulation circuit 40 includes a multiplier 41 which is a second multiplication means, a correlator 42 which is a second accumulation means, and a demodulator 4.
3 and a PN code generator 44 which is a second pseudo code generating means. The multiplier 41 has a function of inputting the received signal IN and the second PN code S44 from the first input terminal and the second input terminal, respectively, and performing multiplication for each chip. The output side of the multiplier 41 is connected to the input side of the correlator 42. The correlator 42 has a function of accumulating the multiplication results of the multiplier 41 and calculating a second correlation value S42 indicating the degree of correlation between the received signal IN and the PN code S44. The output side of the correlator 42 is connected to the input side of the demodulator 43. The second output terminal of the search controller 34 is connected to the first input terminal of the PN code generator 44. At the second input terminal of the PN code generator 44,
The output side of the signal counter 36 is connected. The PN code generator 44 receives the phase difference information S from the search controller 34.
It has a function of generating a PN code S44 while shifting the phase based on the count value S36 from 34b and the signal counter 36. The output side of the PN code generator 44 is
It is connected to the second input terminal of the multiplier 41. The synchronization acquisition circuit 30 and the demodulation circuit 40 are configured by a DSP that is program-controlled.

Next, the operation of FIG. 1 will be described. First, the operation when the sliding correlation method is used will be described. In the synchronization acquisition circuit 30, the received signal IN is multiplied by the multiplier 31 with the PN code S35 for each chip, and the multiplication result is accumulated by the correlator 32 to obtain the correlation value S32. The signal counter 36 is counted up each time the received signal IN is input by one chip and is cleared by the PN code length. For example, assuming that the PN code length is n, the signal counter value CN is a repetition of CN1 to CNn. Here, the numbers of the chips in the chip sequence of the PN code included in the reception signal IN are sequentially assigned from the beginning to the PN code addresses RPN1 to RPN1.
RPNn. The PN code generator 35 sets P based on the phase information S34a sent from the search controller 34 and the received signal counter value S36 sent from the signal counter 36.
The N code S35 is generated.

The position of the PN code in the received signal IN cannot be specified during the synchronization acquisition, but since the signal counter value CN and the PN code address are cleared by the PN code length n, the positional relationship is always constant. Become. That is, assuming that the PN code address RPN1 starts at the signal counter value CNm (1 ≦ m ≦ n), when the count value CN is counted up and becomes the signal count value CNm again, the PN code address of the reception signal IN is similarly obtained. Again R
Become PN1. At this time, the phase difference PHR between the signal count value CNi and the PN code address RPNj is the count value C.
Based on Ni, PHR = CNi−RPNj = m−1, and this phase difference PHR remains unchanged during communication. For example, if m = 30, then PHR = m-1 = 29, and this phase difference PHR is held.

The search controller 34 sends the phase difference information PH whose correlation value is to be investigated to the PN code generator 35, and the PN code generator 35 PN based on the signal counter value CN.
Generate code S35. That is, assuming that the phase difference information PH of the phase to be correlated is PHi and the current counter value of the signal counter value is CNk, a PN code starting from a PN code address of APN = CNk-PHi is generated. PN code address APN and signal counter value C
Since N is updated for each chip and cleared with the PN code length n, the phase difference information PHi remains unchanged during the correlation. When the correlation is over, the search controller 34 updates the phase difference information PHi.

The search controller 34 sets the phase difference information PHi to P
If updating is performed in the range of H1 to PHn, the synchronization determination investigation will be performed in the entire phase space. Assuming that the PN code address RPN1 has started in the signal counter value CNm, when PHi = m−1, that is, when the phase difference information PHi has the same value as the phase difference PHR, synchronization is achieved. The correlation value S32 is
The power comparator 33 compares with the threshold value. If the correlation value S32 is greater than or equal to the threshold, the search controller 34 records both the phase difference information and the correlation value S32, and the PN code generator 3 outputs the phase difference information S34a for the next correlation.
Send to 5. If the correlation value S32 is less than or equal to the threshold value, the next correlation is directly performed. The search controller 34 selects a synchronization position after performing a synchronization check in the entire phase space of the PN code S35. When selecting one synchronization position, there are methods such as selecting the one with the maximum correlation value, or selecting three with a high correlation value and selecting the one with an intermediate phase difference among them. . It is also possible to select a plurality of synchronization positions. In addition, it is possible to shorten the synchronization acquisition time by performing the synchronization determination investigation with the target of only a specific phase space.

On the other hand, in the matched filter method, since the PN code generator 35 generates a constant PN code S35, phase information is calculated from the signal counter value CN in the PN code generator 35, and the search controller 34 is calculated. Inform. In the search controller 34, the phase information and the correlation value S
32 is recorded, and when the investigation in the entire phase space is completed, the selection of the synchronization position is started. Here, the PN code generator 35 uses the PN code addresses RPN1 to RPNp (1 ≦ p ≦ n).
PN code is always generated. The counter value of the signal to be multiplied with the PN code indicated by RPN1 is CNk.
Then, the phase difference information PHi is PHi = k-1. When k is set to 1 to n, the synchronization judgment investigation of the PN code S35 in the entire phase space is performed.

Simultaneously with the completion of the synchronization acquisition of the synchronization acquisition circuit 30, the demodulation circuit 40 starts the demodulation. Demodulation circuit 40
, The phase difference information S34b corresponding to the synchronization position between the PN code of the received signal IN and the PN code S35 is sent from the search controller 34 in the synchronization acquisition circuit 30. Demodulation circuit 4
The PN code generator 44 in 0 generates the PN code S44 according to the phase difference information S34b and the signal counter value S36. That is, assuming that the phase difference information at the synchronization position is PHmax, PN code S44 starting from the PN code address APN = CNk-PHmax
Occurs. The phase difference between the PN code address in the received signal IN and the signal counter value is unchanged, and the signal counter 3
The signal counter value S36 of 6 is the PN code generator 35, 4
4, the phase difference relationship is maintained, and the PN code S44 generated from the PN code generator 44 and the received signal IN are multiplied by the multiplier 41, and the correlation is obtained by the correlator 42 to obtain the demodulator. It is demodulated at 43. Therefore, demodulation is performed at the synchronization position obtained by the synchronization acquisition circuit 30.

Further, in the RAKE system, when demodulation is performed at a plurality of synchronization positions of the PN code of the received signal IN and the PN code S35, a plurality of demodulation circuits 40 are prepared, and the search controller 34 is used for each demodulation circuit. This is performed by giving phase difference information corresponding to a plurality of synchronization positions, respectively. Therefore, since the search position of one synchronization acquisition circuit collectively selects the synchronization position, the control becomes easy.
As described above, in this embodiment, the search controller 34 sets the P
P of the received signal IN in the entire phase space of the N code S35
Since the synchronization position is selected after the synchronization check of the N code and the PN code S35 is performed, the synchronization position corresponding to the maximum correlation value can be selected. Further, the search controller 34
Since it is possible to select a plurality of synchronization positions, it becomes easy to apply to the RAKE system.

[0022]

As described in detail above, according to the present invention, the selecting means selects the PN code included in the received signal and the PN code generated by the receiving side in the entire phase space of the first PN code. Since the synchronization position is selected after performing the synchronization investigation, it is possible to select the accurate synchronization position. Further, since the selecting means selects a plurality of synchronization positions, it can be easily applied to the RAKE system.

[Brief description of drawings]

FIG. 1 is a block diagram of a code division multiple access receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional code division multiple access receiver.

[Explanation of symbols]

31, 41 Multiplier (multiplication means) 32, 42 Correlator (accumulation means) 33 Power comparator (comparison means) 34 Search controller (selection means) 35, 44 PN code generator (pseudo code generation means) 36 Signal counter (Counting means) 43 Demodulator

Claims (1)

[Claims] 1. A code division multiple access receiving device provided on the receiving side of a mobile communication system based on a code division multiple access communication system, in which a signal modulated by spread spectrum is multiplexed in the same frequency band for communication, And a first multiplication means for multiplying the received signal in the baseband band by the first pseudo code, which is composed of the chip row pattern, and is repeated for each code length, and the pulse of the received signal is divided into chips. Counting means for counting each time and clearing with the code length of the first pseudo code; and a first means for sequentially generating the first pseudo code while shifting the phase based on the phase difference information and the count value of the counting means. A pseudo code generating means, and a first representing a degree of correlation between the received signal and the first pseudo code by accumulating multiplication results of the first multiplying means. First accumulating means for calculating a correlation value, comparing means for comparing the first correlation value with a threshold value, and outputting the correlation value when the first correlation value is equal to or more than the threshold value, and the counting The difference between the count value of the means and the chip number of the first pseudo code is used as phase difference information between the pseudo code included in the received signal and the pseudo code generated by the receiving side, and the correlation value output from the comparing means The phase difference information next to the phase difference information corresponding to is transmitted to the first pseudo code generating means and corresponds to the correlation value and the correlation value which are equal to or more than the threshold value in the entire phase space of the first pseudo code. Selecting the phase difference information corresponding to the synchronization position of the pseudo code in the received signal and the pseudo code generated by the receiving side from the recorded phase difference information, Hand of choice Second pseudo code generating means for generating a second pseudo code at a phase based on the phase difference information corresponding to the synchronization position selected by the stage and the count value of the counting means; the received signal and the second pseudo code. Second multiplication means for multiplying each code by a chip; and a second correlation value representing a degree of correlation between the received signal and the second pseudo code by accumulating multiplication results of the second multiplication means. A code division multiple access receiving device comprising: a second accumulating unit for calculating; and a demodulator for phase-correcting the second correlation value for demodulation.