JPH0815382A - Circuit incorporating self test function - Google Patents

Abstract

PURPOSE:To prevent a compressed data from having an indeterminate value by a constitution wherein a data in indeterminate state is masked at a logic gate and a data compressor takes in the data in indeterminate state. CONSTITUTION:When the internal circuit 1 is subjected to self test, output data from a plurality of scan paths 2 previously formed on the circuit 1 is fed through a logic gate 6 to a data compressor 4 and stored therein while being compressed. A scan in pin 5 provides a data to the path 2 and the gate 6 provided for each path 2 performs logical operation on the output data from the path 2 and an input data from the pin 5 corresponding to the path 2. When the indeterminate data on the path 2 is read into the compressor 4, input data from the pin 5 is set at a value for masking the indeterminate data and the gate 6 can mask the indeterminate data. This constitution can prevent the compressed data from becoming indeterminate in the compressor 4.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIGS. 17 and 18) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 to 3) Action (FIGS. 1 to 3) Example (FIGS. 4 to 16) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-test function built-in circuit such as an LSI or a printed circuit board in which a self-test function is built in advance.

[0003]

2. Description of the Related Art Generally, in order to detect a manufacturing defect of a circuit such as an LSI, a test pattern is applied to a circuit under test and its output is an expected value (normal operation output: result of logic / fault simulation). Generally, it is difficult to create a test pattern for an LSI due to its large scale in recent years, and the creation time of the test pattern has become a large proportion of the LSI design time. ing.

For example, FIG. 17 shows a general scan circuit (LSI) having a plurality of (three in the figure) scan paths. In FIG. 17, 100 is a scan circuit and 101 is a predetermined function. A circuit component arranged on the scan circuit 100 to form an internal circuit, such as a flip-flop (FF). Also, from 102A
102C is a scan path, and each scan path 102
A to 102C are formed in advance on the scan circuit 100 (three in the figure) and connect a plurality of flip-flops 101 in a chain.

The scan circuit 100 includes scan-in pins (SI pins) 103A to 103C for supplying test data (test pattern) to the scan paths 102A to 102C, and the scan paths. Scan out pins (SO pins) 104A to 104 for extracting output data from 102A to 102C
C and a scan clock pin (SCK pin) 105 for inputting a clock signal for operating the scan circuit 100 are provided as external input pins.

Both ends of each scan path 102A-102C are connected to SI pins 103A-103C and SO pins 104A-104C, respectively. The clock signal input from the SCK pin 105 is
All flip-flops 10 on the scan circuit 100
1 is input to the clock terminal. During scan operation, each scan path 102A-102C
The upper flip-flop 101 operates as a shift register, and by applying a clock signal from the SCK pin 105, the values given to the respective SI pins 103A to 103C are sequentially changed to the next values on the respective scan paths 102A to 102C. It is shifted in to the flip-flop 101. At the same time, each SO pin 104A-104C has
The value of the flip-flop 101 on each of the scan paths 102A to 102C is sequentially scanned out.

In this way, in addition to the test means for applying the test pattern from the outside of the circuit under test (LSI),
In recent years, a built-in self test called BIST (Built In Self Test) has been performed in each circuit. In this BIST type circuit, for example, a pattern generator [LFSR (Lenear Feedback Shift Registe
r), counter, ROM storage pattern, etc.], data analyzer [MISR (Multiple-Input Signature Register), comparator, ROM storage data, etc.], and a control circuit for controlling these.

In the test using BIST, the test pattern generated by the pattern generator is the circuit under test (LS).
I) is applied to the internal circuit, and the output result is verified by the data analyzer. MISR is often used as a data analyzer, and the output result is signed (Signatur
The data analyzer is called a data compressor because it is compressed and stored in MISR as e). In the present invention as well, since it is premised that MISR is used as a data analyzer, a data compressor will be used instead of the data analyzer.

FIG. 18 shows a general BIST type circuit (LSI) having a plurality of (three in the figure) scan paths. In FIG. 18, 110 is a BIST type circuit, and FIG. Similar to the one shown, on the circuit 110, a flip-flop (FF) 101 as a circuit constituent element forming an internal circuit that performs a predetermined function.
Or a plurality of (three) scans formed in advance to connect a plurality of flip-flops 101 in a chain.
The paths 102A to 102C are arranged.

Further, 111 is each scan path 102A
LF that generates the test pattern to be input to -10C
SR (Pattern Generator), 112 is each scan path 1
It is MISR (data compressor) which compresses and stores the output data from 02A-102C. Where LFSR1
11 and MISR 112 are both configured by a shift register with feedback via an exclusive OR gate (see FIGS. 5 to 7 described later).

Each shift register has an SCK pin 10
The clock signal from 5 causes the shift operation. Further, in FIG. 18, 103 is a scan-in pin (SI pin) connected to the LFSR 111, and 104 is a scan-out pin (SO pin) connected to the MISR 112. Further, like the scan circuit 100 shown in FIG. 17, the clock signal from the SCK pin 105 is input to the clock terminal of each flip-flop 101.

During the self-test operation, LFSR1
11 generates a pseudo random number, and each scan path 102A-
The flip-flop 101 on the scan path 102A to 102C operates as a shift register, and a clock signal is supplied from the SCK pin 105 to the scan path 102A to 102C. Given values are sequentially
It is shifted in to the next flip-flop 101.

At the same time, each scan path 102A ...
The values of the flip-flop 101 on the 102C are sequentially
It is shifted out, compressed and stored in the MISR 112. Lastly, the data compressed and stored in the MISR 112 is read from the scan-out pin SO to determine the defect of the circuit (LSI) 110.

The BIST type circuit 110 as described above
The self-test operation in (1) is performed by a self-test circuit (LFSR111, MISR112, etc.) incorporated inside by applying a clock signal to the circuit 110, and only minimum information (data accumulated in MISR112) is transferred to the outside. Just read it. This BIST type circuit has the following advantages.

When an LFSR or a counter is used as the pattern generator, it is not necessary to create a test pattern given from the outside, so that the number of LSI design steps can be reduced. Since the test pattern is applied from the built-in pattern generator and the result captured by the data compressor can be read out, expensive test equipment is not required.

A scan design as shown in FIG. 17 is a common sense for a large-scale LSI, but in recent years, since the advantages described above are obtained, the number of LSIs using a BIST circuit as shown in FIG. 18 is increasing. ing.

[0017]

However, the BIS
T has the drawback that the reliability of the test cannot be calculated easily. Usually, the reliability of LSI test is calculated as [diagnosis rate (%)] [number of detected failures] / [total number of failures] × 100. It is necessary to perform a failure simulation using the model of the LSI to be tested and the test pattern to judge the failure detection. On the other hand, a pseudo random number generator such as LFSR is used for the BIST pattern generator, and a considerably long pattern is required to obtain a sufficient diagnostic rate. Generally, failure simulation takes a very long time, and a great number of man-hours are required to evaluate a long pattern applied by BIST.

A MISR is generally used for the BIST data compressor. However, since the MISR is composed of a shift register with feedback via an exclusive OR gate (see FIG. 5 described later), the MISR is once used. However, if data in an undefined state is taken into a data compressor such as MISR, all the compressed data (shift register) in this MISR will be in undefined state, resulting in MIS.
Reading the data compressed in R would be meaningless.

Generally, since the internal storage element of an LSI is in an indeterminate state when the power is turned on, the state of the internal storage element is always reset or scanned before performing BIST to set a clear value that is not indeterminate. There must be. However, some internal storage elements cannot be initialized by a simple procedure, and special caution is required to apply BIST to such an LSI.

Further, in the data compressor, particularly the data compressor such as MISR, the contents are updated every time the clock signal is applied, and this updating is performed even while the initialization pattern of the internal storage element is being applied. Is performed, so MISR
Contents are destroyed and the test pattern generation program needs to monitor the contents of MISR, which complicates the processing.

Further, in general test data, a list of values to be applied to a plurality of external input pins is described for the number of patterns. Therefore, the test data for a large-scale LSI becomes very large (see, for example, FIGS. 9 and 13 described later). On the other hand, a test using BIST
The data only describes the number of times the clock signal is applied to operate the BIST (see, for example, FIG.
0, FIG. 14), and is very advantageous in terms of computer resources and load time of test data to the tester device.
However, as mentioned above, testing using only BIST
The data lacks versatility, and requires a long pattern to obtain a satisfactory diagnosis rate, and further requires an additional circuit and a test pattern for initializing the internal storage element.

Depending on the specific circuit on the circuit under test such as LSI, it may be desired to fix the value to be applied / set. In the current BIST, the pseudo random number generated by the pattern generator is applied. Therefore, it is impossible to arbitrarily apply and set the value in a specific circuit, and there is a problem that it is impossible to fix the value as described above.

The present invention has been devised in view of the above problems, and prevents the data compressor from capturing undefined data or destroying the contents of the data compressor during initialization. In addition to enabling reliable and easy self-test, combining scan operation and BIST operation makes it possible to create compact and efficient test data, improve self-test efficiency, and improve LSI performance. It is an object of the present invention to provide a self-test function built-in type circuit which is designed to reduce computer resources and design man-hours when designing a circuit.

[0024]

FIG. 1 is a block diagram showing the principle of the first invention. In FIG. 1, reference numeral 1 is an internal circuit that performs a predetermined function. A plurality of scan paths 2 are formed in advance, and a data compressor 4 that compresses and stores output data from each scan path 2 is incorporated therein.

Further, 5 is a scan-in pin capable of supplying data to each scan path 2, and 6 is a scan path 2
With the logic gates 6 provided for each, each logic gate 6 is
Output data from each scan pass 2 and each scan
The logical operation is performed with the input data from the scan-in pin 5 corresponding to the path 2. Then, in the first invention, when the data in the undefined state on the scan path 2 is read out to the data compressor 4 via the logic gate 6, the scan in.
The input data from the pin 5 to the logic gate 6 is set to a value that masks the undefined data in the logic gate 6 (claim 1).

When data is read from each scan path 2, if the data read pattern including the input data from each scan-in pin 5 is continuous in the same shape, the pattern and the number of consecutive patterns are set. May be used (Claim 2). It also has an external input pin 7 for inputting a switching signal in order to switch between the scan operation for the scan path 2 and the self-test operation using the data compressor 4, and the switching signal from this external input pin 7 is supplied to a logic gate. 6, the output signal from each scan path 2 to the data compressor 4 is masked in the logic gate 6 by switching the switching signal from the external input pin 7 to the scan operation side during the initialization of the internal circuit 1. It may be provided (claim 3), or a prohibiting means for prohibiting the input of the clock signal to the data compressor 4 during the initialization of the internal circuit 1 may be provided (claim 4).

FIG. 2 is a block diagram of the principle of the second invention. In FIG. 2, similarly to the above, 1 is an internal circuit, 2 is a scan path, and 3 is a pattern generation incorporated in the internal circuit 1. The pattern generator 3 is for generating a test pattern to be given to each scan path 2. Further, an external input pin 7 for inputting a switching signal is provided in order to switch between the scan operation for each scan path 2 and the self-test operation using the pattern generator 3, and the scan operation is performed for each scan path 2. -In-pin 5 and selector 8 are provided.

Here, the scan-in pin 5 can supply data to each scan path 2, and the selector 8 responds to the switching signal from the external input pin 7 to each scan-in pin. One of the input data from 5 and the test pattern from the pattern generator 3 is switched and output to each scan path 2. In the second invention, during the normal self-test operation, the selector 8 is switched to the pattern generator 3 side by the switching signal from the external input pin 7, and the test signal supplied from the pattern generator 3 to each scan path 2 is tested. When a part of the pattern is corrected to an arbitrary value, the selector 8 is switched to the scan-in pin 5 side by the switching signal from the external input pin 7 and the scan-in pin 5 is set to an arbitrary value. Data is given to each scan pass 2 and written (claim 5).

When writing data to each scan path 2, a data writing pattern including input data from each scan-in pin 5 and a switching signal to the external input pin 7 is continuously formed in the same pattern. In this case, the description may be made using the pattern and the continuous number (claim 6). FIG. 3 is a block diagram of the principle of the third invention.
As shown in, the third invention is a combination of the first invention and the second invention described above. That is, like the above, 1 is an internal circuit, 2 is a scan path,
3 is a pattern generator, 4 is a data compressor, 5 is a scan-in pin, 6 is a logic gate, 7 is an external input pin, 8
Is a selector.

Then, during a normal self-test operation, the selector 8 is switched to the pattern generator 3 side by a switching signal from the external input pin 7. Further, when a part of the test pattern given from the pattern generator 3 to each scan path 2 is modified to an arbitrary value, the selector 8 is switched to the scan-in pin 5 by the switching signal from the external input pin 7. Then, the data set to an arbitrary value from the scan-in pin 5 is given to each scan path 2 and written.

On the other hand, when the indefinite state data on the scan path 2 is read out to the data compressor 4 via the logic gate 6, the scan-in pin 5 corresponding to the scan path 2 outputs the logic gate. The input data to 6 is set to a value that masks the undefined data in logic gate 6. Further, during initialization of the internal circuit 1, the switching signal from the external input pin 7 is switched to the scan operation side so that each scan path 2 can be connected to the data compressor 4.
The output data to the mask is masked in the logic gate 6 (claim 7).

When reading data from each scan path 2, if the data read pattern including the input data from each scan-in pin 5 is continuous in the same shape, the pattern and the number of consecutive patterns are set. (Claim 8), the data including the input data from each scan-in pin 5 and the switching signal to the external input pin 7 when writing data to each scan-path 2 If the writing patterns are continuous with the same pattern,
You may describe using the pattern and the continuous number (Claim 9).

Further, a prohibiting means for prohibiting the input of the clock signal to the data compressor 4 during the initialization of the internal circuit 1 may be provided (claim 10). Furthermore, the pattern generator 3
A scan chain consisting of the data compressor 4 and the data compressor 4 is configured as one chain in the boundary scan, and an instruction code for instructing the shift-in / shift-out operation and the self-test operation of the scan chain is issued. It may be configured to be pre-assigned as the operation code of the register (claim 11).

[0034]

In the self-test function built-in circuit according to the first aspect of the present invention described above, by appropriately setting the state value of the external input pin 7, when the undefined state data is read from the scan path 2, the undefined state is read. Can be masked by the logic gate 6, and the compressed data in the data compressor 4 can be prevented from becoming an indefinite value (claim 1).

When the pattern for reading data from each scan pass 2 is continuous in the same pattern, it can be described compactly by using the pattern and the number of consecutive patterns (claim 2). Further, by applying the switching signal from the external input pin 7 to the logic gate 6 and switching the switching signal from the external input pin 7 to the scan operation side during initialization of the internal memory element and the like in the internal circuit 1.
The output data from each scan path 2 to the data compressor 4 is masked in the logic gate 6 so that the initial value of the data compressor 4 can be held, and the data compressor 4 is initialized during the initialization of the internal circuit 1. The contents of can be prevented from being destroyed (Claim 3).

Further, during the initialization of the internal circuit 1, it is also possible to prohibit the input of the clock signal to the data compressor 4 by the prohibiting means and stop the application of the clock signal to the data compressor 4 so as to compress the data. The contents of the data compressor 4 can be retained, and the contents of the data compressor 4 can be prevented from being destroyed during the initialization of the internal circuit 1 (claim 4). In the self-test function built-in circuit of the second invention described above, the self-test operation is executed by switching the selector 8 to the pattern generator 3 side by the switching signal from the external input pin 7.
During this self-test operation, the selector 8 is switched to the scan-in pin 5 side by the switching signal from the external input pin 7, and the data set to an arbitrary value from the scan-in pin 5 is sent to each scan path 2. By applying and writing, a part of the test pattern applied from the pattern generator 3 to each scan path 2 can be modified to an arbitrary value (claim 5).

When the patterns for writing data to each scan pass 2 are continuous in the same pattern, it can be described compactly by using the pattern and the number of consecutive times (claim 6). . In the self-test function built-in circuit of the third invention described above, the self-test operation is executed by switching the selector 8 to the pattern generator 3 side by the switching signal from the external input pin 7. During the test operation, the selector 8 is switched to the scan-in pin 5 side by the switching signal from the external input pin 7, and the data set to an arbitrary value is supplied from the scan-in pin 5 to each scan path 2. By writing, a part of the test pattern provided from the pattern generator 3 to each scan path 2 can be modified to an arbitrary value.

On the other hand, during the self test operation, scan in
By setting the state value of pin 5 as appropriate, the scan
When the data in the undefined state is read from the path 2, the data in the undefined state can be masked by the logic gate 6, and the compressed data in the data compressor 4 can be prevented from becoming an undefined value. Further, during the initialization of the internal memory element and the like in the internal circuit 1, by switching the switching signal from the external input pin 7 to the scan operation side, each scan
The output data from the path 2 to the data compressor 4 is masked in the logic gate 6 so that the initial value of the data compressor 4 can be held, and the contents of the data compressor 4 can be maintained during initialization of the internal circuit 1. It can be prevented from being destroyed (Claim 7).

When a pattern for reading data from each scan pass 2 and a pattern for writing data to each scan pass 2 are continuous in the same shape, the pattern and the number of consecutive patterns are set. Can be used for compact description (claims 8 and 9). Also, by prohibiting the input of the clock signal to the data compressor 4 by the prohibiting means during the initialization of the internal circuit 1 and stopping the application of the clock signal to the data compressor 4, The contents can be retained, and the contents of the data compressor 4 can be prevented from being destroyed during the initialization of the internal circuit 1 (claim 1).
0).

Further, the scan chain consisting of the pattern generator 3 and the data compressor 4 is set as one chain in the boundary scan, and the shift-in / shift-out operation and the self-test operation of the scan chain are instructed respectively. The present invention can also be applied to a circuit adopting the boundary scan method by pre-allocating the instruction code for the above as the operation code of the instruction register (claim 11).

[0041]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing a configuration of a self-test function built-in type circuit as one embodiment of the present invention. In FIG. 4, 10 is a circuit (for example, LSI) of the present embodiment, 11
Is an internal circuit that performs a predetermined function on the circuit 10, and the internal circuit 11 is composed of a large number of circuit components, for example, flip-flops (FF).

In order to self-test the internal circuit 11, a plurality of (three in the figure) scan paths 12A to 12C are formed in advance on the circuit 10, and each of the scan paths 12A to 12C is A plurality (five in the figure) of flip-flops 101 are connected in a chain.
The circuit 10 also includes each scan path 12A-12C.
Scan-in pin (SI pin) 15A to 15B for giving test data (test pattern) to
And a scan out pin (SO pin) for extracting output data from each of the scan paths 12A to 12C
19A to 19C and a scan clock pin (SCK pin) 20 for inputting a clock signal for operating the circuit 10 are provided as external input pins, and a scan operation and self-test for each scan path 12A to 12C. A BE (BIST Enable) pin 17 for inputting a switching signal to switch to the (BIST) operation is provided as an external input pin. The clock signal input from the SCK pin 20 is used for all flip-flops on the circuit 10.
It is adapted to be input to the clock terminal of the flop 101.

Further, 13 is an LFSR (pattern generator) which is incorporated in the circuit 10 to generate a test pattern to be input to each of the scan paths 12A to 12C, and 14 is incorporated in the circuit 10 and is included in each of the scan paths 12A to 12C. 12C
Is an MISR (data compressor) for compressing and storing output data from the. Where LFSR13 and MISR
As shown in FIGS. 6 and 5, 14 is composed of a plurality of shift registers 22 with feedback via a plurality of exclusive OR (XOR) gates 21, respectively. Then, each shift register 22 is adapted to perform a shift operation by the clock signal from the SCK pin 20. Further, as shown in FIG. 4, the scan-in pin (SI pin) 15 is connected to the LFSR 13 and the MI
SR14 has a scan out pin (SO pin) 19
Is connected.

By the way, as shown in FIGS. 4 and 5, the line on the output side of each of the scan paths 12A to 12C is SO
Pins 19A to 19C are connected and
MI via ND gates (logic gates) 16A to 16C
It is connected to each XOR gate 21 in SR14. The AND gates 16A to 16C output data from the scan paths 12A to 12C, input data from the SI pins 15A to 15C corresponding to the scan paths 12A to 12C, and a switching signal from the BE pin 17. A signal which is turned off "0" during the scan operation and turned on "1" during the BIST operation] is calculated, and the logical product of these signals is calculated and output to each XOR gate 21 in the MISR 14.

As shown in FIGS. 4 and 6, the lines on the input side of each of the scan paths 12A to 12C are connected to SI pins 15A to 15 via selectors 18A to 18C, respectively.
It is connected to C and LFSR13. Each selector 18
A to 18C are responsive to the switching signal from the BE pin 17,
Input data from each SI pin 15A to 15C and LFS
One of the test patterns from R13 is switched and output to each of the scan paths 12A to 12C. That is, each of the selectors 18A to 18C outputs the input data from each of the SI pins 15A to 15C to each of the scan paths 12A to 12C when the scan operation is selected by the switching signal from the BE pin 17, while
When the BIST operation is selected by the switching signal from the BE pin 17, the test pattern from the LFSR 13 is output to each of the scan paths 12A to 12C.

With the above-described configuration, in the self-test function built-in circuit of this embodiment, the selector 18A-18C is set to the SI pin 15A-15C side by turning off the switching signal to the BE pin 17 to "0". The output from each AND gate 16A to 16C to the MISR 14 is fixed to "0" and the scan operation is performed in each scan path 12A to 12C of the circuit 10.

That is, during the scan operation, the flip-flop 101 on each of the scan paths 12A to 12C operates as a shift register, and by supplying a clock signal from the SCK pin 20, each of the SI pins 15A to 15C.
The value given to C is sequentially shifted in to the next flip-flop 101 on each scan path 12A to 12C via each selector 18A to 18C. At the same time, the values of the flip-flops 101 on the scan paths 12A to 12C are sequentially scanned out to the SO pins 19A to 19C.

On the other hand, by turning on the switching signal to the BE pin 17 to "1", the selectors 18A to 18C are switched to the LFSR 13 side, and the output from the AND gates 16A to 16C to the MISR 14 is changed to each scan. Output data from paths 12A-12C and SI pin 15A corresponding to each scan path 12A-12C
The logical product of the input data from ˜15C and the circuit 10
The BIST operation is performed in each of the scan paths 12A to 12C.

That is, during BIST operation, LFSR1
3 generates a pseudo-random number and each scan path 12A-12
Flip-flop 101 on C, and flip-flop 101 on each scan path 12A-12C
Operates as a shift register and provides a clock signal from SCK pin 20 to allow each scan path 12
The values given to A to 12C are the respective selectors 18A to 18A.
It is sequentially shifted in to the next flip-flop 101 via C.

At the same time, each scan path 12A-1
Value of flip-flop 101 on 2C (output data)
Are sequentially shifted out, and each AND gate 16
After the logical product with the input data from the SI pins 15A to 15C corresponding to the scan paths 12A to 12C is calculated by A to 16C, the logical relationship is compressed and stored in the MISR 14. Finally, by reading the data compressed and stored in the MISR 14 from the SO pin 19, it is possible to judge the defect of the circuit (LSI) 10.

At this time, a normal ATPG (Automatic Te
st Pattern Generation (automatic test pattern generation), it is not necessary to initialize all the internal storage, so an undefined state may appear in the output data from each of the scan paths 12A to 12C. As shown in FIG. 5, the MISR 14 is composed of a shift register 22 with feedback, and the output data from each of the scan paths 12A to 12C is compressed to the shift register 22 in the MISR 14 through the XOR gate 21. When an indeterminate state appears in the output data from each of the scan paths 12A to 12C as described above, the XO gate 21 is used, so that the indeterminate state is taken into the shift register 22 as it is, and further, there is a feedback loop. When one shift register 22 becomes indeterminate, all the shift registers 22 become indeterminate.

Therefore, in this embodiment, during the BIST operation, as shown in FIGS.
Output data from each scan path 12A to 12C and the SI pin 15A corresponding to each scan path 12A to 12C by each AND gate 16A to 16C without directly inputting the output data from the output path 12A to 12C to the MISR 14.
The logical product with the input data from ˜15C is calculated, and MI is calculated.
It is output to SR14.

That is, in this embodiment, the scan path 12
When the output data from A to 12C is in an indefinite state, the value (input data) from the SI pins 15A to 15C of the corresponding scan paths 12A to 12C is set to "0", and the corresponding AND is set. Gates 16A-16C
To the MISR 14 are set to "0", and the undefined data from the scan paths 12A to 12C to the MISR 14 are masked by the AND gates 16A to 16C.

As described above, by appropriately setting the state values of the SI pins 15A to 15C, the scan path 12A
When undefined data is read from ~ 12C,
The data in the indefinite state can be masked by the AND gates 16A to 16C, and it is possible to reliably prevent the compressed data in the MISR 14 from becoming an indefinite value. Here, as a specific example, when scan-out data as shown in FIG. 8 is obtained, data in an undefined state (“U (Unknown)” in FIG. 8) according to the present embodiment is taken into the MISR 14. An example of creating a test pattern that will never occur will be described.

9 to 11, the scan circuit shown in FIG. 17, the BIST circuit shown in FIG. 18, and the present embodiment shown in FIG. 4 (FIG. 5) for the scan out data shown in FIG. 3 shows an example of description of a data read pattern (test data) by the circuit of FIG. 9 to 1
1, "N" indicates a negative pulse clock signal input from the SCK pin, and "X" of the output data output from the SO pin outputs a value of "0" or "1" which is not indefinite. Which indicates that.

As shown in FIG. 9, since the scan circuit requires the pattern description for the number of flip-flops to be scanned, the scan-out data shown in FIG. Is described. In large-scale LSI, flip-flops on one scan path
Since the number of flops is extremely large, the test data will be very large.

As shown in FIG. 10, in the BIST circuit,
By using the repeat descriptor [REPEAT (repeat start) / REPEND (repeat end)], the test data can be described in three lines for the scan-out data shown in FIG. Note that the repeat descriptor "REPEA
The pattern enclosed by "T" and "REPEND" is repeated the number of times specified after the repeat descriptor "REPEAT." However, as described above, the scan description shown in FIG. If the out data is processed, the MISR 14 will be loaded with an undefined value "U", and therefore cannot be used as test data.

On the other hand, in the circuit of this embodiment, as shown in FIG.
As shown in FIG. 8, by using the repetition descriptor, the test data can be described in 7 lines, which is less than the case of the scan circuit shown in FIG. 9, with respect to the scan out data shown in FIG. become. In fact, MISR1
A pattern for reading the data compressed from 4 to the outside is also necessary, but can be ignored as compared with the scan-out pattern (the number of flip-flops to several thousands).

In the scan-out data shown in FIG. 8, the fifth undefined value "U" is the scan paths 12A-1.
Since it is output from 2C, the state value of the corresponding SI pins 15A to 15C is set to "0" in the fifth pattern and A
The value from the ND gates 16A to 16C to the MISR 14 is set to "0", and the undefined value "U" from the scan paths 12A to 12C is masked by the corresponding AND gates 16A to 16C. Since the values other than the fifth are not indeterminate, each SI
Set the state value of pins 15A-15C to "1" and output data from scan paths 12A-12C to MISR1.
Enter in 4. At this time, as shown in FIG. 11, the same pattern (1st-4th and 6-12th) can be put together using a repetition descriptor.

Now, as described above with reference to FIG. 6, the LFSR
13 is also composed of a shift register 22 with feedback, and its output (test pattern) and each external SI
Input data from the pins 15A to 15C corresponds to each selector 1
Each scan path 12A-12C through 8A-18C
Is input to When the BE pin 17 is off “0”, each SI
When the values of the pins 15A to 15C are selected by the selectors 18A to 18C and are shifted into the scan paths 12A to 12C and the BE pin 17 is on "1", the LFS is set.
The output of R13 is selected by each of the selectors 18A to 18C and shifted into each of the scan paths 12A to 12C.

Normally, the BE pin 17 is turned on "1",
The output from the LFSR 13 is shifted in, but when it is desired to clip a specific flip-flop 101 on each scan path 12A to 12C or set a special value for the flip-flop 101, the BE pin 17 is used. Can be turned off "0" and desired data can be shifted in from each SI pin 15A to 15C.

In ATPG, a test pattern for detecting one fault in the LSI internal circuit is created. The external input or flip target to be scanned that must be set to actually detect the failure.
The number of flops is small, and there is no problem even if a pseudo random number generated from the BIST circuit is set. Such a test pattern can be created by appropriately switching between the scan operation and the BIST operation using the circuits shown in FIGS. Further, by using the above-mentioned repeated descriptor, the test data description at the time of BIST operation can be reduced, so that the total test data amount can be greatly reduced.

Here, as a concrete example, a test for the case where scan-in data as shown in FIG. 12 is set in each flip-flop on the scan path.
An example of creating a pattern will be described. In addition, in FIG.
“D0” and “D1” are values determined by ATPG and are specified as either “0” or “1”, but the other parts indicated by “0” or “1” are random numbers. There is no problem if you replace it.

Further, FIGS. 13 to 15 are respectively shown in FIG.
An example of description of the data write pattern (test data) by the scan circuit shown in FIG. 17, the BIST circuit shown in FIG. 18, and the circuit of this embodiment shown in FIG. 4 (FIG. 6) for the scan-in data shown in FIG. Is shown. As shown in FIG. 13, the scan circuit requires pattern description for the number of flip-flops to be scanned.
For the scan-in data shown in 2, test data is described in 12 lines. In this case, it is possible to set specific values “D0 (0)” and “D1 (1)” for a specific flip-flop by sequentially writing data, but in a large-scale LSI, Since the number of flip-flops on one scan path is extremely large, the test data will be very large.

As shown in FIG. 14, in the BIST circuit,
By using the repeat descriptor [REPEAT / REPEND], 3 is obtained for the scan-in data shown in FIG.
Lines can describe test data. The functions of the repeat descriptors "REPEAT" and "REPEND" are as described above with reference to FIG. However, in such a data description, as shown in FIG. 12, it is not possible to set specific values “D0 (0)” and “D1 (1)” for a specific flip-flop, and the LFSR 13 causes Since the generated pseudo-random number is set, the target failure cannot always be detected.

On the other hand, in the circuit of this embodiment, as shown in FIG.
As shown in FIG. 12, by using the repetition descriptor, the test data can be described in 8 lines, which is smaller than the case of the scan circuit shown in FIG. 13, with respect to the scan in data shown in FIG. become. In the scan-in data shown in FIG. 12, it is necessary to forcibly set "0" to the fourth and "1" to the fifth, so when shifting in the fourth and fifth data, , BE pin 17 is set to off “0”, selectors 18A to 18C are switched to SI pins 15A to 15C, and SI pin 1
The value "0" or "1" set from 5A to 15C is sequentially shifted in to each scan path 12A to 12C.

In the other portions, since the random number value may be shifted in, the BE pin 17 is always set to "1", the selectors 18A to 18C are switched to the LFSR13 side, and the output value from this LFSR13 ( Pseudo random numbers) are shifted in to the scan paths 12A to 12C. At this time, as shown in FIG. 15, the same pattern (1
~ 3rd and 6-12th) can be grouped using a repetition descriptor.

In this way, during the BIST operation, the BE
Selectors 18A to 18 according to the switching signal from pin 17
By switching C to each of the SI pins 15A to 15C, and writing and setting the data set to an arbitrary value from each of the SI pins 15A to 15C to each of the scan paths 12A to 12C, the data is written from the LFSR 13 to each of the scan paths 12A to 12C.
A part of the test pattern given to C can be modified to an arbitrary value.

On the other hand, the internal circuit 11 of the circuit (LSI) 10
Since the internal storage element of the internal storage element LSI is in an indefinite state when the power is turned on, the state of the internal storage element is initialized before performing BIST.
In SR14, the shift register 22 shifts each time the clock signal is applied once, and the contents thereof are updated, and the updating is performed even while the initialization pattern of the internal storage element is being applied. To deal with this, as described above, ATP
The G program needs to monitor the contents of the MISR 14, which complicates the processing.

Therefore, in this embodiment, as shown in FIGS. 4 and 5, the BE pin 17 is connected to the AND gates 16A to 16C together with the output data from the SI pins 15A to 15C and the scan paths 12A to 12C. It is input and outputs the logical product of these to each shift register 22 of the MISR 14. As a result, the shift register 22 of the MISR 14
If all are initialized to "0", the switching signal to the BE pin 17 is turned off "0" or the SI pins 15A to 15C are
The contents of all shift registers 22 in the MISR 14 can be held at "0" by setting all the input data to "0".

In the system operation as the normal circuit 10 or the scan operation, the switching signal input to the BE pin 17 is off "0", so that the MIS is performed.
The content of each shift register 22 in R14 is held at "0". Further, even during the BIST operation, the contents of each shift register 22 in the MISR 14 can be held at "0" by setting all the input data to the SI pins 15A to 15C unrelated to the BIST operation to "0".

Furthermore, during the initialization prior to the BIST operation, the contents of each shift register 22 in the MISR 14 are held at "0" by holding the switching signal to the BE pin 17 off "0". Therefore, especially during the initialization prior to the BIST operation, the output data from each scan path 12A-12C to the MISR 14 is transferred to each AND gate 16A.
It becomes possible to hold the initial value of the MISR 14 by being masked at 16C, and it is possible to reliably prevent the contents of the MISR 14 from being destroyed.

As another means for holding the contents of each shift register 22 in the MISR 14 during initialization of the internal circuit 11 (internal storage element), there is, for example, one shown in FIG. 4 and 5, each AND gate 16A
Although the switching signal from the BE pin 17 is input to the 16C to 16C, in FIG.
By providing 25, MISR during initialization
The contents of each shift register 22 in 14 are retained.

That is, the clock signal stop unit 2 shown in FIG.
5 is an inhibit pin (IH pin) 23 and an OR
It is composed of a gate 24. The IH pin 23 is provided in the circuit 10 as an external input pin, and is used to stop applying the clock signal from the SCK pin 20 to each shift register 22 in the MISR 14.
The clock stop signal input to the pin 23 is set from off "0" to on "1".

Further, the OR gate 24 is connected to the SCK pin 20.
From the IH pin 23 and the clock signal from the IH pin 23 are calculated and applied to each shift register 22 in the MISR 14. As a result, regardless of the contents of each shift register 22 in the MISR 14, the IH pin 23
By setting the clock stop signal to
The clock signal from the SCK pin 20 is not applied to each shift register 22 in the MISR 14.

Therefore, the update (shift operation) in each shift register 22 is not performed, and the values of all the shift registers 22 can be held as they are. Even with the configuration shown in FIG. 7, during initialization before the BIST operation, MISR1
It is possible to reliably prevent the contents of 4 from being destroyed. However,
In the circuit configuration shown in FIG. 7, as shown in FIGS.
The switching signal from the pin 17 is applied to each AND gate 16A to 16A.
External input pin (IH pin 2
Although 3) is required one more, there is an advantage that an arbitrary MISR 14 value can be designated and held.

By the way, in the example described above with reference to FIGS. 4 to 15, the case where the present invention is applied to the general scan system has been described, but the present invention is also applied to the boundary scan system as shown in FIG. It In the boundary scan method, the boundary scan cells are arranged between the external input pin on the circuit and the internal circuit, and all of them are connected to each other to connect the test data in pin (TD).
Configure a boundary scan chain from the I pin) to the test data out pin (TDO pin),
Each boundary scan cell in this boundary scan chain is controllable and observable.

In FIG. 16, reference numeral 30 denotes a boundary scan LSI, and this boundary scan LSI 3
0 above the boundary scan chain 31A
And two internal scan chains 31B and 31C are formed. Then, as shown in FIG. 16, in the boundary scan LSI 30, these scan chains (scan paths) 31A to 31C are arranged in place of the scan paths 12A to 12C shown in FIGS. 4 to 7. There is. However, the boundary scan L shown in FIG.
In SI30, instead of SI pin 15A, TDI pin 32
Is provided, and the TDO is used instead of the SO pin 19A.
A pin 33 is provided. In addition, in FIG. 16, LFSR
13, MISR 14, AND gates 16A to 16C, B
The E pin 17 and the selectors 18A to 18C function in exactly the same manner as described above with reference to FIGS.

Further, in FIG. 16, reference numeral 34 is a test clock pin (TCK pin) for inputting a test clock signal for boundary scan, and 35 is a selection signal for selecting a test mode by boundary scan. Test mode select pin (T
MS pins) and 36 are test access port (TAP) circuits which operate in synchronization with a test clock signal from the TCK pin 34 in response to a selection signal from the TMS pin 35. The TAP circuit 36 is a boundary Scan LS
This is for accessing each test mechanism on the I30 and controlling the boundary scan operation.

Further, 37 is from TDI pin 32 to TDO.
Boundary scan chain 3 between pins 33
Bypass register for bypassing 1A, 38 is an instruction register that holds instruction codes according to various control signals from the TAP circuit, 39 is a multiplexer, and this multiplexer 39 responds to the instruction codes from the instruction register 38. Works, Boundary Scan Chain 3
1A, the scan out data from the MISR 14 and the data from the bypass register 37 are multiplexed and output to the TDO pin 33.

The boundary scan chain 31A, the TDI pin 32, the TDO pin 33, and the TC described above are used.
The components such as the K pin 34, the TMS pin 35, the TAP circuit 36, the bypass register 37, the instruction register 38, and the multiplexer 39 are common in the boundary scan system. In the boundary scan method, it is necessary to assign various test modes to the operation code of the instruction register 38, and the instruction code for instructing the BIST operation is pre-assigned as the only operation code of the instruction register 38. At the time of TC
By applying the test clock signal from the K pin 34, the BIST circuits (LFSR13, MISR14, etc.) are operated.

Further, the scan code consisting of the LFSR 13 and MISR 14 is treated as one chain in the boundary scan, and the instruction code for instructing the shift-in / shift-out operation of the scan chain is stored in the instruction register 38. Pre-assigned as the only action code. The structure of the test data in the boundary scan LSI 30 having the above structure is shown below.

Initialization of the TAP circuit 36. Selection of LFSR13 / MISR14 (setting of instruction code). Initialization of LFSR13 / MISR14. Selection of BIST circuit (setting of instruction code). Operation of the BIST circuit (shift-in from the LFSR 13 to the boundary scan chain 31A / internal scan chains 31B and 31C).

Application of system clock (test clock) signal. Operation of the BIST circuit (data compression from the boundary scan chain 31A / internal scan chains 31B and 31C to the MISR 14). Selection of LFSR13 / MISR14 (setting of instruction code). Data read from MISR 14.

The test data in the items and the operations for operating the BIST circuit described above are the same as those shown in FIGS. 11 and 15. As described above, the LS using the general scan is applied to the circuit (LSI 30) adopting the boundary scan method according to the present invention.
Like I, an efficient test pattern can be created with a small number of test data descriptions.

Thus, according to one embodiment of the present invention,
It is possible to prevent the data in the undefined state from being taken into the MISR 14 and the contents of the MISR 14 from being destroyed during the initialization, so that the BIST can be performed reliably and easily. Further, by combining the scan operation and the BIST operation, a small number of gates (AND gates 16A to 16C) can be obtained.
Etc.), it is possible to create very compact, efficient and general-purpose test data, improve BIST efficiency, and
There is an advantage that computer resources and design man-hours at the time of designing a circuit such as an LSI can be significantly reduced.

Conventionally, the pattern output from the LFSR 13 was applied to the internal circuit without processing, but in this embodiment,
As described above, the scan operation and the BIST operation are combined, and the output of the LFSR 13 and the input data from the SI pins 15A to 15C and the like are switched by the selectors 18A to 18C, thereby being applied to a specific circuit in the internal circuit 11. The value can be changed arbitrarily.

In the above-described embodiment, the MISR 14 as the data compressor is used in the analysis of the expected output value of the LSI (circuits 10, 30) in the BIST (Built-In Self Test).
However, the present invention is not limited to this, and other than the analysis method using MISR,
For example, transition count method (Transition Count: a method of analyzing the number of times the output transitions from “0” to “1” and the number of transitions from “1” to “0”), the syndrome method (1's counting: appears in the output. It can also be applied to a method of analyzing the number of times "1").

[0089]

As described above in detail, according to the self-test function built-in type circuit of the present invention, it is possible to prevent the data in the indeterminate state from being taken in by the data compressor and the compressed data in the data compressor to have an indefinite value. It can be surely prevented, and the self-test can be surely performed (claims 1 and 7).

Further, during the initialization of the internal circuit, the data in the data compressor can be held, the contents of the data compressor can be surely prevented from being destroyed, and the contents of the data compressor can be monitored. It is possible to easily carry out the self-test without the need for complicated processing such as performing (Claims 3, 4,
7, 10). Furthermore, by combining the scan operation and the self-test operation, a part of the test pattern given from the pattern generator 3 to each scan path 2 can be modified to an arbitrary value (claims 5, 7). ),
Compact, efficient and versatile test data can be created (Claims 2, 6, 8 and 9), efficiency of self-test is improved, and computer resources and design man-hours at the time of circuit design of LSI etc. are greatly increased. Can be reduced to

Furthermore, the present invention can be applied to a circuit adopting the boundary scan method, and in this case, the same effect as described above can be obtained (claim 11).

[Brief description of drawings]

FIG. 1 is a principle block diagram of a first invention.

FIG. 2 is a principle block diagram of a second invention.

FIG. 3 is a principle block diagram of a third invention.

FIG. 4 is a block diagram showing a configuration of a self-test function built-in type circuit as one embodiment of the present invention.

FIG. 5 is a block diagram showing an extracted portion related to the data compressor of the present embodiment.

FIG. 6 is a block diagram showing an extracted portion of a pattern generator of the present embodiment.

FIG. 7 is a block diagram showing an example of a clock stop circuit (inhibition means) of the data compressor of the present embodiment and a portion related to the clock stop circuit, which is extracted and shown.

FIG. 8 is a diagram showing an example of scan out data.

FIG. 9 is a diagram showing an example of a data read pattern by a conventional scan circuit.

FIG. 10 is a diagram showing an example of a data read pattern by a conventional BIST type circuit.

FIG. 11 is a diagram showing an example of a data read pattern of the present embodiment.

FIG. 12 is a diagram showing an example of scan-in data.

FIG. 13 is a diagram showing an example of a data write pattern by a conventional scan circuit.

FIG. 14 is a diagram showing an example of a data write pattern by a conventional BIST type circuit.

FIG. 15 is a diagram showing an example of a data writing pattern of the present embodiment.

FIG. 16 shows a boundary scan type LSI according to the present invention.
It is a block diagram which shows the structural example at the time of applying to.

FIG. 17 is a block diagram showing a configuration example of a conventional scan circuit.

FIG. 18 is a block diagram showing a configuration example of a conventional BIST type circuit.

[Explanation of symbols]

1 Internal Circuit 2 Scan Path 3 Pattern Generator 4 Data Compressor 5 Scan In Pin 6 Logic Gate 7 External Input Pin 8 Selector 10 Circuit 11 Internal Circuit 12A-12C Scan Path 13 LFSR (Pattern Generator) 14 MISR (Data Compressor) 15, 15A to 15C Scan In Pin (SI Pin) 16A to 16C AND Gate (Logic Gate) 17 BE Pin (External Input Pin) 18A to 18C Selector 19, 19A to 19C Scan Out Pin (SO
Pin) 20 scan clock pin (SCK pin) 21 exclusive OR (XOR) gate 22 shift register 23 inhibit pin (IH pin) 24 OR gate 25 clock signal stop unit (prohibition means) 30 boundary scan LSI 31A Boundary scan chain (scan
31B, 31C Internal scan chain (scan path) 32 Test data in pin (TDI pin) 33 Test data out pin (TDO pin) 34 Test clock pin (TCK pin) 35 Test Mode select pin (TMS pin) 36 Test access port (TAP) circuit 37 Bypass register 38 Instruction register 39 Multiplexer 101 Flip flop (circuit component)

Claims (11)

[Claims] 1. An internal circuit having a predetermined function is provided, and in order to self-test the internal circuit, output data from each of a plurality of scan paths formed in advance on the internal circuit is compressed and stored. It is a self-test function built-in circuit that incorporates a data compressor, and scan-in circuit that can supply data to each scan path.
A pin is provided for each scan path, and a logic gate for performing a logical operation of the output data from each scan path and the input data from the scan-in pin corresponding to each scan path is provided for each scan path. Therefore, when undefined data on the scan path is read out to the data compressor via the logic gate, the input data from the scan-in pin corresponding to the scan path to the logic gate is input. Is set to a value that masks the data in the indeterminate state in the logic gate. 2. When data is read from each scan path, if the data read pattern including the input data from each scan-in pin is continuous in the same pattern, the pattern and the number of consecutive patterns are used. The self-test function built-in circuit according to claim 1, characterized in that 3. An external input pin for inputting a switching signal to switch between a scan operation for the scan path and a self-test operation using the data compressor, and a switch signal from the external input pin is provided. The output data from each scan path to the data compressor is masked in the logic gate by switching the switching signal from the external input pin to the scan operation side during initialization of the internal circuit. The self-test function built-in circuit according to claim 1 or 2, characterized in that: 4. The self-test function according to claim 1, further comprising a prohibiting unit for prohibiting input of a clock signal to the data compressor during initialization of the internal circuit. Embedded circuit. 5. A pattern having an internal circuit that performs a predetermined function and generating a test pattern to be applied to each of a plurality of scan paths formed in advance on the internal circuit in order to self-test the internal circuit. A self-test function built-in circuit incorporating a generator, which has an external input pin for inputting a switching signal to switch between a scan operation for each scan path and a self-test operation using the pattern generator. , Scan in that can provide data to each scan path
Pin and the scan signal according to the switching signal from the external input pin.
Each scan path is provided with a selector that switches between one of the input data from the IN pin and the test pattern from the pattern generator and outputs it to each scan path. When the selector is switched to the pattern generator side by a switching signal from the external input pin and a part of the test pattern given from the pattern generator to each scan path is corrected to an arbitrary value, The selector is switched to the scan-in pin side by a switching signal from an external input pin, and data set to an arbitrary value from the scan-in pin is given to each scan path for writing. Self-test function built-in circuit. 6. A data write pattern including input data from each scan-in pin and a switching signal to the external input pin when writing data to each scan path, which are continuous in the same pattern. 6. The self-test function built-in circuit according to claim 5, characterized in that it is described using the pattern and the continuous number. 7. A pattern having an internal circuit that performs a predetermined function and generating a test pattern to be applied to each of a plurality of scan paths formed in advance on the internal circuit in order to self-test the internal circuit. A self-test function built-in circuit incorporating a generator and a data compressor for compressing and storing output data from each of a plurality of scan paths formed in advance on the internal circuit. A scan-in which has an external input pin for inputting a switching signal to switch between a scan operation for a path and a self-test operation using the pattern generator and the data compressor, and which can supply data to each scan path.・
A pin, output data from each scan path, input data from the scan-in pin corresponding to each scan path, and a switching signal from the external input pin; Depending on the switching signal from the external input pin, each scan
Each scan path is provided with a selector that switches between one of the input data from the IN pin and the test pattern from the pattern generator and outputs it to each scan path. When the selector is switched to the pattern generator side by a switching signal from the external input pin and a part of the test pattern given from the pattern generator to each scan path is corrected to an arbitrary value, The selector is switched to the scan-in pin side by a switching signal from the external input pin, and data set to an arbitrary value from the scan-in pin is given to each scan path and written, while on the scan path When the indeterminate state data of the scan path is read out to the data compressor through the logic gate, the scan path corresponding to the scan path is scanned. Input data from the pin to the logic gate is set to a value that masks the data in the undefined state in the logic gate, and a switching signal from the external input pin is sent to the scan operation side during initialization of the internal circuit. A circuit with a built-in self-test function, wherein the output data from each scan path to the data compressor is masked at the logic gate by switching. 8. When data is read from each scan path, if the data read pattern including the input data from each scan-in pin is continuous in the same pattern, the pattern and the number of consecutive data are used. 8. The self-test function built-in circuit according to claim 7, characterized in that: 9. A data write pattern including input data from each scan-in pin and a switching signal to the external input pin when writing data to each scan path is continuous in the same pattern. 9. The self-test function built-in circuit according to claim 7, wherein the pattern is described by using the pattern and the continuous number. 10. The self-test according to claim 7, further comprising prohibiting means for prohibiting input of a clock signal to the data compressor during initialization of the internal circuit. Function-embedded circuit. 11. A scan chain composed of the pattern generator and the data compressor is configured as one chain in a boundary scan, and a shift-in / shift-out operation and a self-test operation of the scan chain are performed respectively. 11. The self-test function built-in circuit according to claim 7, wherein an instruction code for instructing is pre-assigned as an operation code of an instruction register.