JP2002340988A - Semiconductor integrated circuit and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its test method which can increase a toggle rate of an internal circuit without increasing manufacturing cost in a burn-in test, and improve easily stress coverage. SOLUTION: The test method includes a first step for performing a burn-in test by operating a microcomputer by executing a program stored in a ROM, and a second step for performing a burn-in test by using scan which is executed by a scan chain with a scan cell. Both the first step and the second step are executed in one burn-in test by switching the first step and the second step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a test method therefor. In particular, the present invention relates to a semiconductor integrated circuit in a burn-in test using a built-in ROM and a scan circuit and a test method thereof.

[0002]

2. Description of the Related Art In order to obtain the reliability of a semiconductor integrated circuit,
A burn-in test is performed as screening. In general, the burn-in test is performed on a packaged finished product.In performing a test, a signal having several different frequencies is supplied from an external signal source to a terminal requiring a test. The internal circuit is operating.

In the burn-in test, since a sufficient stress must be applied to the circuit, the operation of the semiconductor integrated circuit during the burn-in test must be such that the circuit operation rate is high. Such a circuit operation rate is called stress coverage, and a toggle rate is often used as an index indicating the circuit operation rate. Here, the toggle ratio indicates the ratio of nodes that have changed from “1” to “0” or from “0” to “1” with respect to all the nodes inside the circuit. In the burn-in test, various devices have been devised to make the toggle rate close to 100%.

For example, in a microcomputer with a built-in ROM, each node in the microcomputer is operated by executing a program stored in the built-in ROM at the time of a burn-in test. By improving the program, it is possible to improve the toggle rate during the burn-in test of the microcomputer.

Further, as disclosed in Japanese Patent No. 3070455, a test circuit having a boundary scan test function and having an input / output circuit in which the output of the last stage is connected to the input of the first stage, By repeating the shift-capture operation in the scan mode at the time of the burn-in test, it is possible to operate the internal circuit at random to increase the toggle rate.

On the other hand, with the recent increase in the performance of electronic devices,
IEEE11 to facilitate printed circuit board testing
49.1 has been standardized. This standard, also known as JTAG, defines a hardware architecture and mechanism for implementing cost-saving tests using software.

A semiconductor integrated circuit equipped with a JTAG circuit has a reset terminal TRST, a clock terminal TCK, a mode select terminal TMS, a data input terminal TDI, a data output terminal TDO, and a boundary scan for holding other terminal states exclusively for JTAG. Register and TCK, T
A JTAG control unit that controls the JTAG operation using RST and TMS as inputs is provided.

In the JTAG control unit, the setting of the JTAG instruction and the setting of the TD are performed by operating a state machine that uses the input value of TMS sampled by TCK as a transition condition.
Fetching a JTAG instruction from I, fetching data into the boundary scan register, fetching the value of a terminal other than the JTAG terminal into the boundary scan register, and reading the value of the boundary scan register into the JTAG
A JTAG function such as setting to a terminal other than the terminal can be realized.

[0009]

However, when a program stored in the built-in ROM is used at the time of the burn-in test as described above, the number of nodes that can be operated by the program decreases as the circuit configuration becomes more complicated. Therefore, when a certain state is reached, there is a problem that it is difficult to further increase the toggle rate.

In the case of a test method in which a shift-capture operation in a scan mode is repeated during a burn-in test, in an LSI in which non-scan blocks and scan blocks coexist, the toggle rate in the non-scan blocks is determined only by the scan cells in the scan blocks. Is difficult to raise. That is, an LSI with a large circuit scale
However, since the number of logic circuit stages becomes deeper, there is a problem that it is difficult to increase the toggle rate of the internal circuit to a certain value or more only by random output of the input / output circuit.

Further, in the method of adding a boundary scan test function to an internal flip-flop (hereinafter, referred to as "FF") to improve the toggle rate, there is a problem that the circuit area increases with the addition of the function. Had occurred.

On the other hand, when increasing the toggle rate of the JTAG circuit in a semiconductor integrated circuit including the JTAG circuit, the JTAG circuit including the boundary scan register as described above is used.
It is necessary to operate the G circuit. For that, JTA
Since it is necessary to give a signal individually to the G dedicated terminal,
There is a problem that the number of signal sources supplied to the terminals during the burn-in test increases, and the manufacturing cost increases accordingly.

In the operation control of JTAG, T
Since it is necessary to supply a series of meaningful input patterns to the MS, it is not possible to operate the JTAG circuit simply by supplying signals having different frequencies from an external signal supply source as in the related art. there were.

The present invention has been made in order to solve the above problems.
It is an object of the present invention to provide a semiconductor integrated circuit capable of increasing a toggle ratio of an internal circuit without increasing a manufacturing cost and easily improving stress coverage, and a test method thereof.

[0015]

In order to achieve the above object, a method for testing a semiconductor integrated circuit according to the present invention comprises an RO
A first step of performing a burn-in test by operating a microcomputer by executing a program stored in M, and a second step of performing a burn-in test using a scan executed by a scan chain using scan cells, By switching between the first step and the second step, the first step is performed in one burn-in test.
Characterized in that both the step (a) and the second step are performed.

With this configuration, all the registers that can be set by software can be set in the first step, and the values of other registers are set at random by executing the scan in the second step. Therefore, there is no register leaking from the test object, and a high toggle rate can be secured in the burn-in test.

Further, in the method for testing a semiconductor integrated circuit according to the present invention, it is preferable that switching between the first step and the second step is performed by an external signal. further,
Switching between the first step and the second step is performed by using a ROM
It is also preferable to carry out by a program stored in the.

Next, in order to achieve the above object, a semiconductor integrated circuit according to the present invention comprises a ROM for storing a program.
An execution unit for executing a program stored in a ROM, a plurality of scan blocks to be scanned, a scan execution unit for scanning a scan block using a scan chain by scan cells, an execution unit, and a scan A control unit for switching the execution unit, wherein the control unit executes both the execution unit and the scan execution unit in one burn-in test.

With this configuration, all registers that can be set by software can be set in the execution unit, and values of other registers are set at random by executing the scan in the scan execution unit. Therefore, there is no register leaking from the test object, and a high toggle rate can be secured in the burn-in test.

Further, a semiconductor integrated circuit according to the present invention comprises:
It is preferable that the control unit switches between the execution unit and the scan execution unit in accordance with an external signal. Furthermore, it is preferable that the control unit includes a control register accessible by software, and the program stored in the ROM accesses the control register to switch between the execution unit and the scan execution unit.

Next, in order to achieve the above object, a semiconductor integrated circuit according to the present invention comprises a ROM for storing a program.
A JTAG circuit including: an execution unit that executes a program stored in a ROM; a JTAG boundary scan register to be scanned; and a JTAG control unit that performs a state transition of the JTAG boundary scan register. JTAG control signal supply means for generating and supplying necessary control signals.

With this configuration, it is not necessary to individually supply a signal to the JTAG dedicated terminal, so that it is not necessary to newly add a signal source, and it is possible to prevent an increase in manufacturing cost.

Further, a semiconductor integrated circuit according to the present invention comprises:
It is preferable that the JTAG control signal supply means generates a control signal according to an external signal and supplies the control signal to the JTAG circuit. Further, in the JTAG control signal supply means, a control register accessible by software is provided.
It is preferable that a program stored in M accesses the control register to generate a control signal and supply it to the JTAG circuit.

[0024]

Embodiment 1 Hereinafter, a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows Embodiment 1 of the present invention.
1 is a configuration diagram of a semiconductor integrated circuit according to the first embodiment.

In FIG. 1, reference numeral 101 denotes a ROM built in the microcomputer, 102 denotes an operation unit that operates according to a program stored in the ROM 101, and 103 denotes a mode signal control unit. Reference numeral 104 denotes a mode setting signal,
Reference numeral 110 denotes a mode switching signal, 100 denotes a scan operation control signal, 105 denotes a mode control signal, 106 denotes a scan mode signal indicating whether or not a scan mode is set, and 107 denotes a shift which controls a scan mode shift operation and a capture operation. / Capture control signals are shown.

In mode signal control section 103, mode control signal 105 is generated from mode setting signal 104, and scan mode signal 106 and shift / capture control signal 107 are generated from mode switching signal 110 and scan operation control signal 100, respectively. Will be.

Reference numerals 108 and 109 denote inputs and outputs, and reference numeral 1 denotes a semiconductor integrated circuit comprising a ROM 101, an operation unit 102, and a mode signal control unit 103. The operation unit 102 corresponds to an execution unit, and the mode control unit 103 corresponds to a control unit.

FIG. 2 is a partial configuration diagram of the operation unit 102 in the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 2, 201 to 206 denote scan cells, 209 to 211 denote FFs, 207, 208, and 2
Reference numeral 12 denotes a logic circuit. Reference numeral 213 denotes a register A, which includes scan cells 201 to 203. Similarly, reference numeral 214 denotes a register B,
FFs 209 to 211 are configured.

The scan cells 201 to 206 and the logic circuit 207 constitute a scan block 215.
The FFs 209 to 211 and the logic circuits 208 and 212 constitute a non-scan block 216. The registers A and B are registers that can be accessed using a program, for example, data registers in a microcomputer.

Reference numeral 217 denotes a scan-in signal;
Reference numeral 8 denotes a scan-out signal. Although not shown in FIG. 2, the scan-in signal 218
Are connected to a scan-out signal of another part in the operation unit 102, and the scan-out signal 218 is connected to a scan-in signal of another part in the operation unit 102, respectively.

The operation of the semiconductor integrated circuit configured as described above will be described with reference to FIGS. FIG. 3 is a timing chart showing an operation at the time of a burn-in test in the semiconductor integrated circuit according to the first embodiment of the present invention.

In FIG. 3, F201 to F206 represent the values of the scan cells 201 to 206 at that time by F2
09 to F211 are FFs 209 to 211 at that time
Are shown.

During the burn-in test, the mode setting signal 1
04 notifies the mode signal control unit 103 of the burn-in test mode. 3, at time T0 to Tn, the mode switching signal 110 shown in FIG. 1 is in an inactive state, and in this period, the mode signal control unit 103 sends the mode control signal 105 indicating the burn-in test mode to the operation unit 102. At the same time as outputting, the scan mode signal 106 is deactivated.

The scan operation control signal 100 is 2
Shifting and capturing are repeated every cycle, but since the mode switching signal 110 is in an inactive state, the shift / capture control signal 107 is output to indicate a capture operation. In addition, the operation unit 102
Receiving a mode control signal 105, a scan mode signal 106 and a shift / capture control signal 107,
The program stored in 101 is executed.

Here, since the scan mode signal 106 is inactive, the scan cells 201 to 201 in FIG.
203 and 205 to 207 operate in the same manner as a normal FF, and at time Tl, the value ABC is written to the register A213 by the program. Therefore, the values of the scan cells 201 to 203 are A, B, and C, respectively.

As a result, in scan cells 204 to 206 at time Tl + 1, X1, X2, and X3 are stored as outputs of logic circuit 204 to which the values of scan cells 201 to 203 at time Tl are input.

Further, at time Tm, the value DEF is written to the register B214 by the program. Therefore, the values of the scan cells 201 to 203 are D,
E and F. The period from time T0 to Tn corresponds to the first step in the present invention.

After time Tn + 1, the mode switching signal 1
10 is activated. As a result, the scan mode signal 106 output from the mode signal control unit 103 is also activated, and the shift / capture control signal 107 repeats the shift and capture every two cycles as in the scan operation control signal 100.

At time Tn + 2, the scan-in signal 21
7 is input and the value is shifted and stored in a scan chain composed of scan cells 201 to 206 using the scan-out signal 218 as an output.
The values of 01 to 206 are S1, A, B, C, X1,
X2. X4, X5, and X6 are output to the FFs 209 to 211 as outputs of the logic circuit 204 to which the values of the scan cells 201 to 203 at the time Tn + 1 are input, respectively.
Is stored.

At time Tn + 3, scan-in signal 21
7 are input and the values are shifted and stored in a scan chain composed of scan cells 201 to 206 using the scan-out signal 218 as an output, so that the values of the scan cells 201 to 206 are S2, S1, A, B,
C and X1. The time Tn +
The values of X7 and X are output from the logic circuit 204 to which the values of the scan cells 201 to 203 in FIG.
8, X9 are stored.

At time Tn + 4, since the shift / capture control signal 107 at time Tn + 3 indicates capture, the values of Y1, Y2, and Y3 are input and stored in the scan cells 201 to 203 from the data input side.
The scan cells 204 to 206 have a time Tn + 3.
, Y4, Y5, and Y6 as outputs of the logic circuit 204 having the values of the scan cells 201 to 203 as inputs.
Will be stored. The FFs 209 to 211 receive X1 as outputs of the logic circuit 208 to which the values of the scan cells 204 to 206 at the time Tn + 3 are input, respectively.
0, X11 and X12 are stored. The period after time Tn + 1 corresponds to the second step.

The values A, B, C,
D, E, F, X1 to X12, Y1 to Y6, S1 to S2
Represents '1' or '0', respectively.

That is, in the burn-in test by the program, it is easy to increase the toggle rate in consideration of the circuit characteristics, but it is difficult to set the value of the FF in the non-scan block. On the other hand, the burn-in test by the scan operation has a high randomness, so that it can complement the stress coverage of the burn-in test by the program, but has a characteristic that it is difficult to set the value of the scan cell inside the scan block. Therefore, by performing both burn-in tests in chronological order and by adding a small amount of hardware resources, the characteristics of both are complemented with each other.

As described above, according to the first embodiment, by providing the mode switching signal 110 and the mode signal control unit 103, the burn-in test using the scan and the burn-in test using the scan can be switched and executed. Since it becomes possible, it is possible to set the values of the FFs 209 to 211 in the non-scan block 216, which is difficult to set only by the burn-in test using scan, and to set the toggle rate in consideration of the circuit characteristics of the logic circuit 212 Can be set to increase the register B214. Similarly, considering the circuit characteristics of the logic circuit 207,
The register A213 can be set so as to increase the toggle rate.

The scan block 215 which is difficult to set only by the burn-in test by executing the program
Since it is easy to set the values of the internal scan cells 204 to 207, as a result, the logic circuits 207 and
08 and 212 can be increased.

Embodiment 2 Hereinafter, a semiconductor integrated circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a configuration diagram of the semiconductor integrated circuit according to the second embodiment of the present invention.

In FIG. 4, reference numeral 401 denotes a mode switching register, 402 denotes a mode switching signal, and 403 denotes a bus. Mode switching register 401
Is written from the operation unit 102 via the bus 403, and outputs the mode switching signal 402. The mode switching register 401 receives the scan mode signal 106 as an input, and stores the value of the bus 403 internally only when the scan mode signal 106 is in an inactive state. Other components in FIG. 4 are as described in the description of the first embodiment. In FIG. 4, the mode switching register 401 and the mode signal control unit 103 correspond to control means.

The operation of the semiconductor integrated circuit according to the second embodiment configured as described above will be described with reference to FIGS. In the first embodiment, the mode switching signal 110 is supplied from outside the semiconductor integrated circuit 1, but in the second embodiment, the mode switching signal
02 is supplied from the mode switching register 401.

That is, when writing from the operation unit 102 is not performed, the mode switching register 401 outputs a mode switching signal 402 for inactivating the state. Executes the program in the ROM 101. This operation is shown in FIG.
Corresponds to the operation from time T0 to Tn-1.

Next, the operation unit 102 sets the mode switching signal 402 to an activated state according to a program.
Data is output to the mode switching register 401 via the bus 403. At this time, since the scan mode signal 106 is in the inactive state, the mode switching register 401
Stores the data on the bus 403 and outputs the mode switching signal 4
02 is activated.

When the scan mode signal 106 is in the activated state, the mode switching register 401
03 is not stored, and the value in the register is retained. In FIG. 3, time Tn corresponds to this operation.
Similarly to the above, at time Tn + 1, the mode switching signal 112 is activated. The operation after Tn + 1 is as shown in FIG.

As described above, according to the second embodiment,
By providing a mode switching register 401 that can be accessed by the operating unit 102 via the bus 403 instead of the mode switching signal 110 in the first embodiment, switching between a burn-in test by executing a program and a burn-in test using scanning can be performed from a program. Control can be performed, switching timing can be set more flexibly than when switching is performed by an external signal, and terminal settings required during a burn-in test can be reduced.

When the scan mode signal 106 is activated, the mode switching register 401 retains the value of the scan mode signal 106. Therefore, when the burn-in test using the scan is performed, the mode switching register 401 is inadvertently switched to the burn-in test by executing the program. It is possible to prevent that.

Third Embodiment Hereinafter, a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a configuration diagram of the semiconductor integrated circuit according to the third embodiment of the present invention.

In FIG. 5, reference numeral 500 denotes a microcomputer unit;
01 denotes a JTAG boundary scan register in which each scan output is connected to an adjacent scan input;
Reference numeral 2 denotes a JTAG control unit. Also, 5
03 is a boundary clock which is a clock of the JTAG boundary scan register 501, and 504 is the first J clock.
Boundary input data input to the scan-in input of the TAG boundary scan register are respectively shown, and both are output from the JTAG control unit 502.

JTAG boundary scan register 50
1, the output is connected to the input terminal of the microcomputer unit 500, and the input is connected to the output terminal of the microcomputer unit 500, respectively.
The final scan output of the JTAG boundary scan register is connected to the JTAG control unit 502.

Reference numeral 505 denotes the JTAG terminal T described above.
JTAG external input consisting of CK, TRST, TMS, and TDI; 506, a JTAG control signal generator; 507, a JTAG enable signal; 508, a selection signal;
Reference numeral 9 denotes a selector.

The JTAG control signal generation unit 506 outputs
According to the value of the G enable signal 507, the selection signal 50
8. The selector 509 outputs the internally generated signals iTCK, iTRST, and iTMS, and the selector 509 outputs the TCK, TCK of the internally generated signals and the JTAG external input 505 according to the selection signal 508.
Signals corresponding to sTCK, sTRST, and sTMS are selected from RST and TMS and output to the JTAG control unit 502.

Reference numerals 108 and 109 denote input / output,
Microcomputer section 500, JTAG boundary scan register 501, JTAG control signal generation section 506, selector 5
09, the JTAG controller 502 constitutes the semiconductor integrated circuit 3. The JTAG boundary scan register 50
1 and the JTAG control unit 502 correspond to the JTAG circuit,
The TAG control signal generation unit 506 and the selector 509 are JTA
It corresponds to G control signal supply means.

The operation of the semiconductor integrated circuit configured as described above according to the third embodiment will be described with reference to FIGS.

FIG. 6 is a timing chart showing an operation at the time of a burn-in test in the semiconductor integrated circuit according to the third embodiment of the present invention. In FIG. 6, ST indicates the internal state of JTAG.

At the time of the burn-in test, the JTAG enable signal 507 is in the inactive state at time T0, so that the selection signal 508 output from the JTAG control signal generation unit 506 includes the internally generated signals iTCK, iTRST, iTMS.
Is not selected, and the selector 509 outputs the JTAG external input 505
Of TCK, TRST, and TMS, sTCK,
Select as sTRST, sTMS. At this time, TCK and TRST are Low and TMS is High.

At time T1, JTAG enable signal 507 is activated, so that JTAG control signal generator 506 causes internally generated signals iTCK, iTRS to be generated.
T, iTMS, and these internally generated signals
A selection signal 508 indicating selection as K, sTRST, and sTMS is output. Then, the selector 509 selects the internally generated signals iTCK, iTRST, and iTMS and outputs them to the JTAG control unit 502.

The JTAG control unit 503 includes sTCK, sT
The JTAG boundary scan register 501 is controlled by performing a state transition defined in IEEE1149.1 according to RST and sTMS. Hereafter, J
The TAG control unit 503 and the JTAG boundary scan register 501 are collectively called a JTAG circuit.

The clock supplied to the microcomputer is selected as iTCK. And JTA
Since the G control signal generation unit 506 sets iTRST to Low, the internal state ST of the JTAG control unit 502 is Test-
Logic-Reset, and the JTAG circuit has been initialized.

At time T2, JTAG control signal generating section 506 sets iTRST to high, but iTRST
Since the MS is also set to High, the internal state ST of the JTAG circuit remains at Test-logic-Reset.

At time T3, since JTAG control signal generating section 506 sets iTMS to Low,
The internal state ST of the G circuit transits to Run-Test-Idle, and a SAMPLE / PRELOAD instruction is set as an execution instruction. Note that in IEEE1149.1, the SAMPLE / PRELOAD instruction causes the JT
The AG performs an operation of storing the value of the input / output terminal of the microcomputer in the boundary scan register in the Capture-DR state.

At time T4, JTAG control signal generating section 506 sets iTRST to High, the internal state ST of the JTAG circuit transits to Select-DR-Scan, and the chain by JTAG boundary scan register 501 is moved between TDI and TDO. Is set.

At time T5, JTAG control signal generating section 506 sets iTRST to Low, so that JTAG
The internal state ST of the circuit transits to Capture-DR,
The value of the input / output terminal of the microcomputer unit 500 is taken into the JTAG boundary scan register 501.

At time T6, since the JTAG control signal generation unit 506 keeps iTRST at Low, the internal state ST of the JTAG circuit transits to Shift-DR, and JTAG with TDI input and TDO output. The value of the cell in the boundary scan register 501 is shifted to the next cell.

After time T6, the internal state ST of the JTAG circuit holds Shift-DR.
The values of the cells of the AG boundary scan register 501 are sequentially shifted.

As described above, according to the third embodiment, the JT
An AG control signal generator 506 and a selector 509 are provided.
By controlling the JTAG control signal generation unit 506 with the TAG enable signal 507, the JTAG control signal generation unit 506 does not need to individually supply a signal to the JTAG dedicated terminal during the burn-in test.
The G circuit can be operated.

Embodiment 4 Hereinafter, a semiconductor integrated circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

In FIG. 7, reference numeral 701 denotes a JTAG enable control register, 702 denotes a JTAG enable signal, and 703 denotes a bus. And J
The TAG enable control register 701 includes the operation unit 102
Is written via the bus 703 from the
An enable signal 702 is output. Other components in FIG. 7 are as described in the description of FIG. ROM10
1, operation unit 102, JTAG enable control register 7
01, the JTAG control signal generation unit 506
0, the microcomputer 700, the JTAG boundary scan register 501, the JTAG controller 506, the selector 509, and the inputs / outputs 108 and 109 constitute the semiconductor integrated circuit 4. The JTAG enable control register 70
1, the JTAG control signal generator 506 and the selector 509 correspond to a JTAG control signal supply unit.

The operation of the semiconductor integrated circuit according to the fourth embodiment configured as described above will be described with reference to FIGS. 7 and 6. In the third embodiment, the JTAG enable signal 507 is supplied from outside the semiconductor integrated circuit 3, but in the fourth embodiment, the JTAG enable signal 702 is supplied from the JTAG enable control register 701. Is different.

That is, when writing from the operation unit 102 is not performed, the JTAG enable control register 70
1 is a deactivated JTAG enable signal 702
Is output. The operation unit 102 sets the JTAG enable control register 701 via the bus 703 to activate the JTAG enable signal 702 in accordance with the program in the ROM 101. The JTAG enable control register 701 activates J by this setting.
A TAG enable signal 702 is output. In FIG. 6, time T0 corresponds to this operation, and as in FIG.
1, the JTAG enable signal 702 is activated. The operation after time T1 is as shown in FIG.

As described above, according to the fourth embodiment,
By providing the JTAG enable control register 701 accessible by the operation unit 102 via the bus 703 instead of the JTAG enable signal 507 in the third embodiment, it becomes possible to control the start of the operation of the JTAG by a program. In addition, the JTAG circuit can be operated according to the terminal state of the microcomputer unit 700, and the necessary terminal settings at the time of burn-in can be reduced.

As described above, the embodiments of the present invention are described separately from the first to fourth embodiments. However, the first and second embodiments are either the third embodiment or the fourth embodiment. It can be used in conjunction with Embodiment 4,
Needless to say, it is possible to provide a semiconductor integrated circuit capable of operating with higher stress coverage than using the first to fourth embodiments alone.

[0079]

As described above, according to the semiconductor integrated circuit of the present invention, the burn-in test using the program and the burn-in test using the scan are switched by the mode switching means, and the JTAG control signal generating means is provided. By using the output of the JTAG control signal generation means instead of the JTAG control signal input from the outside during the burn-in test, stress coverage can be easily improved, and the signal source supplied to the LSI terminal during the burn-in test can be improved. Since there is no need to add a new one, it is possible to reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a partial configuration diagram of an operation unit in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 3 is a timing chart illustrating an operation during a burn-in test in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 6 is a timing chart illustrating an operation during a burn-in test in the semiconductor integrated circuit according to the third embodiment of the present invention;

FIG. 7 is a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention;

[Explanation of symbols]

1, 2, 3, 4 semiconductor integrated circuit 100 scan operation control signal 101 ROM 102 operation unit 103 mode signal control unit 104 mode setting signal 105 mode control signal 106 scan mode signal 107 shift / capture control signal 108, 109 input / output 110, 402 Mode switching signal 201, 202, 203, 204, 205, 206 Scan cell 209, 210, 211 FF 207, 208, 212 Logic circuit 213 Register A 214 Register B 215 Scan block 216 Non-scan block 217 Scan-in signal 218 Scan-out Signal 401 Mode switching register 403, 703 Bus 500, 700 Microcomputer section 501 JTAG boundary scan register 502 JTAG control section 503 Boundary rewrite Click 504 boundary data input 505 JTAG external input 506 JTAG control signal generation unit 507,702 JTAG enable signal 508 selects signal 509 selector 701 JTAG enable register

Claims (9)

[Claims] 1. A first step of operating a microcomputer by executing a program stored in a ROM to perform a burn-in test, and a second step of performing a burn-in test using a scan executed by a scan chain using scan cells. And a step of switching between the first step and the second step to execute both the first step and the second step in one burn-in test. Test method. 2. The test method for a semiconductor integrated circuit according to claim 1, wherein the switching between the first step and the second step is performed by an external signal. 3. The method according to claim 1, wherein the switching between the first step and the second step is performed by a program stored in a ROM. 4. A ROM for storing a program, execution means for executing the program stored in the ROM, a plurality of scan blocks to be scanned, and the scan block using a scan chain by scan cells. And a control unit that switches between the execution unit and the scan execution unit. The control unit controls both the execution unit and the scan execution unit in one burn-in test. A semiconductor integrated circuit, which is executed. 5. The semiconductor integrated circuit according to claim 4, wherein said control unit switches between said execution unit and said scan execution unit in accordance with an external signal. 6. The control unit further comprises a control register accessible by software, and a program stored in the ROM accesses the control register to switch between the execution unit and the scan execution unit. 5. The semiconductor integrated circuit according to item 4. 7. A ROM for storing a program, execution means for executing the program stored in the ROM, a JTAG boundary scan register to be scanned, and a JTAG controller for performing a state transition of the JTAG boundary scan register. And a JTAG control signal supply means for generating and supplying a control signal required for the JTAG circuit. 8. The JTAG control signal supply means generates a control signal according to an external signal, and
8. The semiconductor integrated circuit according to claim 7, which is supplied to a circuit. 9. The JTAG control signal supply means includes a control register accessible by software, and a program stored in the ROM accesses the control register to generate a control signal to generate the JTAG control signal.
8. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is supplied to a TAG circuit.