JPH08153753A - Semiconductor element mounting method - Google Patents

Semiconductor element mounting method

Info

Publication number
JPH08153753A
JPH08153753A JP29302594A JP29302594A JPH08153753A JP H08153753 A JPH08153753 A JP H08153753A JP 29302594 A JP29302594 A JP 29302594A JP 29302594 A JP29302594 A JP 29302594A JP H08153753 A JPH08153753 A JP H08153753A
Authority
JP
Japan
Prior art keywords
semiconductor element
terminal portion
substrate
electric wiring
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29302594A
Other languages
Japanese (ja)
Inventor
Kenichi Komurasaki
賢一 小紫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP29302594A priority Critical patent/JPH08153753A/en
Publication of JPH08153753A publication Critical patent/JPH08153753A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To enable positioning of a semiconductor element to connecting terminals of an electric interconnection on a mounting substrate easily and surely, even using opaque material for the terminals. CONSTITUTION: Gold bumps 3 are formed on input/output terminals 2 of a semiconductor element 1 and contacted with connecting terminals 5 of an electric interconnection 6 on a mounting substrate 8. In this condition, the element 1 is secured to the substrate 8 with a resin 9. A positioning identification means 4 is formed on the back side of the element 1 and the positioning is made by seeing the means 4 through a light permeable window 7 on the substrate 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子の実装方法に
関し、特にFDB(Face Down Bonding) 法による半導体
素子の実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting method, and more particularly to a semiconductor element mounting method by an FDB (Face Down Bonding) method.

【0002】[0002]

【従来の技術】従来、半導体素子をFDB法によって被
着基板上に実装する場合、図3に示すように、半導体素
子1の入出力端子部2に金バンプ3を設け、この金バン
プ3を被着基板8上に形成した電気配線6に連続して形
成した接続端子部5に当接させ、この半導体素子1を被
着基板8上に光硬化型樹脂9などで固着することにより
実装していた。この場合、被着基板8上の接続端子部5
を形成する材料としては、電気絶縁膜となる表面酸化膜
などを生じない材料で形成する必要があり、一般的には
ITO(Indium Tin Oxide)や金などが用いられる。
2. Description of the Related Art Conventionally, when a semiconductor element is mounted on an adherend substrate by the FDB method, a gold bump 3 is provided on the input / output terminal portion 2 of the semiconductor element 1 as shown in FIG. The semiconductor device 1 is mounted by being brought into contact with the connection terminal portion 5 formed continuously with the electric wiring 6 formed on the adherend substrate 8 and fixing the semiconductor element 1 on the adherend substrate 8 with a photocurable resin 9 or the like. Was there. In this case, the connection terminal portion 5 on the adherend substrate 8
It is necessary to form a material that does not form a surface oxide film that becomes an electric insulating film, and ITO (Indium Tin Oxide) or gold is generally used.

【0003】[0003]

【発明が解決しようとする問題点】ところが、接続端子
部5の材料としてITOを用いると、ITOはそれ自体
の電気抵抗が大きく、また半導体素子1の金バンプ3と
接続端子部5との接続抵抗が大きくなり、その接続抵抗
のバラツキも生じるという問題がある。
However, when ITO is used as the material of the connection terminal portion 5, ITO has a large electric resistance of itself, and the connection between the gold bump 3 of the semiconductor element 1 and the connection terminal portion 5 is large. There is a problem that the resistance becomes large and the connection resistance also varies.

【0004】そこで、このような問題を回避するため
に、図4に示すように、ITO10の下地層としてクロ
ムなどの金属層11を設けて、接続端子部5を形成する
という方法が取られていた。
Therefore, in order to avoid such a problem, as shown in FIG. 4, a method of forming a connection terminal portion 5 by providing a metal layer 11 of chromium or the like as a base layer of the ITO 10 is adopted. It was

【0005】一方、反射型の液晶ディスプレイなどのよ
うに絵素電極の形成時にITO膜の成膜工程が必要ない
場合などは、接続端子部5を形成する材料として金が用
いられることもある。
On the other hand, gold may be used as the material for forming the connection terminal portion 5 when the film formation process of the ITO film is not required when forming the pixel electrodes, such as in a reflective liquid crystal display.

【0006】ところが、接続端子部5を形成する材料と
して不透明な金属を用いると、図5に示すように、光が
遮られて被着基板8の裏面側から、半導体素子1の金バ
ンプ3を視認できず、被着基板8と半導体素子1の正確
な位置合わせが困難になるという問題がある。
However, when an opaque metal is used as the material for forming the connection terminal portion 5, as shown in FIG. 5, light is blocked and the gold bumps 3 of the semiconductor element 1 are removed from the rear surface side of the adherend substrate 8. There is a problem that the substrate 8 to be adhered and the semiconductor element 1 are difficult to be accurately aligned because they cannot be visually recognized.

【0007】[0007]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、このような従来技術の問題点に鑑みて成
されたものであり、その特徴とするところは、半導体素
子の入出力端子部に金属突起を設け、この金属突起を被
着基板上の電気配線に連続して形成した接続端子部に当
接させて前記半導体素子を前記被着基板上に樹脂で固着
する半導体素子の実装方法において、前記被着基板上の
電気配線と接続端子部を不透明な導電材料で形成し、こ
の接続端子部近傍の前記電気配線に光透過窓を設け、前
記半導体素子の前記光透過窓と対峙する部分に識別手段
を設けた点にある。
The method of manufacturing a semiconductor device according to the present invention has been made in view of the above problems of the prior art, and is characterized in that the input / output of a semiconductor element is performed. A metal element is provided on the terminal substrate, and the metal element is abutted on a connection terminal portion formed continuously with the electric wiring on the adherend substrate to fix the semiconductor element on the adherend substrate with resin. In the mounting method, the electric wiring and the connection terminal portion on the adherend substrate are formed of an opaque conductive material, a light transmission window is provided in the electric wiring in the vicinity of the connection terminal portion, and the light transmission window of the semiconductor element is provided. The point is that identification means is provided in the facing portion.

【0008】[0008]

【作用】上記のように構成することにより、接続端子部
に不透明な金属を用いても、半導体素子の位置合わせが
容易にできる。
With the above-mentioned structure, even if an opaque metal is used for the connection terminal portion, the semiconductor element can be easily aligned.

【0009】[0009]

【実施例】以下、本発明の実施例を添付図面に基づき詳
細に説明する。なお、従来例と同一箇所には同一符号を
付して説明する。図1は本発明に係る半導体素子の実装
方法の一実施例を示す断面図であり、1は半導体素子、
8はガラスなどの透光部材から成る被着基板、9は半導
体素子1を被着基板8上に固着するための樹脂である。
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The same parts as in the conventional example will be described with the same reference numerals. FIG. 1 is a sectional view showing an embodiment of a semiconductor element mounting method according to the present invention, in which 1 is a semiconductor element,
Denoted at 8 is an adherend substrate made of a translucent member such as glass, and 9 is a resin for fixing the semiconductor element 1 onto the adherend substrate 8.

【0010】半導体素子1の裏面側には、入出力端子部
2が複数箇所設けられており、この入出力端子部2には
金(Au)などから成る金属突起(金バンプ)3がそれ
ぞれ設けられている。
A plurality of input / output terminal portions 2 are provided on the back surface side of the semiconductor element 1, and metal projections (gold bumps) 3 made of gold (Au) or the like are provided on the input / output terminal portions 2, respectively. Has been.

【0011】被着基板8上には、金(Au)、アルミニ
ウム(Al)、ニッケル(Ni)、クロム(Cr)、チ
タン(Ti)などの不透明な導電材料から成る電気配線
6が形成されている。この電気配線6は、スパッタリン
グ法や蒸着法などで形成される。この電気配線6の先端
部には金(Au)などの酸化されにくい金属層から成る
接続端子部5が設けられている。
An electric wiring 6 made of an opaque conductive material such as gold (Au), aluminum (Al), nickel (Ni), chromium (Cr) or titanium (Ti) is formed on the adhered substrate 8. There is. The electric wiring 6 is formed by a sputtering method, a vapor deposition method, or the like. A connection terminal portion 5 made of a metal layer such as gold (Au) that is not easily oxidized is provided at the tip of the electric wiring 6.

【0012】電気配線6の先端部近傍には、光透過窓7
がそれぞれ設けられている。この光透過窓7は、例えば
電気配線6をフォトリソグラフィなどによってパターニ
ングする際に同時に形成すればよい。
A light transmitting window 7 is provided near the tip of the electric wiring 6.
Are provided respectively. The light transmitting window 7 may be formed at the same time when the electric wiring 6 is patterned by photolithography or the like.

【0013】半導体素子1の光透過窓7と対峙する部分
には、識別手段4が設けられている。このように光透過
窓7と対峙する入出力端子部2に識別手段4を設けると
電気配線6や金属層5を不透明な導電材料で形成して
も、被着基板8の裏面側からこの識別手段4を基準に半
導体素子1を正確に位置合わせすることができる。
An identification means 4 is provided in a portion of the semiconductor element 1 facing the light transmission window 7. When the identification means 4 is provided in the input / output terminal portion 2 facing the light transmission window 7 as described above, even if the electrical wiring 6 and the metal layer 5 are formed of an opaque conductive material, the identification is performed from the back surface side of the adherend substrate 8. The semiconductor element 1 can be accurately aligned with the means 4 as a reference.

【0014】この識別手段4は、例えば半導体素子1の
光透過窓7と対峙する部分が入出力端子部2である場
合、金属突起とすることができる。識別手段4を金属突
起にすれば、半導体素子1を接続するための金属突起3
と同一工程で形成できる点で望ましいが、金属突起に限
らず、有色樹脂などを塗布したものであってもよい。
The identification means 4 may be a metal projection when the portion of the semiconductor element 1 facing the light transmission window 7 is the input / output terminal portion 2, for example. If the identification means 4 is a metal protrusion 3, the metal protrusion 3 for connecting the semiconductor element 1 is connected.
Although it is desirable in that it can be formed in the same step as above, it is not limited to metal protrusions, and colored resin or the like may be applied.

【0015】また、この光透過窓7と識別手段4は正確
な位置合わせを行うためには、複数箇所設けることが望
ましい。
Further, it is desirable that the light transmitting window 7 and the identifying means 4 are provided at a plurality of positions in order to perform accurate alignment.

【0016】半導体素子1を被着基板8に固着する場
合、フェノール樹脂やエポキシ樹脂などから成る光また
は熱硬化型樹脂9を被着基板1の所定箇所に塗布して、
半導体素子1の入出力端子部2の金属突起3を被着基板
8の金属層5に当接させて、被着基板8の裏面側から識
別手段4を基準に位置合わせして、樹脂9を熱または光
で硬化させることによって、金属突起3が出力端子部の
金属5に当接した状態で固着する。
When the semiconductor element 1 is fixed to the substrate 8 to be adhered, a light or thermosetting resin 9 made of a phenol resin, an epoxy resin or the like is applied to predetermined portions of the substrate 1 to be adhered,
The metal protrusion 3 of the input / output terminal portion 2 of the semiconductor element 1 is brought into contact with the metal layer 5 of the adherend substrate 8, and the resin 9 is aligned from the rear surface side of the adherend substrate 8 with the identifying means 4 as a reference. By curing with heat or light, the metal protrusions 3 are fixed in contact with the metal 5 of the output terminal portion.

【0017】図2は、接続端子部を被着基板8の裏面側
から見た図である。不透明な導電材料から成る電気配線
6に矩形上の光透過窓7が形成され、この光透過窓7を
介して識別手段4が視認できる。なお、電気配線6は不
透明な導電材料で形成されることから、半導体素子1と
電気配線6を接続する金属突起3は被着基板1の裏面側
からは視認できない。
FIG. 2 is a view of the connection terminal portion viewed from the back surface side of the adherend substrate 8. A rectangular light transmission window 7 is formed in the electric wiring 6 made of an opaque conductive material, and the identification means 4 can be visually recognized through the light transmission window 7. Since the electric wiring 6 is formed of an opaque conductive material, the metal protrusions 3 connecting the semiconductor element 1 and the electric wiring 6 cannot be visually recognized from the back surface side of the adherend substrate 1.

【0018】また上記発明では不透明な電気配線6のみ
に、光透過窓7を形成したが、出力端子部5を広面積に
形成して、この出力端子部5と電気配線6の双方に光透
過窓7を形成してもよい。これが請求項4に記載した発
明であり、請求項1に記載した発明と全く同一の効果を
奏することができる。
Further, in the above invention, the light transmission window 7 is formed only in the opaque electric wiring 6, but the output terminal portion 5 is formed in a large area and the light transmission is carried out to both the output terminal portion 5 and the electric wiring 6. The window 7 may be formed. This is the invention described in claim 4, and the same effect as the invention described in claim 1 can be obtained.

【0019】[0019]

【発明の効果】以上のように、本発明に係る半導体装置
の製造方法によれば、被着基板上の電気配線と接続端子
部を不透明な導電材料で形成し、この接続端子部近傍の
前記電気配線に光透過窓を設け、前記半導体素子の前記
光透過窓と対峙する部分に識別手段を設けたことから、
接続端子部に不透明な材料を用いても、接続端子部と半
導体素子との位置合わせを容易且つ確実に行うことがで
きる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the electric wiring and the connection terminal portion on the substrate to be adhered are formed of an opaque conductive material, and the vicinity of the connection terminal portion is formed. Since a light transmission window is provided in the electric wiring, and the identification means is provided in a portion facing the light transmission window of the semiconductor element,
Even if an opaque material is used for the connection terminal portion, the connection terminal portion and the semiconductor element can be easily and reliably aligned with each other.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体素子の実装方法の一実施例
を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element mounting method according to the present invention.

【図2】本発明に係る半導体素子の実装方法において、
半導体素子の固着部を被着基板の裏面側から見た図であ
る。
FIG. 2 shows a method of mounting a semiconductor device according to the present invention,
It is the figure which looked at the adhesion part of a semiconductor element from the back side of a to-be-adhered substrate.

【図3】従来の半導体素子の実装方法を示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a conventional semiconductor element mounting method.

【図4】従来の半導体素子の実装方法に用いられる接続
端子部を示す図である。
FIG. 4 is a diagram showing a connection terminal portion used in a conventional semiconductor element mounting method.

【図5】従来の半導体素子の実装方法において、半導体
素子の固着部を被着基板の裏面側から見た図である。
FIG. 5 is a view of a fixing portion of a semiconductor element as seen from the back surface side of a substrate to which the semiconductor element is mounted in a conventional semiconductor element mounting method.

【符号の説明】[Explanation of symbols]

1・・・半導体素子、2・・入出力端子部、3・・・接
続用バンプ、4・・・位置合わせ用バンプ、 5・・・
接続端子部、6・・・電気配線、7・・・光透過窓、8
・・・被着基板、9・・・樹脂
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... I / O terminal part, 3 ... Connection bump, 4 ... Positioning bump, 5 ...
Connection terminal part, 6 ... Electric wiring, 7 ... Light transmitting window, 8
... Substrate, 9 ... Resin

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の入出力端子部に金属突起を
設け、この金属突起を被着基板上の電気配線に連続して
形成した接続端子部に当接させて前記半導体素子を前記
被着基板上に樹脂で固着する半導体素子の実装方法にお
いて、前記被着基板上の電気配線と接続端子部を不透明
な導電材料で形成し、この接続端子部近傍の前記電気配
線に光透過窓を設け、前記半導体素子の前記光透過窓と
対峙する部分に識別手段を設けたことを特徴とする半導
体素子の実装方法。
1. An input / output terminal portion of a semiconductor element is provided with a metal protrusion, and the metal protrusion is brought into contact with a connection terminal portion formed continuously with an electric wiring on a substrate to be adhered to attach the semiconductor element to the adherend. In a method of mounting a semiconductor element fixed on a substrate with a resin, an electric wiring and a connecting terminal portion on the adherend substrate are formed of an opaque conductive material, and a light transmitting window is provided in the electric wiring near the connecting terminal portion. A mounting method for a semiconductor element, characterized in that identification means is provided in a portion of the semiconductor element facing the light transmission window.
【請求項2】 前記光透過窓と識別手段を2箇所以上設
けることを特徴とする請求項1に記載の半導体素子の実
装方法。
2. The method of mounting a semiconductor element according to claim 1, wherein the light transmission window and the identification means are provided at two or more places.
【請求項3】 前記半導体素子の前記光透過窓と対峙す
る部分が前記半導体素子の入出力端子部であり、前記識
別手段が金属突起であることを特徴とする請求項1また
は2に記載の半導体素子の実装方法。
3. The semiconductor device according to claim 1, wherein a portion of the semiconductor element facing the light transmission window is an input / output terminal portion of the semiconductor element, and the identifying means is a metal protrusion. Semiconductor device mounting method.
【請求項4】 半導体素子の入出力端子部に金属突起を
設け、この金属突起を被着基板上の電気配線に連続して
形成した接続端子部に当接させて前記半導体素子を前記
被着基板上に樹脂で固着する半導体素子の実装方法にお
いて、前記被着基板上の電気配線と接続端子部を不透明
な導電材料で形成し、この接続端子部と前記電気配線に
光透過窓を設け、前記半導体素子の前記光透過窓と対峙
する部分に識別手段を設けたことを特徴とする半導体素
子の実装方法。
4. A semiconductor element is attached to the semiconductor element by providing a metal projection on an input / output terminal section of the semiconductor element, and abutting the metal projection on a connection terminal section formed continuously with an electric wiring on the adhesion substrate. In a method of mounting a semiconductor element fixed on a substrate with a resin, an electric wiring and a connection terminal portion on the adherend substrate are formed of an opaque conductive material, and a light transmission window is provided in the connection terminal portion and the electric wiring, A method of mounting a semiconductor element, wherein an identification means is provided in a portion of the semiconductor element facing the light transmission window.
JP29302594A 1994-11-28 1994-11-28 Semiconductor element mounting method Pending JPH08153753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29302594A JPH08153753A (en) 1994-11-28 1994-11-28 Semiconductor element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29302594A JPH08153753A (en) 1994-11-28 1994-11-28 Semiconductor element mounting method

Publications (1)

Publication Number Publication Date
JPH08153753A true JPH08153753A (en) 1996-06-11

Family

ID=17789517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29302594A Pending JPH08153753A (en) 1994-11-28 1994-11-28 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JPH08153753A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1126645A (en) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp Semiconductor integrated circuit device and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1126645A (en) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp Semiconductor integrated circuit device and its manufacture

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