JPH0815371B2 - Synchronous input device - Google Patents

Synchronous input device

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Publication number
JPH0815371B2
JPH0815371B2 JP61255559A JP25555986A JPH0815371B2 JP H0815371 B2 JPH0815371 B2 JP H0815371B2 JP 61255559 A JP61255559 A JP 61255559A JP 25555986 A JP25555986 A JP 25555986A JP H0815371 B2 JPH0815371 B2 JP H0815371B2
Authority
JP
Japan
Prior art keywords
circuit
detection circuit
difference detection
voltage
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61255559A
Other languages
Japanese (ja)
Other versions
JPS63110917A (en
Inventor
昭憲 田崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61255559A priority Critical patent/JPH0815371B2/en
Publication of JPS63110917A publication Critical patent/JPS63110917A/en
Publication of JPH0815371B2 publication Critical patent/JPH0815371B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は異なる配電系統を、同期をとって自動閉合
する同期投入装置に関するものである。
Description: TECHNICAL FIELD The present invention relates to a synchronous closing device that automatically closes different power distribution systems in synchronization.

〔従来の技術〕[Conventional technology]

第3図は例えば特開昭55−109135号公報に示された従
来の同期投入装置のブロック接続図であり、図におい
て、1aは発電機17を投入・解列する発電機用遮断器、1b
は母線同志を閉合又は開路する母線用遮断器、2は電圧
・周波数検出用変圧器、18は電圧・周波数のアナログデ
ータをデイジタルに変換する回路、6はアナログ・デイ
ジタル変換回路18を通して入力されたデータを演算する
演算回路、19は演算回路6の演算結果に基づき、遮断器
1a又は1bへ入・切信号を出力する出力回路、20は母線に
接続された負荷である。
FIG. 3 is a block connection diagram of a conventional synchronous closing device disclosed in, for example, Japanese Patent Laid-Open No. 55-109135. In FIG. 3, 1a is a generator circuit breaker for closing and opening a generator 17, and 1b is a circuit breaker.
Is a circuit breaker for closing / opening the busbars, 2 is a voltage / frequency detecting transformer, 18 is a circuit for converting voltage / frequency analog data into digital, and 6 is input through an analog / digital converting circuit 18. An arithmetic circuit for arithmetically operating data, 19 is a circuit breaker based on the arithmetic result of the arithmetic circuit 6.
An output circuit for outputting an on / off signal to 1a or 1b, and 20 is a load connected to the bus bar.

第4図は、第3図の演算回路6の制御動作プログラム
のフローチャート図である。
FIG. 4 is a flow chart of the control operation program of the arithmetic circuit 6 of FIG.

次に動作について説明する。第3図において、母線用
遮断器1bを投入する場合、既に2台の発電機17が運転中
で、発電機用遮断器1aが投入済であれば同期投入が必要
となる。
Next, the operation will be described. In FIG. 3, when the busbar circuit breaker 1b is turned on, if two generators 17 are already in operation and the generator circuit breaker 1a has already been turned on, synchronous closing is required.

この場合、母線用遮断器1bの投入指令により、上記の
各発電機17の電圧・周波数及び電圧位相が変圧器2及び
アナログ・デイジタル変換回路18を経由して、演算回路
6に入力される。
In this case, the voltage / frequency and the voltage phase of each of the generators 17 are input to the arithmetic circuit 6 via the transformer 2 and the analog / digital conversion circuit 18 according to the closing command of the busbar breaker 1b.

これらの入力データを基に演算回路では、第4図のフ
ローチャート図に従ったプログラム手順で制御を実行す
る。即ち、まず、母線用遮断器1bの投入側母線の電圧確
立を確認し(ステップ4−1)、電圧が確立していれ
ば、投入側発電機の電圧・周波数を制御して、被投入側
母線のそれと合わせる(ステップ4−2)。これら電圧
・周波数の差が許容差内に入ったならば(ステップ4−
3)、両母線の電圧位相を比較し、次の同期点、即ち位
相合致点までの時間を予測し(ステップ4−4)、この
予測時間が許容値内となると(ステップ4−5)、出力
回路19を通して、母線用遮断器1bに投入信号を出力し
(ステップ4−6)、遮断器を投入する。
Based on these input data, the arithmetic circuit executes the control in the program procedure according to the flowchart of FIG. That is, first, the establishment of the voltage on the closing side busbar of the busbar circuit breaker 1b is confirmed (step 4-1), and if the voltage is established, the voltage / frequency of the closing side generator is controlled to make it the receiving side. Match it with that of the busbar (step 4-2). If these voltage / frequency differences fall within the tolerance (step 4-
3) Comparing the voltage phases of both buses, predicting the time to the next synchronization point, that is, the phase matching point (step 4-4), and when this predicted time is within the allowable value (step 4-5), Through the output circuit 19, a closing signal is output to the busbar breaker 1b (step 4-6), and the breaker is closed.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従来の同期投入装置は以上のように構成されているの
で、投入側と被投入側の電圧,周波数及び電圧位相を直
接アナログ・デイジタル変換し、演算回路で電圧差,周
波数差及び位相差を演算する方式としているため、400H
z系のように高周波電源では演算精度が落ち、同期投入
を失敗するなどの問題点があった。
Since the conventional synchronous closing device is configured as described above, the voltage, frequency and voltage phase of the input side and the input side are directly analog-digital converted, and the voltage difference, frequency difference and phase difference are calculated by the arithmetic circuit. Since it is a method to do, 400H
High-frequency power supplies such as the z system have problems such as poor accuracy in computation and failure in synchronization.

また、発電機及び系統の電源が不安定または電磁ノイ
ズ,静電ノイズなどの影響があるところでは、発電機と
系統電源の電圧差,周波数差,位相差の出力は変動し、
リップルを含んだものとなる。このため、同期投入の全
機能を演算回路のプログラムだけに依存している従来装
置では、発電機と系統電源の電圧差,周波数差,位相差
が許容値外のときに、たまたま許容値になったり、回路
の故障で許容値になると、ミス投入による重大事故が懸
念されるなど信頼性に問題点があった。
In addition, when the power source of the generator and the grid is unstable or affected by electromagnetic noise, electrostatic noise, etc., the output of the voltage difference, frequency difference, phase difference between the generator and the grid power source fluctuates,
It will include ripple. For this reason, in a conventional device in which all the functions of synchronous closing depend on only the program of the arithmetic circuit, when the voltage difference, the frequency difference, and the phase difference between the generator and the system power supply are out of the allowable values, the allowable values occur by accident. However, there is a problem in reliability, such as a serious accident due to a mistaken input when the allowable value is caused by a circuit failure.

この発明は上記のような問題点を解消するためになさ
れたもので、高周波電源に適用できるほか、非常用電源
及び連続給電を必要とする重要なプラント電源などの高
信頼度電源供給装置に適用できる同期投入装置を得るこ
とを目的とする。
The present invention has been made to solve the above problems, and can be applied to a high-frequency power supply and also to a highly reliable power supply device such as an emergency power supply and an important plant power supply that requires continuous power supply. The purpose is to obtain a synchronization insertion device that can be used.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る同期投入装置は、別個独立の電圧差検
出回路,周波数差検出回路,位相差検出回路の出力に基
づいて同期投入信号を出力する演算回路と、上記各検出
回路の出力値を許容値と比較する比較増幅回路と、この
各比較増幅回路の出力条件の論理積を得る論理積回路と
を備えたものである。
The synchronization closing device according to the present invention allows an operation circuit that outputs a synchronization closing signal based on the outputs of the voltage difference detection circuit, the frequency difference detection circuit, and the phase difference detection circuit, which are independent of each other, and the output values of the detection circuits. It is provided with a comparison amplification circuit for comparing with a value and a logical product circuit for obtaining a logical product of output conditions of the respective comparison amplification circuits.

〔作用〕[Action]

この発明における演算回路は、電圧差検出回路,周波
数差検出回路,位相差検出回路の出力に基づいて同期投
入信号を出力し、論理積回路は、上記検出回路のそれぞ
れの出力値を許容値と比較する複数の比較増幅回路の出
力条件によって上記同期投入信号を有効とするもので、
同期投入をミスなく確実に行うことができ、信頼性が向
上する。
The arithmetic circuit according to the present invention outputs a synchronization closing signal based on the outputs of the voltage difference detection circuit, the frequency difference detection circuit, and the phase difference detection circuit, and the AND circuit sets the respective output values of the detection circuit as the allowable values. The synchronization input signal is validated according to the output conditions of a plurality of comparison and amplification circuits to be compared,
The synchronization can be surely performed without any mistake, and the reliability is improved.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第
1図において、1は遮断器、2は変圧器、3は電圧差検
出回路、4は周波数差検出回路、5は位相差検出回路、
6は演算回路、7〜11は演算回路の演算結果に基づき出
力される信号で、7,8は電圧の増及び減信号、9,10は周
波数の上昇及び下降信号、11は遮断器1の投入信号、12
a〜12cは設定器、13a〜13cは電圧差検出回路3,周波数差
検出回路4,位相差検出回路5のそれぞれの出力値と設定
器12a〜12cで設定された許容値とを比較し増幅する複数
の比較増幅器、14はその各比較増幅回路13a〜13cの出力
条件を論理積する論理積回路、15は論理積回路14の出力
で駆動され、遮断器1の投入信号11を有効とする電磁継
電器、16は上記符号3〜6,12a〜12c,13a〜13c,14,15を
付した各部材で構成されたこの発明の同期投入装置であ
る。
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a circuit breaker, 2 is a transformer, 3 is a voltage difference detection circuit, 4 is a frequency difference detection circuit, 5 is a phase difference detection circuit,
6 is an arithmetic circuit, 7 to 11 are signals output based on the arithmetic result of the arithmetic circuit, 7 and 8 are voltage increase and decrease signals, 9 and 10 are frequency increase and decrease signals, and 11 is a circuit breaker 1 Input signal, 12
a to 12c are setting devices, and 13a to 13c compare and amplify the respective output values of the voltage difference detecting circuit 3, the frequency difference detecting circuit 4, and the phase difference detecting circuit 5 with the allowable values set by the setting devices 12a to 12c. A plurality of comparison amplifiers, 14 is a logical product circuit that logically ANDs the output conditions of the respective comparison amplification circuits 13a to 13c, and 15 is driven by the output of the logical product circuit 14 to make the closing signal 11 of the circuit breaker 1 valid. An electromagnetic relay, 16 is the synchronous closing device of the present invention, which is composed of each member having the above-mentioned reference numerals 3 to 6, 12a to 12c, 13a to 13c, 14 and 15.

第2図は、上記同期投入装置16内の演算回路6で実行
される制御動作プログラムフローチャート図である。
FIG. 2 is a flow chart of a control operation program executed by the arithmetic circuit 6 in the synchronization input device 16.

次に動作について説明する。両母線の電圧が確立して
いる状態で遮断器1の同期投入指令(図示しない)が入
力されると、変圧器2を通して両母線の電源が電圧差検
出回路3,周波数差検出回路4,位相差検出回路5に入力さ
れる。この各検出回路3〜5の出力は、設定器12a〜12c
で設定された許容値との判定のために、比較増幅回路13
a〜13cに入力されるとともに演算回路6にも入力され
る。
Next, the operation will be described. When the synchronous closing command (not shown) of the circuit breaker 1 is input while the voltage of both buses is established, the power sources of both buses are supplied to the voltage difference detection circuit 3, frequency difference detection circuit 4, and position through the transformer 2. It is input to the phase difference detection circuit 5. The outputs of the detection circuits 3 to 5 are setters 12a to 12c.
The comparison and amplification circuit 13 is used to judge the allowable value set in
It is input to a to 13c and also to the arithmetic circuit 6.

演算回路6では第2図の制御動作フローチャート図に
示すように、まず、電圧差,周波数差が許容値か否かを
判断し(ステップ2−1)、この判断結果がNO、つまり
許容値より大であれば、この偏差を小とするため、電圧
又は周波数の「大」側発電機には減8又は下降10信号
を、電圧又は周波数の「小」側発電機には増7又は上昇
9信号を出力する(ステップ2−2)。
As shown in the control operation flowchart of FIG. 2, the arithmetic circuit 6 first determines whether or not the voltage difference and the frequency difference are allowable values (step 2-1), and the determination result is NO, that is, the allowable value. If it is large, in order to make this deviation small, a decrease 8 or decrease 10 signal is given to the voltage or frequency “large” side generator, and an increase 7 or increase 9 is given to the voltage or frequency “small” side generator. A signal is output (step 2-2).

また、ステップ2−1の判断結果がYES、つまり偏差
が許容値内であれば、位相差検出回路5より両機の電圧
位相合致点を予測し、(ステップ2−3)、遮断器1の
動作時間を考慮してある一定時間前に投入信号11を出力
する(ステップ2−4)。
If the determination result of step 2-1 is YES, that is, if the deviation is within the allowable value, the phase difference detection circuit 5 predicts the voltage phase matching point of both units, and the operation of the circuit breaker 1 is performed (step 2-3). In consideration of time, the closing signal 11 is output a certain time before (step 2-4).

この演算回路6の動作と並行して、電圧差検出回路3
からの電圧差信号,周波数差検出回路4からの周波数差
信号,位相差検出回路5からの位相差信号は設定器12a
〜12cで設定された許容値と比較増幅回路13a〜13cで比
較され、全てが許容値内のとき、この各比較増幅回路13
a〜13cの出力条件を論理積する論理積回路14の出力で電
磁継電器15が励磁される。この電磁継電器15の接点15a
は前記演算回路6の投入信号11の出力路に直列に接続さ
れているので、この接点15aの閉路時に上記投入信号11
が出力されたときのみ該投入信号を有効なものとして遮
断器1が投入する。
In parallel with the operation of the arithmetic circuit 6, the voltage difference detection circuit 3
The voltage difference signal from the frequency difference detection circuit 4, the frequency difference signal from the frequency difference detection circuit 4, and the phase difference signal from the phase difference detection circuit 5 are set by the setter 12a.
~ 12c is compared with the allowable value set in the comparison and amplification circuit 13a ~ 13c, and when all are within the allowable value, each comparison and amplification circuit 13
The electromagnetic relay 15 is excited by the output of the AND circuit 14 that logically ANDs the output conditions of a to 13c. Contact 15a of this electromagnetic relay 15
Is connected in series to the output path of the closing signal 11 of the arithmetic circuit 6, the closing signal 11 is closed when the contact 15a is closed.
The circuit breaker 1 closes the input signal as a valid signal only when is output.

なお、上記実施例では、演算回路の制御動作の投入信
号バックアップは、電圧差,周波数差,位相差の全てが
許容値内で電磁継電器を励磁し、この接点によるインタ
ロックとしたが、これは無接点によるインタロックでも
よい。また、電圧差,周波数差,位相差の各許容値内信
号を各々有接点又は無接点信号をつくり、これらの全て
の信号と投入信号とのインタロックでも同様の効果を奏
する。
In the above embodiment, the input signal backup of the control operation of the arithmetic circuit is an interlock by this contact by exciting the electromagnetic relay within the allowable values of the voltage difference, the frequency difference, and the phase difference. A non-contact interlock may be used. Further, the same effect can be obtained even if the signals within the permissible values of the voltage difference, the frequency difference, and the phase difference are each made into a contact point signal or a non-contact point signal, and interlocking all of these signals with the closing signal.

なお、ディジタル制御系において、アナログ系(ハー
ドウエアによるチェック)を併用するのは次の理由によ
る。
In the digital control system, the analog system (check by hardware) is also used for the following reason.

演算回路6はCPUのソフトウエア処理のため図示して
いないが、CPU以外のアナログをディジタルに変換し、C
PUに入力するアナログ入力回路(A/I入力回路)、ソフ
トウェア判断結果をCPUより出力し、リレー等を動作さ
せるディジタル出力回路(D/O出力回路)等の周辺回路
も含む。
The arithmetic circuit 6 is not shown in the figure because of the software processing of the CPU, but it converts analog signals other than the CPU into digital signals, and
It also includes peripheral circuits such as an analog input circuit (A / I input circuit) that inputs to the PU, a digital output circuit (D / O output circuit) that outputs the software judgment result from the CPU, and operates a relay.

また、演算回路は、電力系統制御(系統の電圧、周波
数、電力の監視制御)の1つとして、同期投入制御を行
うものであるが、この演算回路による処理は、ハードウ
ェアおよびソフトウェアの合成であり、ハードウェアだ
けによる条件チェックであるAND回路14の出力より遅
い。
Further, the arithmetic circuit performs synchronous closing control as one of electric power system control (monitoring control of voltage, frequency, and electric power of the system), and the processing by the arithmetic circuit is a combination of hardware and software. Yes, it is slower than the output of AND circuit 14, which is a condition check only by hardware.

そこで、同期投入中、大容量モータ起動など大容量負
荷投入が発生し、両機の位相が合致しなくなった場合で
も、即応答ができず、投入信号を出力し、その結果、非
同期投入で発電機損傷などを行う危険がある。
Therefore, even if a large capacity load such as large capacity motor start occurs during synchronous closing and the phases of both machines do not match, immediate response is not possible and the closing signal is output, resulting in asynchronous closing There is a risk of damage.

その点、アナログ回路13、14の応答は早く、演算回路
6より投入信号11が出力される前にリレー15により、投
入信号11をカットすることができ、非同期投入を防止す
ることができる。
In that respect, the analog circuits 13 and 14 respond quickly, and the closing signal 11 can be cut by the relay 15 before the closing signal 11 is output from the arithmetic circuit 6, so that asynchronous closing can be prevented.

ディジタル処理はアナログ処理専用に比べてデータ処
理が容易であり、表示器と組み合わせ、この系統電力状
態表示および同期投入時の異常表示(条件不一致の原因
表示)等が可能である。
Compared to analog processing only, digital processing facilitates data processing, and by combining it with a display, it is possible to display this system power status and abnormal display at the time of synchronization input (display of cause of condition mismatch).

反面、ディジタル処理するため、入出力の周辺回路
(CPU以外の回路)も必要で、これらの異常時は誤って
同期投入することもある。例えば、アナログ入力回路が
異常で電圧差または周波数差大にもかかわらず、正常と
同じデータとなった場合は、CPUでアナログ入力データ
を信用し、位相合致点を見つけると投入信号を出力し、
大きな系統電力変動を引き起こすこともある。
On the other hand, for digital processing, I / O peripheral circuits (circuits other than CPU) are also required, and when these abnormalities occur, synchronization may be mistakenly turned on. For example, if the analog input circuit is abnormal and the voltage difference or frequency difference is large, but the data is the same as the normal data, the CPU trusts the analog input data and outputs a closing signal when a phase matching point is found,
It may also cause large grid power fluctuations.

この点、本願発明は論理回路14の出力リレー15によっ
て、演算回路6の出力で動作する遮断器1の投入回路を
インタロックするため、前記周辺回路異常による誤投入
またはCPU処理による誤投入等が防止できる。
In this respect, according to the present invention, the output relay 15 of the logic circuit 14 interlocks the closing circuit of the circuit breaker 1 operated by the output of the arithmetic circuit 6. It can be prevented.

〔発明の効果〕〔The invention's effect〕

以上のように、この発明によれば、別個独立の電圧差
検出回路,周波数差検出回路,位相差検出回路の出力に
基づいてソフトウエアによる判断により演算回路から同
期投入信号を出力するとともに該各検出回路の出力がそ
れぞれ許容値内であるか否かをハードウエアにより判断
し、全ての出力が許容値であることを条件に上記同期投
入信号を有効とするように構成したので、高周波電源に
適用しても同期投入を失敗することがなく、また、ミス
投入のおそれもなく、高信頼度電源供給装置に適用して
有効な高精度,高信頼度のものが得られる効果がある。
As described above, according to the present invention, the synchronization input signal is output from the arithmetic circuit based on the output of the voltage difference detection circuit, the frequency difference detection circuit, and the phase difference detection circuit, which are independent of each other, and the synchronization input signal is output from the arithmetic circuit. The output of the detection circuit is judged by the hardware whether or not it is within the allowable value, and it is configured so that the above synchronization input signal is valid on condition that all the outputs are within the allowable value. Even if it is applied, there is no effect of failing to apply the synchronization, and there is no fear of mistaken input, and there is an effect that when applied to the high reliability power supply device, an effective high precision and high reliability can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例による同期投入装置を示す
ブロック接続図、第2図はこの発明の同期投入装置の構
成要素である演算回路の制御動作プログラムのフローチ
ャート図、第3図は従来の同期投入装置のブロック接続
図、第4図は従来の同期投入装置の構成要素である演算
回路の制御動作プログラムのフローチャート図である。 3は電圧差検出回路、4は周波数差検出回路、5は位相
差検出回路、6は演算回路、11は同期投入信号、13は比
較増幅回路、14は論理積回路。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a block connection diagram showing a synchronization input device according to an embodiment of the present invention, FIG. 2 is a flow chart diagram of a control operation program of an arithmetic circuit which is a constituent element of the synchronization input device of the present invention, and FIG. FIG. 4 is a block connection diagram of the synchronization input device of FIG. 4, and FIG. 4 is a flow chart of a control operation program of an arithmetic circuit which is a constituent element of the conventional synchronization input device. 3 is a voltage difference detection circuit, 4 is a frequency difference detection circuit, 5 is a phase difference detection circuit, 6 is an arithmetic circuit, 11 is a synchronization input signal, 13 is a comparison amplification circuit, and 14 is a logical product circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】異なる配電系統間の電圧,周波数および位
相を合わせて遮断器を投入する同期投入装置において、
前記各配電系統における電圧差,周波数差および位相差
をそれぞれ別個独立に検出する電圧差検出回路,周波数
差検出回路および位相差検出回路と、前記電圧差検出回
路,周波数差検出回路および位相差検出回路のアナログ
出力を入力して前記電圧差,周波数差が許容値内に入る
ように前記各配電系統における発電機の電圧または周波
数を増減制御して許容値内に入れば位相合致点を見つけ
て同期投入信号を出力するソフトウエアによるディジタ
ル処理の演算回路と、この演算回路の誤動作による非同
期投入防止のため、前記電圧差検出回路,周波数差検出
回路および位相差検出回路のそれぞれの出力値を許容値
と比較する複数の比較増幅回路と、前記各比較増幅回路
の出力条件によって前記演算回路から出力される同期投
入信号を有効とするハードウエアによる判断の論理積回
路とを具備したことを特徴とする同期投入装置。
1. A synchronous closing device for closing a circuit breaker by adjusting voltage, frequency and phase between different distribution systems,
A voltage difference detection circuit, a frequency difference detection circuit, and a phase difference detection circuit that individually and independently detect a voltage difference, a frequency difference, and a phase difference in each distribution system, and the voltage difference detection circuit, the frequency difference detection circuit, and the phase difference detection circuit. Input the analog output of the circuit and increase / decrease the voltage or frequency of the generator in each distribution system so that the voltage difference and the frequency difference are within the allowable values. Allows the output values of the voltage difference detection circuit, the frequency difference detection circuit, and the phase difference detection circuit to prevent the asynchronous input due to a malfunction of the arithmetic circuit and the digital processing arithmetic circuit that outputs the synchronous closing signal. A plurality of comparison and amplification circuits to be compared with the value, and the synchronization input signal output from the arithmetic circuit is made effective depending on the output condition of each of the comparison and amplification circuits. Synchronous feeding device, characterized by comprising the AND circuit of the decisions made by hardware.
JP61255559A 1986-10-29 1986-10-29 Synchronous input device Expired - Lifetime JPH0815371B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61255559A JPH0815371B2 (en) 1986-10-29 1986-10-29 Synchronous input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61255559A JPH0815371B2 (en) 1986-10-29 1986-10-29 Synchronous input device

Publications (2)

Publication Number Publication Date
JPS63110917A JPS63110917A (en) 1988-05-16
JPH0815371B2 true JPH0815371B2 (en) 1996-02-14

Family

ID=17280404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61255559A Expired - Lifetime JPH0815371B2 (en) 1986-10-29 1986-10-29 Synchronous input device

Country Status (1)

Country Link
JP (1) JPH0815371B2 (en)

Also Published As

Publication number Publication date
JPS63110917A (en) 1988-05-16

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