JPH08148080A - Array-shaped field emission cold cathode and manufacture thereof - Google Patents

Array-shaped field emission cold cathode and manufacture thereof

Info

Publication number
JPH08148080A
JPH08148080A JP28772594A JP28772594A JPH08148080A JP H08148080 A JPH08148080 A JP H08148080A JP 28772594 A JP28772594 A JP 28772594A JP 28772594 A JP28772594 A JP 28772594A JP H08148080 A JPH08148080 A JP H08148080A
Authority
JP
Japan
Prior art keywords
emitter
cold cathode
insulating layer
field emission
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28772594A
Other languages
Japanese (ja)
Other versions
JP2630280B2 (en
Inventor
Hideo Makishima
秀男 巻島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28772594A priority Critical patent/JP2630280B2/en
Publication of JPH08148080A publication Critical patent/JPH08148080A/en
Application granted granted Critical
Publication of JP2630280B2 publication Critical patent/JP2630280B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To improve a reliable life of a cathode by preventing decreasing of insulating resistance and dielectric strength due to contamination by dirt, dust or the like received during a process of manufacturing an array-shaped field emission cold cathode and an electronic device equipped with this cathode. CONSTITUTION: Layers of insulating layer 2 and gate electrode 3 are deposited through a cathode of forming an emitter 5 by a film deposition method in a gate opening and through a mask formed on the emitter 5 formed by etching a substrate 1. In this cathode, a common insulating film 6 is formed in at least a lower part of the emitter 5 and a side surface part of the insulating layer 2. In order to form this insulating film 6, a pressure reducing CVD method or SOG technique is used.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子放出源となる冷陰
極、特にアレイ状に並んだ鋭利な先端から電子を放出す
るアレイ状電界放射冷陰極ならびにその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode serving as an electron emission source, and more particularly to an array-type field emission cold cathode which emits electrons from an array of sharp tips.

【0002】[0002]

【従来の技術】微小な円錐状のエミッタと、エミッタの
すぐ近くに形成され、エミッタからの電流を引き出す機
能ならびに電流制御機能を持つゲート電極で構成された
微小冷陰極をアレイ状に並べた冷陰極がC.A.Spi
ndt等によって提案されている(Journal o
f Applied Physics,Vol.39,
No.7,pp.3504,1968)。このスピント
(Spindt)型冷陰極は、熱陰極と比較して高い電
流密度が得られ、放出電子の速度分散が小さい等の利点
を持つ。また、単一の電界放出エミッタと比較して電流
雑音が小さく、数10〜200Vの低い電圧で動作し、
比較的悪い真空度の環境中でも動作するとされている。
2. Description of the Related Art A cold condensing cathode is formed by arranging a minute conical emitter and a micro cold cathode formed in the immediate vicinity of the emitter and having a function of drawing a current from the emitter and a current control function. The cathode is C.I. A. Spi
proposed by Ndt et al. (Journal o
f Applied Physics, Vol. 39,
No. 7, pp. 3504, 1968). This Spindt type cold cathode has advantages that a higher current density can be obtained and the velocity dispersion of emitted electrons is smaller than that of a hot cathode. In addition, the current noise is smaller than that of a single field emission emitter, and it operates at a low voltage of several tens to 200 V,
It is said to work even in an environment with a relatively poor vacuum degree.

【0003】図5(a)には前記文献に開示された従来
技術であるスピント型冷陰極主要部の構造の断面図を示
している。基板101の上に絶縁層102とゲート電極
103が堆積されている。絶縁層102とゲート電極1
03には空洞104が形成されている。空洞104の中
には、高さ約1μmの微小な円錐状のエミッタ105が
膜堆積法によって形成されている。
FIG. 5 (a) shows a sectional view of the structure of a Spindt-type cold cathode main part which is the prior art disclosed in the above document. An insulating layer 102 and a gate electrode 103 are deposited on a substrate 101. Insulating layer 102 and gate electrode 1
03 has a cavity 104 formed therein. In the cavity 104, a minute conical emitter 105 having a height of about 1 μm is formed by a film deposition method.

【0004】基板101とエミッタ105とは電気的に
接続されており、エミッタ105とゲート電極103の
間には約100Vの電圧が印加される。絶縁層102は
厚さは約1μm、ゲート電極103の開口径も約1μm
と狭く、エミッタ105の先端は10nm程度と極めて
尖鋭に作られているので、エミッタ105の先端には強
い電界が加わる。この電界が2〜5×107 V/cm以
上になるとエミッタ105の先端から電子が放出され
る。106はこの微小冷陰極の空洞104の中の等電位
線を示し、107は放出された電子の電子ビーム軌道を
示す。
The substrate 101 and the emitter 105 are electrically connected, and a voltage of about 100 V is applied between the emitter 105 and the gate electrode 103. The thickness of the insulating layer 102 is about 1 μm, and the opening diameter of the gate electrode 103 is also about 1 μm.
Since the tip of the emitter 105 is extremely sharp, about 10 nm, a strong electric field is applied to the tip of the emitter 105. When this electric field becomes 2-5 × 10 7 V / cm or more, electrons are emitted from the tip of the emitter 105. Reference numeral 106 denotes equipotential lines in the cavity 104 of the micro cold cathode, and reference numeral 107 denotes an electron beam trajectory of emitted electrons.

【0005】このような構造の微小冷陰極を基板101
の上にアレイ状に並べることにより大きな電流を放出す
る平面状の陰極が構成される。また、基板のエッチング
によってエミッタを形成する冷陰極がGrayによって
提案され、Grayタイプと呼ばれる。このGrayタ
イプの陰極を図5(b)に示す。
A micro cold cathode having such a structure is mounted on a substrate 101.
A planar cathode that emits a large current is formed by arranging the cathodes in an array. In addition, a cold cathode that forms an emitter by etching a substrate is proposed by Gray and is called a Gray type. This Gray type cathode is shown in FIG.

【0006】このような陰極では、エミッタ105とゲ
ート電極103の間に高い電界が加えられるため、陰極
の製造工程中あるいは陰極を実装した電子管等の電子装
置の製造工程中に塵埃等が絶縁層の側面につくと、エミ
ッタ105とゲート電極103の間の絶縁抵抗が低下し
て漏洩電流が流れたり、絶縁耐圧が低下して放電が発生
し、ゲート電極103やエミッタ105を破壊する恐れ
がある。
In such a cathode, since a high electric field is applied between the emitter 105 and the gate electrode 103, dust and the like are deposited on the insulating layer during the manufacturing process of the cathode or the manufacturing process of an electronic device such as an electron tube on which the cathode is mounted. In this case, the insulation resistance between the emitter 105 and the gate electrode 103 may be reduced to cause leakage current, or the withstand voltage may be reduced to cause a discharge, thereby destroying the gate electrode 103 or the emitter 105. .

【0007】図6は特開平6−52788に開示された
従来技術を示す。図6において、シリコン基板108の
上に同じシリコン材料で形成されたエミッタ109とシ
リコン基板108の上にはエミッタ109の先端部を除
いて絶縁層110が積層され、絶縁層110の上には補
助絶縁層111とこの上にゲート電極112が形成され
ている。エミッタ109の先端部露出のためのエッチン
グ工程で用いるエッチング材料に対して耐腐食性が絶縁
層110よりも優れ、エッチングされにくい補助絶縁層
111材料を使用している。このため、エミッタ109
から絶縁層110、絶縁補助層111との間に段差が形
成される。この結果、ゲート電極112とエミッタ10
9の間の表面距離が増加し、ゲート電極112の下部が
絶縁層で保護されるため、絶縁耐力が改善される。
FIG. 6 shows a prior art disclosed in Japanese Patent Application Laid-Open No. 6-52788. 6, an emitter 109 made of the same silicon material is formed on a silicon substrate 108, and an insulating layer 110 is laminated on the silicon substrate 108 except for the tip of the emitter 109. An insulating layer 111 and a gate electrode 112 are formed thereon. The material of the auxiliary insulating layer 111, which is superior in corrosion resistance to the etching material used in the etching process for exposing the tip of the emitter 109 and is hard to be etched, is used. Therefore, the emitter 109
Thus, a step is formed between the insulating layer 110 and the auxiliary insulating layer 111. As a result, the gate electrode 112 and the emitter 10
9 is increased, and the lower portion of the gate electrode 112 is protected by the insulating layer, so that the dielectric strength is improved.

【0008】また、特開平6−176685にも図6と
同様に、エミッタ下部を、ゲート電極とエミッタを分離
している絶縁層で被覆する実施例が開示されている。
Japanese Patent Application Laid-Open No. HEI 6-176686 discloses an embodiment in which the lower portion of the emitter is covered with an insulating layer separating the gate electrode and the emitter, similarly to FIG.

【0009】図7は特開平6−131968に開示され
た従来技術を示す。図7において、エミッタ105の表
面には、硬質炭素膜または炭化物層からなる被覆膜が形
成されている。このため、エミッタ105に雰囲気ガス
が吸着されにくく、安定な電子放出特性が得られる。
FIG. 7 shows a conventional technique disclosed in Japanese Patent Laid-Open No. 6-131968. In FIG. 7, a coating film made of a hard carbon film or a carbide layer is formed on the surface of the emitter 105. Therefore, the atmospheric gas is hardly adsorbed to the emitter 105, and stable electron emission characteristics can be obtained.

【0010】図8は米国特許第4940916号に開示
された従来技術である冷陰極の構造を示す。図8におい
て、絶縁基板113の上にエミッタ電極114が形成さ
れ、エミッタ電極114の上に抵抗層115、その上に
エミッタ105が形成されている。抵抗層115はエミ
ッタ105に直列の抵抗となる。
FIG. 8 shows a structure of a conventional cold cathode disclosed in US Pat. No. 4,940,916. In FIG. 8, an emitter electrode 114 is formed on an insulating substrate 113, a resistor layer 115 is formed on the emitter electrode 114, and an emitter 105 is formed on the resistor layer 115. The resistance layer 115 becomes a resistor in series with the emitter 105.

【0011】図9は特開平4−292831に開示され
た従来技術を示す。図9において、絶縁基板113の上
に順にエミッタ電極114、抵抗層115、絶縁層10
2、ゲート電極103が積層されている。しかし、エミ
ッタ105が形成されている部分にはエミッタ電極11
4は欠如しているので、抵抗層115の拡がり抵抗がエ
ミッタ105と直列になる。
FIG. 9 shows a prior art disclosed in Japanese Patent Laid-Open No. 4-292831. In FIG. 9, an emitter electrode 114, a resistance layer 115, and an insulating layer
2. The gate electrode 103 is laminated. However, in the portion where the emitter 105 is formed, the emitter electrode 11
4 is absent, so that the spreading resistance of the resistive layer 115 is in series with the emitter 105.

【0012】図8、図9に示す陰極においては、エミッ
タの下の抵抗層が負帰還抵抗あるいは電流制限抵抗とな
り、エミッタから流れる電流を制限するので、たとえ
ば、エミッタとゲート電極の間に導電性の塵埃が挟まっ
てエミッタとゲート電極の間を短絡しても過大な電流に
よって、エミッタとゲート電極構造が破壊されることは
ない。また、放電が発生する条件になっても、この抵抗
によって流れる電流が制限される。
In the cathode shown in FIGS. 8 and 9, the resistance layer below the emitter serves as a negative feedback resistance or a current limiting resistance and limits the current flowing from the emitter. Therefore, for example, conductivity is provided between the emitter and the gate electrode. Even if the dust is sandwiched and the emitter and the gate electrode are short-circuited, the structure of the emitter and the gate electrode is not destroyed by the excessive current. Also, even under the condition that discharge occurs, the current flowing through this resistor is limited.

【0013】[0013]

【発明が解決しようとする課題】電界放射冷陰極では電
子を真空中に取り出すために、エミッタ105の上部を
絶縁膜などで被覆することができず、エミッタ105お
よびその周辺部であるゲート電極103は、陰極の製造
中ならびに冷陰極を収める電子デバイスを組み立てる途
中は外部の環境に曝される。
In the field emission cold cathode, the upper part of the emitter 105 cannot be covered with an insulating film or the like in order to extract electrons into a vacuum, and the emitter 105 and the gate electrode 103 which is the peripheral part thereof. Are exposed to the external environment during manufacturing of the cathode and during assembly of the electronic device containing the cold cathode.

【0014】電界放射冷陰極の製造工程中には微細な塵
埃や吸着物質が絶縁層102の側壁あるいはエミッタ1
05の側面、ゲート電極103の表面に付着する機会が
数多く存在する。たとえば、ゲート電極103の上に堆
積したエミッタ材料をリフトオフ法によって除去する
際、ゲート電極103の上の犠牲層をエッチングするエ
ッチング工程においてもエッチング液中に溶解している
物質が付着する恐れがある。さらに、ウエハから個々の
チップに切断するダイシング工程では、ダイシングソー
によるきりかすが付着する可能性がある。この冷陰極を
実装して平面ディスプレイや電子管等の電子デバイスを
製造する場合、外囲器や内部の電極から放出されるガス
による汚染の恐れがある。
During the manufacturing process of the field emission cold cathode, fine dust and adsorbed substances are generated on the side wall of the insulating layer 102 or the emitter 1.
There are many opportunities to adhere to the side surface of 05 and the surface of the gate electrode 103. For example, when the emitter material deposited on the gate electrode 103 is removed by the lift-off method, the substance dissolved in the etching liquid may adhere even in the etching step of etching the sacrificial layer on the gate electrode 103. . Further, in the dicing step of cutting the wafer into individual chips, there is a possibility that chips generated by the dicing saw may adhere. When an electronic device such as a flat display or an electron tube is manufactured by mounting the cold cathode, there is a risk of contamination by gas released from an envelope or an internal electrode.

【0015】これらの物質が絶縁層102の側面に付着
すると、ゲート電極103とエミッタ105の間の漏洩
電流の原因となるとともに、ゲート電極103とエミッ
タ105の間の放電の原因になる。
When these substances adhere to the side surface of the insulating layer 102, they cause a leakage current between the gate electrode 103 and the emitter 105 and a discharge between the gate electrode 103 and the emitter 105.

【0016】図6に示す冷陰極や特開平6−17668
5に示す構造においては、補助絶縁層111によって絶
縁特性を改善しているが、それでもエミッタ109とゲ
ート電極112の間の絶縁物表面の距離は0.5μm以
下と極めて短いので、陰極製造工程中などで発生する微
小粒子等が絶縁層に付着するとこの間の絶縁を劣化させ
る可能性が高い。
A cold cathode shown in FIG.
In the structure shown in FIG. 5, the insulating property is improved by the auxiliary insulating layer 111, but the distance between the insulator surface between the emitter 109 and the gate electrode 112 is 0.5 μm or less, which is extremely short. If fine particles or the like generated in the above process adhere to the insulating layer, the insulation during this period is likely to deteriorate.

【0017】図7に示す陰極においては、エミッタ上に
被覆されている硬質炭素膜あるいは炭素化合物は導体あ
るいは半導体となり、絶縁層の側面に付着した塵埃等の
微粒子や吸着物による絶縁抵抗や耐圧の劣化に対する改
善効果はない。
In the cathode shown in FIG. 7, the hard carbon film or carbon compound coated on the emitter becomes a conductor or a semiconductor, and the insulation resistance and the breakdown voltage of the fine particles such as dust and the adsorbed substances adhered to the side surface of the insulating layer. There is no improvement effect on deterioration.

【0018】図8、図9に示す陰極においては、陰極全
体が破壊されたり、エミッタとゲート電極間の短絡によ
り全陰極領域が使用不可能になる恐れはないが、導電性
塵埃が付着してエミッタ105とゲート電極間103を
短絡した場合には、エミッタ105の最大動作電流より
も大きな電流が流れ、電力を消費し、電流の流れている
抵抗の部分を加熱する。さらに、このエミッタからはエ
ミッション電流が流れず、有効な電子放出領域が縮小さ
れる。
In the cathodes shown in FIGS. 8 and 9, there is no risk that the entire cathode will be destroyed or the entire cathode region will become unusable due to a short circuit between the emitter and the gate electrode, but conductive dust will adhere. When the emitter 105 and the gate electrode 103 are short-circuited, a current larger than the maximum operating current of the emitter 105 flows, power is consumed, and the resistor portion in which the current flows is heated. Further, no emission current flows from this emitter, and the effective electron emission area is reduced.

【0019】[0019]

【課題を解決するための手段】本発明においては、Sp
indtおよびGrayタイプの冷陰極において、電界
放射冷陰極のエミッタの先端とゲート電極の一部を除い
て、ゲート電極、絶縁層の側壁、エミッタを絶縁膜で被
覆する。
According to the present invention, Sp
In the indt and gray type cold cathode, the gate electrode, the side wall of the insulating layer, and the emitter are covered with the insulating film except for the tip of the emitter and the part of the gate electrode of the field emission cold cathode.

【0020】この絶縁膜を形成するため、減圧CVD法
あるいはSOG技術を使用する。
In order to form this insulating film, a low pressure CVD method or SOG technique is used.

【0021】[0021]

【作用】この結果、冷陰極の製造工程中ならびに冷陰極
を実装する電子装置の製作中に、塵埃の付着や汚染物質
の吸着によって生じるエミッターゲート電極間の絶縁抵
抗の低下や放電の恐れを取り除くことができる。
As a result, during the manufacturing process of the cold cathode and during the manufacture of the electronic device on which the cold cathode is mounted, the possibility of lowering the insulation resistance between the emitter and gate electrodes and the danger of electric discharge caused by adhesion of dust and adsorption of contaminants is eliminated. be able to.

【0022】これにより、冷陰極と冷陰極を使用した電
子デバイスの信頼性ならびに製造歩留まりが向上する。
As a result, the reliability and the production yield of the cold cathode and the electronic device using the cold cathode are improved.

【0023】[0023]

【実施例】本発明について図面を参照して詳細に説明す
る。図1は本発明の第1の実施例を示す電界放射冷陰極
の構造の断面図を示す。図1において、シリコンの基板
1には下から順に絶縁層2、ゲート電極3が積層され、
ゲート電極3と絶縁層2には微小な空洞4が形成されて
いる。空洞4の中には、電子を放出する円錐状のエミッ
タ5がシリコンの基板1のエッチングによって形成さ
れ、空洞4の中ではゲート電極3の側面、絶縁層2の側
面、エミッタ5の下部には絶縁膜6が被覆されている。
エミッタ5、ゲート電極3の開口、空洞4で微小冷陰極
7が形成される。
The present invention will be described in detail with reference to the drawings. FIG. 1 shows a sectional view of the structure of a field emission cold cathode showing a first embodiment of the present invention. In FIG. 1, an insulating layer 2 and a gate electrode 3 are laminated on a silicon substrate 1 in order from the bottom,
A minute cavity 4 is formed in the gate electrode 3 and the insulating layer 2. In the cavity 4, a conical emitter 5 for emitting electrons is formed by etching the silicon substrate 1. In the cavity 4, the side of the gate electrode 3, the side of the insulating layer 2, and the bottom of the emitter 5 are formed. The insulating film 6 is covered.
The minute cold cathode 7 is formed by the emitter 5, the opening of the gate electrode 3, and the cavity 4.

【0024】絶縁層2はシリコン酸化物あるいはシリコ
ン窒化物、ゲート電極3はポリシリコンで作られてい
る。ゲート電極3の開口の直径は約1μm、エミッタ5
の高さは約1μm、絶縁層2の厚さは約0.8μm、ゲ
ート電極3の厚さは約0.2μmである。このような微
細な構造の微小冷陰極を単一あるいはアレイ状に並べて
電子源すなわち陰極として使用する。
The insulating layer 2 is made of silicon oxide or silicon nitride, and the gate electrode 3 is made of polysilicon. The diameter of the opening of the gate electrode 3 is about 1 μm,
Is about 1 μm, the thickness of the insulating layer 2 is about 0.8 μm, and the thickness of the gate electrode 3 is about 0.2 μm. Micro cold cathodes having such a fine structure are arranged in a single or array form and used as an electron source, that is, a cathode.

【0025】図1から明らかなように、この構造の陰極
においては、ゲート電極3と絶縁層2のそれぞれの側面
部ならびにエミッタ5の下部が共通の絶縁膜6で被覆さ
れている。このため、図6に示す従来の技術と比較し
て、ゲート電極3とエミッタ5との間の絶縁表面距離が
長くなり、絶縁体表面の汚染があってもこれを伝わって
流れる電流を十分小さく抑えることが可能になる。この
結果、絶縁抵抗劣化の可能性が極めて小さくなる。さら
に、微小な放電の引き金になる電子が放出され易いのは
負の電圧を印加した電極と誘電体、真空の3者が交わる
ところとされているが、図1の場合にはエミッタ5の先
端近くの絶縁膜6が途切れる絶縁膜端部8がこれに相当
する。ここから電子の放出があった場合にも、この電子
は絶縁層2や絶縁膜6のような絶縁体の表面に当たるこ
となく直接ゲート電極3あるいは図には示していないが
エミッタ5に対し正の電圧を印加した電極、たとえば陽
極に達する。従って、絶縁体表面に衝突して多数の2次
電子を発生させて放電の元になる電子を増倍させること
もない。さらに、微粒子が空洞4の中に付着した場合に
もエミッタ3の表面の絶縁膜6によってエミッタ5とゲ
ート電極3を短絡させる可能性は小さくなる。
As is apparent from FIG. 1, in the cathode having this structure, the side surfaces of the gate electrode 3 and the insulating layer 2 and the lower part of the emitter 5 are covered with a common insulating film 6. Therefore, as compared with the conventional technique shown in FIG. 6, the insulating surface distance between gate electrode 3 and emitter 5 becomes longer, and even if there is contamination on the surface of the insulator, the current flowing through the surface is sufficiently small. It becomes possible to suppress. As a result, the possibility of insulation resistance deterioration becomes extremely small. Further, it is said that the electron that triggers the minute discharge is easily emitted at the intersection of the electrode to which the negative voltage is applied, the dielectric and the vacuum. In the case of FIG. The insulating film end portion 8 where the nearby insulating film 6 is cut off corresponds to this. Even when electrons are emitted therefrom, the electrons do not hit the surface of an insulator such as the insulating layer 2 or the insulating film 6 and are directly directed to the gate electrode 3 or to the emitter 5 although not shown in the drawing. A voltage is applied to an electrode, for example, an anode. Therefore, there is no need to generate a large number of secondary electrons by colliding with the surface of the insulator to multiply the electrons that cause discharge. Further, even when fine particles adhere to the cavity 4, the possibility that the emitter 5 and the gate electrode 3 are short-circuited by the insulating film 6 on the surface of the emitter 3 is reduced.

【0026】この陰極の基本構造はGrayタイプと呼
ばれ、製造方法は公知である(たとえば応用物理、第5
9巻、第2号、pp.164〜169、1990.)。
絶縁膜6の形成には、たとえばLPCVD(減圧CV
D)によって空洞4の内部、エミッタ5の表面、ゲート
電極3の側面を含めて全面にシリコン酸化物、シリコン
窒化物などの絶縁体を堆積し、次にドライエッチング等
によって誘電体の一部を除去して図1に示すような構造
を得る。
The basic structure of this cathode is called Gray type, and its manufacturing method is known (for example, Applied Physics, No. 5).
9, Vol. 2, No. 2, pp. 164-169, 1990. ).
For example, LPCVD (low-pressure CV)
D) deposits an insulator such as silicon oxide or silicon nitride on the entire surface including the inside of the cavity 4, the surface of the emitter 5 and the side surface of the gate electrode 3, and then a part of the dielectric is removed by dry etching or the like. The structure is removed to obtain the structure shown in FIG.

【0027】図2は本発明の第2の実施例を示す電界放
射冷陰極の構造の断面図を示す。図2において、図1と
同じ番号の部分は図1と全く同じ構成要素を示し、各構
成要素の材料、寸法は図1に示す第1の実施例と同じで
ある。図2においては、絶縁膜6は熱酸化法によって成
膜される。ゲート電極3にはポリシリコンを使用してい
るので、ゲート電極3の上および側面にシリコン酸化物
が形成される。第1の実施例と同様にゲート電極3の上
および、エミッタ5の先端の酸化物を除去することによ
って図2のような構造が実現される。
FIG. 2 is a sectional view showing the structure of a field emission cold cathode according to a second embodiment of the present invention. In FIG. 2, the parts with the same numbers as in FIG. 1 indicate the same constituent elements as in FIG. 1, and the materials and dimensions of each constituent element are the same as in the first embodiment shown in FIG. In FIG. 2, the insulating film 6 is formed by a thermal oxidation method. Since polysilicon is used for the gate electrode 3, silicon oxide is formed on the upper and side surfaces of the gate electrode 3. The structure shown in FIG. 2 is realized by removing the oxide on the gate electrode 3 and the tip of the emitter 5 as in the first embodiment.

【0028】本実施例においても第1の実施例と同様な
効果が期待できる。絶縁膜6がない場合には、ゲート電
極3と基板1(エミッタ5)との間の絶縁表面距離は絶
縁層2の厚さよりも僅かに長い程度であるが、絶縁膜6
を形成することによってこの絶縁表面距離を絶縁層2の
厚さの1.5倍以上にすることが出来る。さらに、エミ
ッタ5と絶縁層6が接する部分から電子が放出されて
も、直接ゲート電極に電子が到達し、絶縁体によって電
子が増倍されることもない。
In this embodiment, the same effect as in the first embodiment can be expected. When the insulating film 6 is not provided, the insulating surface distance between the gate electrode 3 and the substrate 1 (emitter 5) is slightly longer than the thickness of the insulating layer 2;
Is formed, the insulating surface distance can be made 1.5 times or more the thickness of the insulating layer 2. Furthermore, even if electrons are emitted from the portion where the emitter 5 and the insulating layer 6 are in contact, the electrons directly reach the gate electrode and the electrons are not multiplied by the insulator.

【0029】図3には図2の電界放射冷陰極の製造工程
図を示す。基板1の上にシリコン窒化物のような絶縁物
を用いたマスク用絶縁層9を成膜する(図3(a))。
次に、マスク用絶縁層9をパターンニングして、ゲート
電極3の開口に相当するマスクとする(図3(b))。
このマスク用絶縁層9′をマスクとして基板1をエッチ
ングして図3(c)を得る。この上に絶縁層2およびポ
リシリコンのゲート電極3を基板1に対し垂直方向から
堆積して図3(d)を得る。次に、マスク用絶縁層9′
をエッチングによって除去し、さらに熱酸化によってポ
リシリコンのゲート電極3の側面および上部ならびにエ
ミッタ5の上にシリコン酸化物の絶縁膜層10を成膜し
て、図3(e)を得る。ここでは、エミッタ5の先端は
両側から酸化され、先端の尖った構造が得られる。さら
に、ゲート電極3およびエミッタ5の先端のシリコン酸
化物をエッチングによって除去して図3(f)を得る。
FIG. 3 shows a manufacturing process diagram of the field emission cold cathode of FIG. An insulating layer 9 for a mask using an insulator such as silicon nitride is formed on the substrate 1 (FIG. 3A).
Next, the mask insulating layer 9 is patterned to form a mask corresponding to the opening of the gate electrode 3 (FIG. 3B).
The substrate 1 is etched using the mask insulating layer 9 'as a mask to obtain FIG. On this, an insulating layer 2 and a polysilicon gate electrode 3 are deposited in a direction perpendicular to the substrate 1 to obtain FIG. Next, the mask insulating layer 9 '
Is removed by etching, and the insulating film layer 10 of silicon oxide is formed on the side surface and the upper portion of the gate electrode 3 of polysilicon and on the emitter 5 by thermal oxidation to obtain FIG. Here, the tip of the emitter 5 is oxidized from both sides, and a structure with a sharp tip is obtained. Further, the silicon oxide at the tips of the gate electrode 3 and the emitter 5 is removed by etching to obtain FIG.

【0030】図4は本発明の第3の実施例を示す電界放
射冷陰極の構造の断面図を示す。図4において、図1と
同じ番号の部分は図1と全く同じ構成要素を示し、各構
成要素の材料、寸法は図1に示す第1の実施例と同じで
ある。図4においては、エミッタ12はタングステンあ
るいはモリブデンのような耐熱金属で作られ、ゲート電
極11はタングステン、モリブデン、ニオブ、タングス
テンシリサイド等の金属あるいは金属化合物で作られ、
絶縁層2には例えばシリコンの熱酸化膜(SiO2 )を
使用する。ゲート開口の直径は約1μm、エミッタ12
の高さは約1μm、絶縁層2の厚さは約0.8μm、ゲ
ート電極11の厚さは約0.2μmである。
FIG. 4 is a sectional view showing the structure of a field emission cold cathode according to a third embodiment of the present invention. 4, parts having the same numbers as in FIG. 1 indicate the same constituent elements as those in FIG. 1, and the materials and dimensions of each constituent element are the same as those in the first embodiment shown in FIG. In FIG. 4, the emitter 12 is made of a heat-resistant metal such as tungsten or molybdenum, and the gate electrode 11 is made of a metal or a metal compound such as tungsten, molybdenum, niobium, or tungsten silicide.
For example, a thermal oxide film of silicon (SiO 2 ) is used for the insulating layer 2. The diameter of the gate opening is about 1 μm and the emitter 12
Has a height of about 1 μm, the insulating layer 2 has a thickness of about 0.8 μm, and the gate electrode 11 has a thickness of about 0.2 μm.

【0031】この陰極を製作するには、基本的には(J
ournal of Applied Physic
s,Vol.39,No.7,pp.3504,196
8)等に開示されているように、ゲート電極11と絶縁
層2に空洞を形成したのちウエハを回転させながら斜め
方向からアルミニウム、酸化アルミニウムなどの犠牲層
を堆積し、次にエミッタ材料をウエハの真上から堆積す
れば良い。次に、SOGによる絶縁体をウエハの上に成
膜して、エッチバック等の手段によってゲート電極11
の上およびエミッタ12の先端の絶縁体を除去し、図4
に示す絶縁膜13を形成する。
To manufacture this cathode, basically (J
own of Applied Physic
s, Vol. 39, no. 7, pp. 3504,196
8) etc., after forming a cavity in the gate electrode 11 and the insulating layer 2, a sacrificial layer such as aluminum or aluminum oxide is deposited from an oblique direction while rotating the wafer, and then the emitter material is deposited on the wafer. What is necessary is just to deposit from right above. Next, an insulator made of SOG is formed on the wafer, and the gate electrode 11 is formed by means such as etch back.
4 and the insulator on the top of the emitter 12 and the tip of the emitter 12 are removed.
Is formed.

【0032】[0032]

【発明の効果】以上説明したように、本発明の冷陰極に
おいては、冷陰極の製造工程中ならびに冷陰極を実装す
る電子装置の製造中に、塵埃の付着や汚染物質の吸着に
よって生じるエミッターゲート電極間の絶縁抵抗の低下
や絶縁耐圧の低下および放電の恐れを取り除くことがで
きる。これにより、冷陰極と冷陰極を使用した電子デバ
イスの信頼性ならびに製造歩留まりが向上する。
As described above, in the cold cathode of the present invention, during the manufacturing process of the cold cathode and the manufacturing of the electronic device on which the cold cathode is mounted, the emitter gate generated by the adhesion of dust and the adsorption of the contaminants is produced. It is possible to eliminate the possibility of lowering the insulation resistance between the electrodes, lowering the withstand voltage and discharging. This improves the reliability and manufacturing yield of the cold cathode and the electronic device using the cold cathode.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す電界放射冷陰極の
断面図である。
FIG. 1 is a cross-sectional view of a field emission cold cathode according to a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す電界放出冷陰極の
構造図である。
FIG. 2 is a structural diagram of a field emission cold cathode showing a second embodiment of the present invention.

【図3】(a)〜(f)は本発明の第2の実施例を示す
電界放出冷陰極の製造工程図である。
FIGS. 3 (a) to 3 (f) are process diagrams for manufacturing a field emission cold cathode according to a second embodiment of the present invention.

【図4】本発明の第3の実施例を示す電界放出冷陰極の
構造図である。
FIG. 4 is a structural diagram of a field emission cold cathode showing a third embodiment of the present invention.

【図5】従来技術のSpindtタイプ(a)およびG
rayタイプ(b)の冷陰極の断面図である。
FIG. 5 Prior art Spindt type (a) and G
It is sectional drawing of the cold cathode of a ray type (b).

【図6】特開平6−53788に開示された従来技術の
冷陰極の断面図である。
FIG. 6 is a sectional view of a conventional cold cathode disclosed in JP-A-6-53788.

【図7】特開平6−131968に開示された従来技術
の冷陰極の断面図である。
FIG. 7 is a cross-sectional view of a conventional cold cathode disclosed in JP-A-6-131968.

【図8】米国特許第4940916号に開示された従来
技術の冷陰極の断面図である。
FIG. 8 is a cross-sectional view of a prior art cold cathode disclosed in US Pat. No. 4,940,916.

【図9】特開平4−292831に開示された従来技術
の冷陰極の断面図である。
FIG. 9 is a sectional view of a conventional cold cathode disclosed in JP-A-4-292831.

【符号の説明】[Explanation of symbols]

1,101 基板 2,102,110 絶縁層 3,11,103,112 ゲート電極 4,104 空洞 5,12,105,109 エミッタ 6,13 絶縁膜 7 微小冷陰極 8 絶縁膜端部 9 マスク用絶縁層 10 絶縁膜層 106 等電位面 107 電子ビーム軌道 108 シリコン基板 111 補助絶縁層 113 絶縁基板 114 エミッタ電極 115 抵抗層 DESCRIPTION OF SYMBOLS 1, 101 Substrate 2, 102, 110 Insulating layer 3, 11, 103, 112 Gate electrode 4, 104 Cavity 5, 12, 105, 109 Emitter 6, 13 Insulating film 7 Micro cold cathode 8 Insulating film edge 9 Insulation for mask Layer 10 insulating film layer 106 equipotential surface 107 electron beam orbit 108 silicon substrate 111 auxiliary insulating layer 113 insulating substrate 114 emitter electrode 115 resistance layer

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板と、前記基板の上にエッチング法に
よって形成し、先端を先鋭化した電子放出電極と、前記
電子放出電極とその付近を除いて前記基板の上に形成し
た絶縁層と、前記電子放出電極を取り囲む開口を持つ制
御電極とから成る複数の微小冷陰極から構成されたアレ
イ状電界放射冷陰極において、少なくとも、絶縁層の側
壁と、電子放出電極の基板付近とを絶縁膜で被覆したこ
とを特徴とするアレイ状電界放射例陰極。
1. A substrate, an electron-emitting electrode formed on the substrate by an etching method and having a sharpened tip, an insulating layer formed on the substrate except the electron-emitting electrode and its vicinity, In an array-type field emission cold cathode composed of a plurality of minute cold cathodes including a control electrode having an opening surrounding the electron emission electrode, at least a side wall of the insulating layer and the vicinity of the substrate of the electron emission electrode are formed of an insulating film. Arrayed field emission example cathode characterized by being coated.
【請求項2】 基板と、前記基板の上に膜堆積法によっ
て形成し、先端を先鋭化した電子放出電極と、前記電子
放出電極とその付近を除いて前記基板の上に形成した絶
縁層と、前記電子放出電極を取り囲む開口を持つ制御電
極とから成る複数の微小冷陰極から構成されたアレイ状
電界放射冷陰極において、少なくとも、絶縁層の側壁
と、電子放出電極の基板付近を絶縁膜で被覆したことを
特徴とするアレイ状電界放射冷陰極。
2. A substrate, an electron-emitting electrode formed on the substrate by a film deposition method and having a sharpened tip, and an insulating layer formed on the substrate except the electron-emitting electrode and its vicinity. In an array-type field emission cold cathode composed of a plurality of minute cold cathodes each including a control electrode having an opening surrounding the electron emission electrode, at least a side wall of the insulating layer and the vicinity of the substrate of the electron emission electrode are formed of an insulating film. An array-type field emission cold cathode characterized by being coated.
【請求項3】 前記絶縁膜が減圧CVD法によって成膜
されたことを特徴とする請求項1記載のアレイ状電界放
射冷陰極の製造方法。
3. The method for manufacturing an array field emission cold cathode according to claim 1, wherein the insulating film is formed by a low pressure CVD method.
【請求項4】 前記制御電極がポリシリコンで形成さ
れ、前記絶縁膜が熱酸化法によって成膜されたことを特
徴とする請求項1記載のアレイ状電界放射冷陰極の製造
方法。
4. The method of manufacturing an array field emission cold cathode according to claim 1, wherein the control electrode is formed of polysilicon, and the insulating film is formed by a thermal oxidation method.
【請求項5】 前記絶縁膜がSOG(Spin on
glass)法によって成膜されたことを特徴とする請
求項2記載のアレイ状電界放射冷陰極の製造方法。
5. The insulating film is SOG (Spin on)
The method for manufacturing an array-type field emission cold cathode according to claim 2, wherein the film is formed by a glass method.
JP28772594A 1994-11-22 1994-11-22 Array-shaped field emission cold cathode and its manufacturing method Expired - Lifetime JP2630280B2 (en)

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Publications (2)

Publication Number Publication Date
JPH08148080A true JPH08148080A (en) 1996-06-07
JP2630280B2 JP2630280B2 (en) 1997-07-16

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Country Status (1)

Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369496B1 (en) 1997-12-03 2002-04-09 Nec Corporation Micro cold cathode with shield member
KR100726838B1 (en) * 2000-08-31 2007-06-11 주식회사 엘지이아이 electron gun and the fabrication method thereof for the cathode ray tube with cold cathode
US7456564B2 (en) 2004-05-04 2008-11-25 Electronics And Telecommunications Research Institute Field emission display having a gate portion with a metal mesh

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714499A (en) * 1993-06-24 1995-01-17 Toppan Printing Co Ltd Field emission element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714499A (en) * 1993-06-24 1995-01-17 Toppan Printing Co Ltd Field emission element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369496B1 (en) 1997-12-03 2002-04-09 Nec Corporation Micro cold cathode with shield member
KR100726838B1 (en) * 2000-08-31 2007-06-11 주식회사 엘지이아이 electron gun and the fabrication method thereof for the cathode ray tube with cold cathode
US7456564B2 (en) 2004-05-04 2008-11-25 Electronics And Telecommunications Research Institute Field emission display having a gate portion with a metal mesh

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Publication number Publication date
JP2630280B2 (en) 1997-07-16

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