JPH08142456A - Image forming device - Google Patents

Abstract

PURPOSE: To provide an image forming device for realizing effective power saving controlling. CONSTITUTION: The image forming device consists of a CPU 1, which stops internal operations by means of halt instruction, a ROM 2, a RAM 3, an interface 7 for connecting with an external host device, a panel part 8, in which operating switches and a display LED are built, an image forming part 6, a control circuit 4 and the like. After the elapse of the predetermined period of time since the final printing operation, the migration to power saving mode is performed by the CPU 1 through halt instruction. After that, the CPU 1 stops an oscillating circuit 18 and cuts off a logic power source 11. Then, when an interface 7 receives data from the external host device or the operating switches in the panel part 8 is actuated, an interruption signal INT goes into the CPU 1 so as to re-start the printing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus for forming an image on a recording medium, and more particularly to an image forming apparatus capable of reducing power consumption when not operating.

[0002]

2. Description of the Related Art Conventionally, in an image forming apparatus such as a serial dot printer, when the transmission of print data from an external host device such as a computer is interrupted for a certain period of time, the operation of a portion such as a motor and a light source that consumes a large amount of power is stopped. Some are in a power saving state.

FIG. 6 is a block diagram showing an example of a conventional electrical configuration. This image forming apparatus includes a CPU (Central Processing Unit) 61 for managing the operation of the entire apparatus, a ROM (Read Only Memory) 62 which is a non-volatile memory, and a RAM (Random Access Memory) capable of rewriting data.
63, an interface (I / F) 67 for connecting to an external host device (not shown), signal input means such as operation switches, and signal display means such as display LEDs (light emitting diodes) and buzzers. The panel unit 68 includes an image forming unit 66 for forming an image on a recording medium, a control circuit 64 for controlling the image forming unit 66, and the like.

The CPU 61 performs signal processing such as data input / output, data transfer, calculation, etc. according to a program stored in the ROM 62. The ROM 62 stores programs and data necessary for the operation of the CPU 61 and data necessary for printing such as character codes and character fonts. RAM6
Reference numeral 3 is used for a work area of the CPU 61, temporary storage of data received from an external host device, expansion of document data, and the like. The interface 67 exchanges data with an external host device. Such CPU 61, ROM
62, RAM 63, interface 67, panel section 68
The control circuit 64 and the control circuit 64 are connected to each other by a bus 69 including an address bus, a data bus, a control bus and the like. A clock circuit 60 that generates a clock CK that determines the operation timing is built in the CPU 61 and is also supplied to the control circuit 64.

The image forming section 66 includes a print head for printing on a recording medium and a carriage (C
A drive unit such as a CR motor that moves R) in the width direction of the recording medium or a PF (paper feed) motor that conveys the recording medium by a fixed amount is provided. The drive circuit 65 is
The image forming unit 66 based on the control signal from the control circuit 64.
Drive each drive unit of.

In such an image forming apparatus, a logic power source 71 that supplies power to a logic circuit that handles digital signals, and a drive power source 70 that supplies power to a unit such as a motor that requires relatively large power. And are provided. The drive power supply 70 supplies power to the drive circuit 65 via the power supply line V3.

On the other hand, the logic power source 71 is, for example, TTL.
A direct current of 5V compatible with CMOS is output to the power supply line V1, and is supplied to the CPU 61, the ROM 62, the RAM 63, the interface 67, the panel unit 68, the control circuit 64, and the power supply disconnecting circuit 72 described later. Also, the power supply line V
A part of 1 serves as a power supply line V2 through a power supply disconnecting circuit 72 such as a relay, and is connected to a part of the panel 68 and the control circuit 64 capable of interrupting power supply. The power supply disconnection circuit 72 supplies power to the power supply line V2 when the power saving signal SP from the control circuit 64 is at a high level, while it supplies power to the power supply line V2 when the power saving signal SP is at a low level.
The power supply to 2 is cut off.

FIG. 7 is a flow chart showing the operation of FIG. First, when the image forming apparatus is powered on, the RAM 63, the control circuit 64, the interface 67, the panel section 68, and the control circuit 64 are initialized in step s1, and the control circuit 64 is operated in step s2. The drive circuit 65 and the image forming unit 66 are operated to perform an initial operation for initializing the print position, print conditions, etc., and the print standby state is set. When a print command from the external host device is received in this state, the print operation can be started.

Next, in step s3, a timer for measuring time is started, and in step s4, it is determined whether print data is input from the external host device,
If there is no data input, the process proceeds to step s10, and steps s4 and s10 are repeated until a fixed time has elapsed since the timer started counting time.

On the other hand, if there is data input from the external host device in step s4, the process proceeds to step s5, the timer operation is stopped, and the RAM is operated in step s6.
Document data is developed based on the received data stored in 63, the drive circuit 65 and the image forming unit 66 are operated via the control circuit 64, and printing is performed on the recording medium. In step s7, it is determined whether or not the printing is completed. In step s8, the presence or absence of print data is determined, and a series of operations is repeated until the printing of the print data is completed. When there is no data to be printed, the timer is restarted in step s9.

In this way, the fixed time is measured from the time when the initial operation or the last printing operation is completed, and it is monitored whether new print data is received during that period. If a certain period of time has passed since there was no print data, step s
11, the timer operation is stopped, and step s1
2 stops the operation of drive circuit 65, and drives power supply 7
The power supply from 0 to the image forming unit 66 is stopped. In this way, the energization of the CR motor, the PF motor, etc. is all cut off, and a relatively large amount of power can be saved at this stage.

In the next step s13, the power saving signal S
P is set to the low level to cut off the power supply to the power supply line V2. At this stage, a part of the panel unit 68, for example, the display LED and the like and a part of the control circuit 64 are de-energized, thereby saving a part of power consumption of the logic system. In the next step s14, similarly to step s4, the process waits until print data is input from the external host device.

When data input is restarted, step s15
In step 1, the power saving signal SP is set to a high level to restart the power supply to the power supply line V2, the process returns to step s1, the logic system and the drive system are initialized again, and the printing operation is executed.

When the state in which there is no data to be printed continues for a certain period of time, power saving control becomes possible by stopping the energization of a part of the logic system and the drive system.

Further, as another prior art, Japanese Patent Laid-Open No. 6-26
No. 6463 discloses an image forming apparatus in which the oscillator is stopped until the control signal is input from the host device, and the operation of the CPU is stopped.

[0016]

However, in the conventional image forming apparatus shown in FIGS. 6 and 7, the power supply line V
Although it is possible to save power in a part of the logic system to which the power is supplied by 2 and the drive system, a part in which the power supply line V1 supplies the power, that is, a part related to the CPU 60, the ROM 62, the RAM 63, and the like is out of the power saving control. There is.
Therefore, although the power-off circuit 72 is required, a large power saving effect cannot be realized.

In a device in which a host device and a printing device are integrated, such as a word processor, a power saving control method is possible in which the logic power supply is cut off under the control of the host device side. However, when the host device and the printing device are separated, a special interface must be prepared to shut off the logic power supply under the control of the host device side. In addition, if the printing apparatus alone performs power saving control such as shutting off the logic power source, it cuts off its own power source, making it difficult to perform the next recovery operation.

Therefore, a method of switching to a backup power source such as a battery when the logic power source is cut off can be considered.
When the PU, ROM, and RAM are operating, the consumption current remains considerably, so the consumption of the backup power supply is remarkable,
To guarantee long-term operation, a large-capacity, large-sized backup power supply is indispensable.

Therefore, the object of power saving control in the printing apparatus alone is limited to only shutting down the drive power source, or at most a part of the logic system, for example, turning off the display LED.

It is an object of the present invention to provide an image forming apparatus capable of realizing more effective power saving by expanding the target of power saving control to most of logic circuits.

[0021]

According to the present invention, there is provided a central processing unit for performing signal processing according to a program, a memory unit for storing a program and data, an interface unit for connecting to an external host device, and a signal. A panel unit including an input unit and a signal display unit, an image forming unit for forming an image on a recording medium, a control unit for controlling the image forming unit, a central processing unit, a memory unit, an interface unit, and a panel. In an image forming apparatus including a bus for connecting the control unit and the control unit to each other, a clock generation unit that generates a clock that determines the operation timing of the central processing unit, and power supply to the memory unit and the control unit are controlled. The power supply control unit and the oscillation monitoring unit for monitoring the operation of the clock generation unit are provided, and the central processing unit is provided until the level of the interrupt signal changes. When the signal input from the external host device to the interface section is interrupted for a predetermined time, the central processing section shifts to the suspend mode and the operation of the clock generating section is stopped. When the oscillation monitoring unit instructs the power supply control unit to stop the power supply to the memory unit and the control unit, and when a signal input from the interface unit or the panel unit occurs, the operation of the clock generation unit is performed. Is restarted, the power supply to the memory unit and the control unit is restarted, the level of the interrupt signal is changed, and the central processing unit releases the temporary stop mode. Further, the present invention is, after a predetermined time has elapsed from the restart of the operation of the clock generator,
It is characterized in that the level of the interrupt signal of the central processing unit is changed.

[0022]

According to the present invention, the central processing unit has a halt (HAL)
T) When the instruction is executed, the internal operation is automatically stopped to enter the suspend mode (Halt state). In this mode, the input / output operation with the peripheral circuit is stopped and the power consumption due to the clock operation is suppressed. . When the level of the interrupt signal exemplified by reset, non-maskable interrupt, maskable interrupt, or the like changes, the central processing unit that has transitioned to the suspend mode releases the suspend mode and returns to the normal operation.

Therefore, when the signal input from the external host device to the interface unit is interrupted for a predetermined time, the central processing unit shifts to the suspend mode, thereby stopping the operation of peripheral circuits such as the memory unit and the control unit. Therefore, power consumption is significantly suppressed. On the other hand, when a signal is input from the interface section or panel section, the level of the interrupt signal is changed and the central processing section cancels the pause mode, so that the printing operation can be performed promptly without delaying data reception or switch operation. I can resume.

Further, by stopping the operation of the clock generating unit along with the transition to the suspend mode of the central processing unit, the power consumption of the clock generating unit and its peripheral circuits can be suppressed.

Further, when the oscillation monitor detects that the operation of the clock generator has stopped, it instructs the power supply controller to stop the power supply to the memory and controller. Therefore, the current consumption in the memory unit and the control unit becomes zero, and more effective power saving becomes possible.

When a signal is input from the interface section or the panel section, the operation of the clock generating section restarts, and after a lapse of a predetermined time, the level of the interrupt signal of the central processing section is changed. Therefore, the central processing unit returns to the normal operation after the clock is sufficiently stabilized, and the malfunction due to the unstable clock can be surely prevented.

[0027]

1 is a block diagram showing the electrical construction of an embodiment of the present invention. The image forming apparatus includes a CPU (Central Processing Unit) 1 for managing the operation of the entire apparatus, a ROM (Read Only Memory) 2 which is a non-volatile memory, and a RAM (Random Access Memory) 3 in which data can be rewritten.
A panel in which an interface (I / F) 7 for connecting to an external host device (not shown), signal input means such as operation switches, and signal display means such as display LEDs (light emitting diodes) and buzzers are incorporated. A unit 8, an image forming unit 6 for forming an image on a recording medium, a control circuit 4 for controlling the image forming unit 6, and the like.

The CPU 1 carries out signal processing such as data input / output, data transfer and calculation according to a program stored in the ROM 2. It is preferable to use a CMOS type CPU1 in terms of power consumption, for example, Z80.
A type (model number “LH5080L”, manufactured by Sharp) is exemplified, and when the CPU 1 executes a halt command, it has a power save mode (temporary stop mode) that automatically stops the internal operation and enters the halt state. RO in this mode
Input / output operations with peripheral circuits such as M2 and RAM3 are stopped, and power consumption due to clock operation is suppressed. The CPU 1 that has entered the power save mode cancels the power save mode by a hardware interrupt such as a reset, a non-maskable interrupt, or a maskable interrupt, and returns to normal operation. In the present embodiment, an example of returning using a maskable interrupt will be described.

The ROM 2 stores programs and data necessary for the operation of the CPU 1 and data necessary for printing such as character codes and character fonts. RAM3 is CPU
The first work area is used for temporary storage of received data from an external host device and expansion of document data. The interface 7 exchanges data with an external host device. The CPU 1, the ROM 2, the RAM 3, the interface 7, the panel unit 8 and the control circuit 4 are preferably CMOS type ICs in terms of power consumption, and are composed of an address bus, a data bus, a control bus and the like. They are interconnected by a bus 9.

The image forming section 6 includes a print head for printing on a recording medium and a carriage (CR) having the print head mounted thereon.
A drive unit such as a CR motor for moving the recording medium in the width direction of the recording medium and a PF (paper feed) motor for conveying the recording medium by a constant amount. The drive circuit 5 drives each drive unit of the image forming unit 6 based on the control signal from the control circuit 4.

In such an image forming apparatus, a drive power supply 10 for supplying electric power to a unit requiring relatively large electric power such as a motor, and a logic power supply 11 for supplying electric power to a logic system circuit which handles digital signals. And a backup power supply 20. The drive power supply 10 supplies power to the drive circuit 5 via the power supply line V3.

The logic power supply 11 is, for example, TTL or CM.
DC 5V compatible with the OS is supplied to the power supply line V2 via the power supply disconnecting circuit 12 such as a relay, and the CPU1,
ROM2, RAM3, control circuit 4, interface 7,
Power is supplied to the panel section 8 and the like. The power-off circuit 12
Power is supplied to the power supply line V2 when the power saving signal SP from the oscillation monitoring circuit 21 described later is at a high level, while power supply to the power supply line V2 is cut off when the power saving signal SP is at a low level.

Further, the backup power supply 20 is composed of, for example, a primary battery or a secondary battery, and even if the power supply line V2 is cut off by the power supply disconnecting circuit 12, for example, DC 5V is output to the power supply line V1, CPU1,
Power is constantly supplied to the interface 7 and the panel unit 8.

It should be noted that the interface 7
When receiving data from the external host device, outputs a restart signal B1 (low level) meaning that data is received. Further, when the operation switch such as the paper feed is operated, the panel section 8 has a restart signal B2 which means that a signal is input.
Outputs (low level). The NAND element 17 to which the restart signals B1 and B2 are input outputs a high level and outputs an interrupt signal INTA to the oscillation circuit 18 when at least one input becomes a low level. Here, an example in which the restart signals B1 and B2 are negative logic and the interrupt signal INTA is positive logic is shown, but the positive / negative of the logic can be changed as necessary.

An oscillation circuit 18 for generating a clock CK for determining the operation timing of the CPU 1 is provided outside the CPU 1, and the clock CK is also supplied to the control circuit 4.

A reset circuit 19 which outputs a reset signal RESET when the power is turned on or a reset operation is provided, and is input to the CPU 1 and the oscillation circuit 18. Further, when the CPU 1 executes the halt instruction, the halt signal HALT is inverted to the low level. Furthermore, CP
The interrupt signal INTB output from the oscillation circuit 18 is used as a maskable interrupt for U1.

Further, the oscillation monitoring circuit 21 is the oscillation circuit 18
When the oscillation circuit 18 outputs the clock CK having a constant cycle, the high-level power saving signal SP is output to permit the power supply to the power supply line V2. On the contrary, when the operation of the oscillation circuit 18 is stopped, the power saving signal SP becomes low level after a predetermined time, and the power supply line V2
Power supply to the power supply is stopped.

FIG. 2 is a circuit diagram showing an example of the oscillation circuit 18 of FIG. A resistor R1 and a crystal oscillator XL are connected in parallel between one input terminal and an output terminal of the NAND element 35, each terminal is grounded via capacitors C1 and C2, and the other input of the NAND element 35 is input. Outputs a clock CK when is at a high level, and the NAND element 3
A crystal oscillator that stops oscillation when the input of 5 is low level is constructed. The resistor R and the capacitors C1 and C2
The value of is determined in consideration of the characteristics of the crystal oscillator XL and the stray capacitance of the circuit. Further, a ceramic oscillator or the like can be used instead of the crystal oscillator XL.

The halt signal HALT is input to the trigger terminal of the flip-flop 34 via the NOT element 33, and the inverting output terminal of the flip-flop 34 is NAND.
It is connected to the element 35. Also, the interrupt signal INTA
Is input to the NOR element 32 and the reset signal RESET is input.
Is input to the NOR element 32 via the NOT element 31,
The output of the NOR element 32 is connected to the clear terminal of the flip-flop 34. The data terminal and preset terminal of the flip-flop 34 are connected to the power supply line V1.

Further, in order to delay the timing of the interrupt request by a predetermined time, the shift register 36 having a 3-bit structure is used.
The interrupt signal INTA is input to the data terminal, the clock CK is input to the clock terminal, and the interrupt signal INTB is output from the inverting output terminal.

FIG. 3 is a timing chart showing the operation of the oscillation circuit 18. The halt signal H is generated during the normal operation of the CPU 1.
ALT is at a high level, and the crystal oscillator outputs a clock CK having a constant cycle and supplies it to the CPU 1 and the control circuit 4. Next, when the CPU 1 executes the halt instruction and the halt signal HALT goes from the high level to the low level at time t1, the inverted output of the flip-flop 34 goes to the low level, the crystal oscillator stops, and the clock CK maintains the high level. In this state, the CPU 1 shifts to the power save mode.

Next, at time t2, the restart signals B1 and B
When either of 2 becomes low level, interrupt signal INTA
Is inverted to a high level, the inverted output of the flip-flop 34 becomes a high level, the operation of the crystal oscillator is restarted, and the clock CK having a constant cycle is output. On the other hand, the interrupt signal I
NTA is also input to the shift register 36 and clock C
Serial transfer of 3 bits is performed by K, and is output to the CPU 1 as a negative logic interrupt signal INTB at time t3 when a predetermined time has elapsed. When the operation of CPU1 resumes,
The Holt signal HALT returns to high level. In this way, since the CPU 1 is interrupted after a time delay of 3 bits after the operation of the crystal oscillator is restarted, the operation of the CPU 1 is restarted after the operation of the crystal oscillator is stabilized, and the stable operation is realized.

FIG. 4A is a circuit diagram showing an example of the oscillation monitoring circuit 21, and FIG. 4B is a timing chart thereof. The oscillation monitoring circuit 21 is composed of a retrigger type multivibrator, and outputs a pulse having a constant time width Ta determined based on the time constants of the resistor R2 and the capacitor C3 with reference to the rising edge of the clock CK as an input signal. Further, when the clock CK rises within the period in which the pulse of the time width Ta is output, the time measurement of the time width Ta is started again. Therefore, when the clock CK having a cycle shorter than the time width Ta is continuously input, the power saving signal of a constant level is output. After that, when the oscillation circuit 18 is stopped and the clock CK is not output, the power saving signal SP becomes low level after the elapse of the time width Ta from the last rise.

FIG. 5 is a flowchart showing the operation. First, when the power source of the image forming apparatus is turned on, interruption is prohibited by masking in step a1, and the RAM 3, control circuit 4, interface 7, panel section 8 and control circuit 4 are initialized in step a2. In the next step a3, the drive circuit 5 and the image forming section 6 are operated via the control circuit 4 to perform an initial operation for initializing the print position, print conditions, etc., and the print standby state is set. When a print command from the external host device is received in this state, the print operation can be started.

Next, in step a4, a timer for measuring time is started, and in step a5 it is determined whether print data is input from the external host device.
If there is no data input, the process proceeds to step a11, and steps a5 and a11 are repeated until a fixed time elapses after the timer starts counting time.

On the other hand, if there is data input from the external host device in step a5, the process moves to step a6 to stop the timer operation, and in step a7 RAM
Document data is developed based on the received data stored in 3, and the drive circuit 5 and the image forming unit 6 are operated via the control circuit 4 to print on the recording medium. Step a8
In step a9, it is determined whether printing is completed.
The presence / absence of print data is determined by, and a series of operations is repeated until the printing of print data is completed. When there is no more data to be printed, the timer is restarted in step a10.

In this way, the fixed time is measured from the time when the initial operation or the last printing operation is completed, and it is monitored whether new print data is received during that period. If a certain time has passed since the print data was lost, step a
12, the timer operation is stopped, and step a1
The operation of the drive circuit 5 is stopped at 3, and the drive power supply 10
Power supply to the image forming unit 6 is stopped. Thus C
All energization of the R motor, PF motor, etc. is cut off, and relatively large power saving becomes possible at this stage.

At the next step a14, step a
After the interrupt prohibition set in 1 is released, the halt instruction is executed, and the power save mode is entered in step a15. At this time, the CPU 1 outputs the halt signal HALT, stops the operation of the oscillation circuit 18, and stops the clock CK. Further, the operation of the CPU 1 is stopped, the level changes of the address bus, the read and the write on the bus 9 are also eliminated, and the access operation to the ROM 2 and the RAM 3 is also stopped. R
A CMOS-IC can be used for the logic system such as the OM2, the RAM3, the control circuit 4, and the panel unit 8.
-IC has a characteristic that current consumption flows when the signal level is inverted. Therefore, if there is no change in the signal level of the bus 9, the power consumption of the logic system using the CMOS-IC can be significantly suppressed. In addition, CPU
When 1 is temporarily stopped, energization of the panel unit 8, for example, the display LED is also stopped.

Further, when the clock CK is stopped, the oscillation monitoring circuit 21 inverts the power saving signal SP to the low level after the passage of the time width Ta and instructs the power supply disconnecting circuit 12 to stop the power supply to the power supply line V2. . ROM
2, the consumption current of the RAM 3 and the control circuit 4 is completely stopped, so that the power saving effect is further improved.

When the power save mode is released, when the interface 7 receives data from the external host device or the operation switch of the panel section 8 is operated,
After the oscillation circuit 18 resumes operation and oscillation stabilizes, CP
The interrupt signal INTB is input to U1. Then CP
U1 returns from the power save mode to the normal operation mode and resumes the normal printing operation from step a1 in FIG.

When the state in which there is no data to be printed continues for a certain period of time, the CPU 1 shifts to the power save mode and stops the internal operation, so that the power saving control of the logic system becomes possible.

In the above description, an example of using a 3-bit configuration as the shift register 36 has been described. However, it is preferable to determine the number of bits and the clock cycle in consideration of the time during which the crystal oscillator stabilizes. Instead of the register 36, a delay circuit that delays the pulse signal for a predetermined time may be used.

Further, although the example in which the oscillation circuit 18 is provided outside the CPU 1 is shown, the oscillation circuit 18 may be built in the CPU 1.

Further, an example in which a retrigger type multivibrator is used as the oscillation monitoring circuit 21 has been shown, but any device capable of detecting the presence / absence of a clock having a constant cycle may be used.

Further, the power saving signal SP output from the oscillation monitoring circuit 21 can be used to stop the power supply to the drive power supply 10, the drive circuit 5, and the image forming section 6.

[0056]

As described above in detail, according to the present invention, the operation of the peripheral circuit is stopped together with the transition of the central processing unit to the suspend mode, so that a large power saving can be realized. Further, the central processing unit returns to the normal operation in response to an interrupt request from the interface unit or the panel unit, so that the printing operation can be promptly restarted.

Further, by stopping the operation of the clock generator in the suspend mode, the power consumption can be further suppressed. Furthermore, the power supply to the memory unit and the control unit is stopped by detecting that the operation of the clock generating unit is stopped, so that more effective power saving can be achieved.

Furthermore, since the return of the normal operation is performed after the operation of the clock generating section is sufficiently stabilized, the malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an oscillator circuit 18 of FIG.

FIG. 3 is a timing chart showing the operation of the oscillation circuit 18.

FIG. 4A is a circuit diagram showing an example of the oscillation monitoring circuit 21, and FIG. 4B is a timing diagram thereof.

FIG. 5 is a flowchart showing an operation of the image forming apparatus.

FIG. 6 is a block diagram showing an example of a conventional electrical configuration.

FIG. 7 is a flowchart showing the operation of FIG.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Control Circuit 5 Drive Circuit 6 Image Forming Section 7 Interface 8 Panel Section 9 Bus 10 Drive Power Supply 11 Logic Power Supply 12 Power Supply Disconnection Circuit 17 NAND Element 18 Oscillation Circuit 19 Reset Circuit 20 Backup Power Supply 21 Oscillation Monitoring Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display H04N 1/00 C

Claims (2)

[Claims] 1. A central processing unit for performing signal processing according to a program, a memory unit for storing a program and data, an interface unit for connecting to an external host device, and a signal input unit and a signal display unit. A panel section, an image forming section for forming an image on a recording medium, a control section for controlling the image forming section, a central processing section, a memory section, an interface section, a panel section and a control section are connected to each other. An image forming apparatus including a bus for controlling the operation of the central processing unit, a clock generating unit that generates a clock that determines the operation timing of the central processing unit, a power supply control unit that controls power supply to the memory unit and the control unit, and a clock generating unit. And an oscillation monitoring unit for monitoring the operation of, the central processing unit stops all the operations until the level of the interrupt signal changes. It has a suspend mode, and when the signal input from the external host device to the interface section is interrupted for a predetermined time, the central processing section shifts to the suspend mode, the operation of the clock generating section is stopped, and the oscillation monitoring section operates. The power supply control unit is instructed to stop the power supply to the memory unit and the control unit. On the other hand, when a signal is input from the interface unit or the panel unit, the operation of the clock generation unit is restarted and the memory unit is restarted. An image forming apparatus, wherein power supply to the control unit is restarted, the level of the interrupt signal is changed, and the central processing unit releases the temporary stop mode. 2. The image forming apparatus according to claim 1, wherein the level of the interrupt signal of the central processing unit is changed after a lapse of a predetermined time after the operation of the clock generating unit is restarted.