JPH08140256A - Open phase detecting device - Google Patents

Abstract

PURPOSE: To prevent wrongly detecting an open phase even when distortion is generated in a load current. CONSTITUTION: A device comprises current detecting means CT1, CT2 for detecting a current flowing through a three-phase cable 2, rectifying means S1 for rectifying the output detected by the current detecting means CT1, CT2, amplifier means 31 for amplifying the output of the rectifying means S1, reference voltage generating means for obtaining reference voltage for detecting an open phase of the three-phase cable 2 by using an output of the amplifier means 31 and a comparator means 37 for comparing an output voltage value of the amplifier means 31 with the reference voltage value of the reference voltage generating means. The device is provided with an arithmetic means for judging that the phase of the three-phase cable 2 is open when the reference voltage value is larger than the output voltage value continuously for a predetermined time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a phase loss detecting device for accurately detecting a phase loss in a three-phase electric circuit to which an electric motor or the like is connected.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional open phase detecting device disclosed in Japanese Patent Publication No. 4-67425. CT1, CT2, C
T3 is a current detecting means for detecting a current in the three-phase electric circuit 2, and 1 is a three-phase full-wave rectifying means for inputting each output signal of the current detecting means and outputting a rectified signal 1a subjected to three-phase full-wave rectification,
3 is a peak value detecting means for outputting a peak value signal 3a according to the peak value of the rectified signal 1a, 4 is an average value detecting means for outputting an average value signal 4a according to the average value of the rectified signal 1a, and 6 is a peak value. An arithmetic means for performing an arithmetic operation using the signal 3a and the respective magnitudes A and B of the average value signal 4a to output a pulsation rate signal 6a corresponding to the pulsation rate R of the rectified signal 1a, and 12 is a peak value signal 3a inputted. A first determination means for comparing the magnitude of the input signal with the first set current value I1 of the internal organs and outputting a first determination signal 12a if A ≧ I1, 13 is the peak value signal 3a input and the input The magnitude of the signal is A, and the second set current value I2 is built-in.
In comparison with A <I2, the 21st determination signal 13a is output, and when A ≧ I2, the 22nd determination signal 13b is output. The second determination means 10 receives the reset signal 14a or the time is up. When the signal 10a is output or when it is reset to the initial state, the clocking operation is stopped, and
When the judgment signal 12a is input, the time counting means starts the time counting operation and outputs the time-up signal 10a after the lapse of the set time.

Reference numeral 14 is provided with a first reference value R1 and a second reference value R2. When the 21st determination signal 13a is input, the value R of the pulsation rate signal 6a is compared with the first reference value R1. R
If R <R1, the reset signal 14a is output. If the 22nd determination signal 13b is input, the reset signal 14a is compared, and if R <R2, the reset signal 14a is output. , 15 is a control means for outputting an operation start signal 15a when the power is turned on, and 16 is a drive signal 16a with a cycle ΔT when the operation start signal 15a is input.
And the signal generation means for outputting the phase loss detecting device.

The operation of the conventional open-phase detecting device configured as described above will be described. Now, assuming that the magnitude of A becomes I1 ≦ A <I2 and R ≧ R1 due to the occurrence of the open-phase condition in the electric circuit 2, the signal 12a is output, so that the timing means 10 is provided.
Starts the time counting operation, while the determination means 14 determines the reference value R1.
However, the reset signal 14a is not output from the means 14 because R ≧ R1. Then, the pulsation rate R is (A-
B) / A, and when the pulsation rate R is larger than the first reference value R1 and the second reference value R2, the counting means 10 counts up and outputs the open phase signal.

[0005]

In the conventional open-phase detecting apparatus, when a distorted wave is generated as shown in FIG. 8, a distorted wave is generated if the peak value Au of the distorted waveform and the peak value An of the normal waveform are given. The pulsation rate during the operation is Ru = (Au-B) / A
It becomes u, and the pulsation rate under normal conditions is Rn = (An-B)
Since / An and Au> An, most of them are Ru.
> Rn and the pulsation rate R using the peak value Au of the distorted waveform
When calculating, there is a case where the open phase is erroneously detected.

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to provide a phase loss detecting device in which it is difficult to erroneously detect a phase loss even when a load current is distorted. .

Another object of the present invention is to provide an open phase detecting device in which an unbalanced load current flows and it is difficult to detect the open phase by mistake.

[0008]

According to a first aspect of the present invention, there is provided an open-phase detecting device, wherein current detecting means for detecting a current in a three-phase electric circuit, rectifying means for rectifying the output detected by the current detecting means, and Amplifying means for amplifying the output of the rectifying means, reference voltage generating means for obtaining a reference voltage for determining the open phase of the three-phase electric circuit by using the output of the amplifying means, output voltage value of the amplifying means and the reference voltage Comparing means for comparing the reference voltage values of the generating means, and if the reference voltage value is continuously larger than the output voltage value for a predetermined time, the calculating means for judging that the three-phase electric circuit is open phase. It is characterized by that.

According to another aspect of the present invention, there is provided an open-phase detecting device, which comprises a judgment voltage generating means for obtaining a judgment voltage for judging the degree of unbalance of the three-phase electric circuit by using the maximum value and the minimum value of the output voltage of the amplifying means. An unbalance comparison means for comparing the judgment voltage value of the judgment voltage generating means with the output voltage value of the amplifying means, and the three-phase depending on whether the judgment voltage value is larger than the output voltage value for a predetermined time. And a reference voltage changing means for changing the reference voltage value for determining the open phase of the electric circuit.

According to another aspect of the present invention, there is provided an open-phase detecting device characterized in that the calculating means sets a predetermined time to be equal to or shorter than an overcurrent withstanding time of the load.

[0011]

According to the open-phase detector of the first aspect, the current detecting means detects the current in the three-phase electric circuit, the rectifying means rectifies the output of the current detecting means, and the amplifying means detects the output of the rectifying means. Amplification, the reference voltage generating means inputs the output voltage of the amplifier to generate a reference voltage for determining the open phase of the three-phase circuit, and the comparing means outputs the output voltage value of the amplifying means and the reference voltage generating means. The reference voltage values are compared with each other, and the arithmetic means determines that the three-phase electric circuit is out of phase when the reference voltage value is continuously larger than the output voltage value for a predetermined time.

According to the open-phase detecting device of the second aspect, the judgment voltage generating means generates the judgment voltage for judging the degree of unbalance of the three-phase electric circuit by using the maximum value and the minimum value of the output voltage, The unbalance comparison means compares the determination voltage value of the determination voltage generating means with the output voltage value of the computing means, and the reference voltage changing means determines whether the determination voltage value is larger than the output voltage value by a predetermined time. The reference voltage value for determining the open phase is changed by.

According to the open-phase detecting device of the third aspect, the calculating means determines that the phase is open when the predetermined time becomes equal to or less than the overcurrent withstanding time of the load.

[0014]

【Example】

Example 1. FIG. 1 shows an open-phase detecting device that is an embodiment of the present invention.
Shown in In the figure, the same reference numerals as those used in the related art indicate the same or corresponding parts. 21 is a three-phase AC power supply (hereinafter referred to as "power supply"), 2
Reference numeral 2 is a motor 22 connected to a power source 21. CT
1, CT2 is a current transformer as a current detecting means for detecting a current in the three-phase electric circuit 2, S1 is a three-phase full-wave rectifier as a rectifying means for rectifying the outputs of the current transformers CT1, CT2, 30
Is a resistor that limits the input current of the operational amplifier 13, 31 is an operational amplifier as an amplifying means for amplifying the voltage rectified by the three-phase full-wave rectifier S1, and 32 and 33 are resistors that determine the gain G of the operational amplifier. Resistance value R12, R13
Have. The gain G is R12 / R13 + 1. Reference numeral 35 denotes a microcomputer (hereinafter referred to as "microcomputer"), and the microcomputer 35 inputs the output voltage E1 of the operational amplifier 31 by an arithmetic unit and performs arithmetic operations and the like. Three
Reference numeral 7 is a comparator as a comparing means or an unbalance comparing means for comparing the reference voltage value or the judgment voltage value output from the analog output terminal DA1 of the microcomputer 35 with the output voltage E1 from the operational amplifier 31, and 38 is a capacitor. . FIG. 2 is a waveform diagram of each part of the phase loss detection device. In FIG. 2, E1 indicates the output voltage of the operational amplifier, and E3 is the reference voltage for determining the open phase.

Next, the operation of the open phase detector will be described with reference to FIG.
This will be described with reference to the flowchart in FIG. In addition, when the following flowchart is executed, the reference voltage generating means and the arithmetic means are executed. First, the number of inputs of the output voltage E1 of the operational amplifier 31 for calculating the reference voltage E3 to the microcomputer 35 in one cycle, that is, the sampling number CN is set to eight. A flag 0 is set in the register SP that determines the open phase mode (hereinafter referred to as SP_F = 0).
When the phase loss mode reaches the set number of times, it is determined that there is a phase loss, and 30 is set in the phase loss counter PH. From this, when the open phase mode reaches 30 times, it is determined to be open phase. The initial setting of the reference voltage E3 for determining the phase loss is set to 0.4En. En is the output voltage of the operational amplifier 31 when the rated current flows through the motor 2. or,
The period of the open phase mode is set by the timer FM, and this set value is set to 0.1 Sec. Timer S for sampling period
It is set by T, and this set value is set to 1 msec when the power supply frequency is 60 HZ (step 101). Here, the product of the sampling cycle ST of the output voltage E1 and the number of times of sampling CN, that is, the total sampling cycle of one cycle of the open-phase mode is set to 1 msec × 8 = 8 msec in order to keep it within the half cycle of the power supply frequency. .

Next, the timers of the timer FM and the timer ST are started (step 102). It is determined whether or not the timer FM is up (step 10
3) If the time is not up, the judgment is continued. If the time is up, it is determined whether or not the timer TM2 is up (step 104). If the time is not up, the determination is continued. If the time is up, the output voltage E1 of the operational amplifier 31 is input to the microcomputer 35 (step 105). It is determined whether the phase loss mode is the SP_F flag by 1 or not (step 120). Since SP_F is initially set to 0, the reference voltage E3 is output to one of the input sides of the comparator 37 (step 121). ), The reference voltage E3 and the output voltage E1 are compared by the comparator 37 (step 122), and E3> E
If it is 1, it is determined to be the open phase mode and SP_F is set to 1. At the same time, the phase loss counter PH is decremented by 1 (step 123), the sampling number CN is decremented by 1 (step 125), it is determined whether or not the CN is zero (step 126), and if it is not zero, the phase loss mode continues. Therefore, steps 104, 105, 125 and 126 are sequentially executed to input the output voltage E1 to the microcomputer 35 eight times.
Therefore, in step 126, the sampling count CN
Is zero. On the other hand, if E3> E1 is not set, 30 is set to the open phase counter PH (step 124). As a result, the value of the open-phase counter PH becomes the same as the initial setting.

When the sampling number CN becomes zero in step 126, the number CN is newly set to 8 and the flag of SP_F is set to 0 to reset the open phase mode. An average voltage Eave is obtained by averaging the integrated output voltage E1 (step 130). Reference voltage E
3 is obtained by 0.4Eave and the value is set (step 131). The set value becomes the new reference voltage E3. It is determined whether the open phase counter PH is zero (step 150). If it is not zero, step 103
~ 105 are executed and SP_F is zero, so it is determined that the phase is not the open phase mode (step 120), and step 12
If steps 1 and 122 are executed and E3> E1 is continued, SP_F is set to 1 in step 123, the open phase counter PH is decremented by 1, and steps 125, 126, and 10 are executed.
4 and 105 are sequentially executed, and when the sampling number CN becomes zero, steps 130 and 131 are executed. The open phase mode is repeated 30 times, the open phase counter PH becomes zero, and the open phase counter PH is set to 30 (step 1
51), the open phase signal is output (step 152). Next, it is determined whether the FM timer is up (step 103). That is, by detecting the open-phase mode, the output voltage E1 is set to 1 ms each time 0.1 sec elapses.
For each ec, the output voltage E1 input to the microcomputer eight times is set as an averaged reference voltage E3, and the reference voltage E3 and the output voltage E3
1 is compared with each other, and if the open phase mode continues 30 times, it is determined to be open phase.

In the above embodiment, the open phase detection time is set to 3 seconds, but it is not limited to this time. The detection time is generally set shorter than the overload withstanding time of the device such as the motor 22. In the above-described embodiment, the reference voltage E3 is set by inputting the output voltage E1 every 0.1 sec, but the load current of the motor 22 does not change so much in the open phase state. .1 Sec
It is not always necessary to reset every time.

Example 2. In the first embodiment, the average output voltage Eave changes even when the current flowing through the motor 22 is the same unbalance rate, so the reference voltage E3 also changes. Therefore, the open phase of the three-phase electric circuit 2 cannot be detected with a predetermined detection accuracy. The second embodiment of the present invention improves this point. The value of the reference voltage E3 is changed by detecting the degree of imbalance of each phase. When an unbalanced current flows in the two phases of the motor 22 in FIG. 4, assuming that the unbalanced rate is 45%, the current peak values of the respective phases are IRe, ISe, and ITe according to a known unbalanced rate calculation table. IRe: ISE: ITe = 1:
It becomes 0.6: 0.6. On the other hand, when an unbalanced current flows in one phase of the motor 22 in FIG. 5, the current peak value of each phase becomes IRe: ISE: ITe = 1: 1: 0.45.

Now, when one phase is unbalanced, assuming that the minimum phase voltage peak value of the output voltage E1 is E11m, E11m =
It becomes K1 and Eave. When the two phases are unbalanced, E12m = K2 · Eave, where E12m is the peak value of the minimum phase voltage of the output voltage E1. Note that K1, K
2 is a coefficient for changing the reference voltage. If the coefficients K1 and K2 are set so as to satisfy the above equation, the open phase can be detected at the desired unbalance rate without erroneous detection.

Next, the operation of the open phase detecting device will be described with reference to the flowchart of FIG. In FIG. 6, steps 102 to 105, steps 120 to 126, and steps 150 to 152 are the same as those in the first embodiment, and therefore description thereof will be omitted. When the following flowchart is executed, the judgment voltage generating means and the reference voltage changing means are executed. First, as in the first embodiment, the sampling number CN is set to 8 and the open phase counter PH is set to 30. Next, the reference voltage E3 is K · En, where K is a voltage setting ratio.
Also, input coefficient K1 and coefficient K2, and set K to (K1 + K
2) / 2 is calculated and set by the unbalance counter UC
Set N to 8. , En is set as the maximum value Emax of E1 and the minimum voltage value Emin of E1, and KEn is set as the determination voltage EB for determining the degree of unbalance (step 101a).

The output voltage E1 is compared with the judgment voltage EB (step 106). If E1 <EB, the unbalance counter UCN is set to UCN = UCN-1 (step 10).
7) The output voltage E1 is compared with the maximum value Emax of the output voltage (step 108). If E1 <EB is not satisfied, step 108 is directly executed. As a result of comparison, E1> E
If it is max, the output voltage E1 is set to Emax (step 109). On the other hand, if E1> Emax is not satisfied, the output voltage E1 is compared with the minimum value Emin of the output voltage (step 110). If E1 <Emin, E1 is set to E1min (step 11
1). On the other hand, if E1 <Emin is not satisfied, step 11
0 is not executed.

Next, in step 130a, the sampling number CN is set to 8 and SP_F is set to zero. Further, the average voltage Eave is calculated, and the determination voltage EB is calculated as (E
(max + Emin) / 2, and set. It is determined whether or not the unbalance counter UCN <4 (step 1
40), if UCN <4, it is assumed that the one-phase current of the load current is large and the other two-phase currents are small, which is an unbalanced current.
= K1 (step 141). If UCN <4, it is assumed that the two-phase current of the load current is large and the other one-phase currents are small, and K = K2 (step 1).
42). , K · Eave is calculated and set as the reference voltage E3 (step 143). By changing K according to the imbalance of the load current as in the above embodiment, the open phase detection can be detected with high sensitivity.

Example 3. In this embodiment, the quick response of phase loss detection is improved. This embodiment will be described with reference to the flowchart of FIG. Steps 102-105
And steps 120 to 126 and steps 150 to 15
Since 2 is the same as or equivalent to that of the first embodiment, the description thereof is omitted.

First, the sampling number CN is set to 7. Set SP_F = 0 and set the missing phase counter PH to 30.
Set. The initial setting of the reference voltage E3 for determining the phase loss is set to 0.4En. Further, the period of the open phase mode is set by the timer FM, and the set value is set to 0.1 Sec.
The sampling period is set by the timer ST, and this set value is set to 0.4 msec when the power supply frequency is 60 HZ (step 101b). In step 130b, the sampling count CN is set to 7, and SP_F = 0
Is set and the average voltage Eave is calculated. Next, the average voltage Eave is compared with the previous average voltage Eave-1 (step 145), and if Eave-1 <Eave, E3 is calculated by 0.4Eave and set (step 14).
6), execute step 150. On the other hand, Eave-1 <
If it is not Eave, step 150 is directly executed.

[0026]

According to the open phase detecting device of the first aspect,
Current detecting means for detecting a current in the three-phase electric circuit, rectifying means for rectifying the output detected by the current detecting means, amplifying means for amplifying the output of the rectifying means, and output using the amplifying means Reference voltage generating means for obtaining a reference voltage for determining the open phase of the three-phase circuit, and comparison means for comparing the output voltage value of the amplifying means and the reference voltage value of the reference voltage generating means, the reference voltage value is If the output voltage value is continuously larger than the output voltage value for a predetermined period of time, the three-phase electric circuit is provided with a calculating unit that determines that there is an open phase. There is an effect of obtaining a phase loss detecting device that can prevent it.

According to the open-phase detecting device of the second aspect, the determination voltage generation for obtaining the determination voltage for determining the degree of unbalance of the three-phase electric circuit by using the maximum value and the minimum value of the output voltage of the amplifying means. Means, and an unbalance comparison means for comparing the judgment voltage value of the judgment voltage generating means with the output voltage value of the amplifying means,
Since the reference voltage changing means for changing the reference voltage value for determining the open phase of the three-phase electric circuit depending on whether the determination voltage value is larger than the output voltage value by a predetermined time,
Even if the degree of unbalance of each phase is different, there is an effect of obtaining a phase loss detecting device capable of preventing the phase loss detection.

According to the open-phase detecting device of the third aspect, the calculating means sets the predetermined time to be equal to or shorter than the overcurrent withstanding time of the load. Therefore, the open-phase detecting device can surely protect the load equipment from the open phase. There is an effect to obtain.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a phase loss detection device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a load current according to an embodiment of the present invention.

FIG. 3 is a flow chart showing the operation of the open-phase detection device according to the embodiment of the present invention.

FIG. 4 is a waveform diagram of a load current according to another embodiment of the present invention.

FIG. 5 is a waveform diagram of a load current according to another embodiment of the present invention.

FIG. 6 is a flow chart showing an operation of the open-phase detector according to another embodiment of the present invention.

FIG. 7 is a flow chart showing an operation of a phase loss detecting device according to another embodiment of the present invention.

FIG. 8 is a configuration diagram showing a conventional phase loss detection device.

FIG. 9 is a distortion waveform diagram of a load current by a conventional phase loss detection device.

[Explanation of symbols]

 31 amplification means, 37 comparison means

Claims (3)

[Claims] 1. A current detecting means for detecting a current in a three-phase electric circuit, a rectifying means for rectifying an output detected by the current detecting means, an amplifying means for amplifying an output of the rectifying means, and an amplifying means. A reference voltage generating means for obtaining a reference voltage for determining the open phase of the three-phase electric circuit using the output; and a comparing means for comparing the output voltage value of the amplifying means and the reference voltage value of the reference voltage generating means, A phase loss detecting device comprising a calculating means for determining that the three-phase electric circuit is out of phase when the reference voltage value is continuously higher than the output voltage value for a predetermined time. 2. A judgment voltage generation means for obtaining a judgment voltage for judging the degree of unbalance of the three-phase electric circuit by using the maximum value and the minimum value of the output voltage of the amplification means, and the judgment voltage of the judgment voltage generation means. Value and the output voltage value of the amplifying means, and an unbalanced comparing means, and a reference voltage for determining the open phase of the three-phase electric circuit depending on whether the determination voltage value is larger than the output voltage value by a predetermined time. The phase loss detecting device according to claim 1, further comprising a reference voltage changing unit that changes a value. 3. The phase loss detecting device according to claim 1, wherein the arithmetic means sets a predetermined time so as to be equal to or less than an overcurrent withstanding time of the load.