JPH08139284A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor device and a method for manufacturing the same in which III-V compound semiconductor operated at a high speed is used with small gate leakage current. CONSTITUTION: As a p-type transistor P, a channel layer 2P, a hole supply layer 4P, a III-V compound semiconductor layer 5P in which a composition ratio is so deviation that V group atoms are increased from a stoichiometric ratio, and a p-type contact layer 6P are formed on a III-V compound semiconductor substrate, a gate electrode 7P is Schottky-junctioned on the layer 5P, and a source electrode 8P and a drain electrode 9P are brought into ohmic contact with a p-type contact layer 6P. As an n-type transistor N, a channel layer 2N, an electron supply layer 4N, a III-V compound semiconductor 5N in which a composition ratio is so deviated that III group atoms are increased from a stoichiometric ratio, and an n-type contact layer 6N are formed on a III-V compound semiconductor substrate, a gate electrode 7N is Schottky-junctioned on the layer 5N, and a source electrode 8N and a drain electrode 9N are brought into ohmic contact with the layer 6N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a compound semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In order to meet the demand for higher speed and lower power consumption of core systems that support today's information society, electronic devices are required to have higher speed and lower power consumption. Therefore, low power consumption has been achieved by the CMOS circuit of silicon, but the demand for further low power consumption and high speed is unavoidable. Therefore, it is attempted to meet this demand by further miniaturization, but naturally there is a limit. Therefore, an attempt is made to satisfy this requirement by using a III-V group compound semiconductor having physical properties more suitable for high speed than silicon.

[0003]

[Problems to be Solved by the Invention] However, III-
Since a conventional transistor using a group V compound semiconductor basically uses a Schottky junction gate electrode,
The rising voltage in the forward direction is lower than 1V, and the power supply voltage of the electronic device circuit cannot be set higher than 1V.

For this reason, there is a problem that a large current cannot be taken and the operation speed does not increase. Further, if the power supply voltage is set to 1 V or higher, there is a problem that the power consumption cannot be reduced due to the leakage current from the gate electrode. An object of the present invention is to provide a semiconductor device using a III-V group compound semiconductor which operates at high speed with a small gate leakage current, and a manufacturing method thereof.

[0005]

Means for Solving the Problems The present inventors have
Uses Group V compound semiconductors to reduce gate leakage current
In order to realize a semiconductor device that operates at high speed, III-V
As a result of investigating the characteristics of group compound semiconductors, it is possible to change the Schottky barrier height of the GaAs layer grown at low temperature by the MBE method by controlling the deviation from the stoichiometric ratio (S.Fuji).
eda, Appl. Phys. Lett., 61, 288 (1992)). In addition, since the GaAs layer grown at low temperature has high resistance,
It is used as a buffer layer in the device structure using epitaxial system and is effective in reducing the side gate effect (FWSmith et al., IEEE Electron Dev. Lett., 9,
77 (1988)).

In the case of a heterojunction transistor, the gate leakage current depends on the height of the Schottky barrier of the gate electrode and the energy difference ΔEc of the conduction band and the energy difference ΔEv of the valence band at the heterojunction. Therefore,
The composition ratio of the compound semiconductor layer that forms a Schottky junction with the gate electrode is shifted from the stoichiometric ratio to increase the height of the Schottky barrier, and the compound semiconductor having a larger band gap between the gate electrode and the channel layer than the channel layer. It was thought that the gate leakage current can be suppressed by inserting the layer. Further, by adopting a device structure that does not increase the source parasitic resistance even if such a compound semiconductor layer has high resistance, the gate leakage current is small,
Moreover, the inventors have come up with a semiconductor device using a III-V group compound semiconductor that operates at high speed.

The principle of the present invention will be described with reference to FIG. In the semiconductor device according to the present invention, as shown in FIG. 1A, p is formed in the region on the left side of the III-V compound semiconductor substrate 1.
The type transistor P is formed, and the n-type transistor N is formed in the right region. II as the p-type transistor P
A channel layer 2P is provided on the IV compound semiconductor substrate, and a hole supply layer 4P is provided on the channel layer 2P. Holes are supplied from the hole supply layer 4P to the channel layer 2P to form the hole channel 3P. Hole supply layer 4
On P, a compound semiconductor layer 5P made of a III-V group compound semiconductor whose composition ratio is deviated from the stoichiometric ratio (stoichiometry) so that the number of V group atoms is large is formed in the center, and p is formed on the left and right sides. The mold contact layer 6P is formed. The gate electrode 7P is Schottky-junctioned on the compound semiconductor layer 5P, and the source electrode 8P and the drain electrode 9P are in ohmic contact on the p-type contact layer 6P.

In the case of this p-type transistor P, the composition ratio of the compound semiconductor layer 5P deviates from the stoichiometric ratio (stoichiometry) so that the number of group V atoms increases, so that the Schottky barrier of the gate electrode 7P is Higher and less gate leakage current. Source electrode 8P and drain electrode 9P
Has ohmic contact with the p-type contact layer 6P, the source parasitic resistance does not increase.

As the n-type transistor N, a channel layer 2N is provided on the III-V group compound semiconductor substrate, and an electron supply layer 4N is provided on the channel layer 2N. Electrons are supplied from the electron supply layer 4N to the channel layer 2N to form an electron channel 3N. On the electron supply layer 4N,
A compound semiconductor layer 5N made of a group III-V compound semiconductor is formed in the center, in which the composition ratio is deviated from the stoichiometric ratio (stoichiometry) so that the number of group III atoms is increased.
The mold contact layer 6N is formed. A gate electrode 7N is Schottky-junctioned on the compound semiconductor layer 5N,
The source electrode 8N and the drain electrode 9N are in ohmic contact with each other on the mold contact layer 6N.

In the case of this n-type transistor N, the compound semiconductor layer 5N has a stoichiometry ratio of III.
Since the composition ratio is shifted such that the number of group atoms is large, the Schottky barrier of the gate electrode 7N is high and the gate leakage current is small. Source electrode 8N and drain electrode 9
Since N is in ohmic contact with the p-type contact layer 6N, the source parasitic resistance does not increase.

The gate electrode 7P of the p-type transistor P and n
P-type transistor N is commonly connected to the gate electrode 7N, and p
The drain electrode 9P of the n-type transistor P and the drain electrode 9N of the n-type transistor N are commonly connected, the source electrode 8P of the p-type transistor P is connected to the power supply VDD, and the source electrode 8N of the n-type transistor N is connected to the power supply VSS. As a result, as shown in FIG. 1B, the p-type transistor P
With the n-type transistor N, a low power consumption complementary transistor circuit can be realized.

Therefore, an object of the present invention is to provide a channel layer in which a channel through which charged particles move is formed, a charged particle supply layer for supplying charged particles to the channel layer, and a band gap smaller than that of the charged particle supply layer. It is a small III-V compound semiconductor, and the stoichiometric ratio of the III-V compound semiconductor is used to increase the Schottky barrier height.
It is achieved by a semiconductor device comprising a compound semiconductor layer whose composition ratio is shifted so that the number of group III atoms or group V atoms is large, and a gate electrode which is Schottky-junctioned to the compound semiconductor layer.

In the above semiconductor device, the charged particles are electrons, and the compound semiconductor layer is formed of the III-
It is desirable that the composition ratio deviates from the stoichiometric ratio of the group V compound semiconductor so that the number of group III atoms is large. In the above semiconductor device, the charged particles are holes, and the composition ratio of the compound semiconductor layer is deviated from the stoichiometric ratio of the III-V compound semiconductor so that the group V atoms are increased. Is desirable.

In the semiconductor device described above, it is desirable that a second compound semiconductor layer having the same conductivity type as that of the charged particle supply layer is inserted between the charged particle supply layer and the compound semiconductor layer. The above object is to provide a channel layer in which a channel through which charged particles move is formed, a non-doped semiconductor layer having a band gap larger than that of the channel layer, and a III-V band gap smaller than that of the non-doped semiconductor layer.
A group III compound semiconductor, in which the composition ratio deviates from the stoichiometric ratio of the group III-V compound semiconductor such that the group III atom or group V atom increases so that the Schottky barrier height increases. A semiconductor device having a layer, a gate electrode Schottky-junctioned to the compound semiconductor layer, and an impurity-doped source region and a drain region formed below the region sandwiching the gate electrode. To be achieved.

In the above-mentioned semiconductor device, the charged particles are electrons, and the compound semiconductor layer is the III-
It is preferable that the composition ratio deviates from the stoichiometric ratio of the group V compound semiconductor so that the number of group III atoms increases, and the source region and the drain region are n-type impurity regions. In the above-described semiconductor device, the charged particles are holes, and the compound semiconductor layer has a composition ratio deviated from the stoichiometric ratio of the III-V group compound semiconductor so that the group V atoms increase. The source region and the drain region are preferably p-type impurity regions.

The above object is provided with an n-type transistor formed of the semiconductor device described above and a p-type transistor formed of the semiconductor device described above, and the gate electrode of the p-type transistor and the gate electrode of the n-type transistor are commonly connected. And a drain of the p-type transistor and a drain of the n-type transistor are commonly connected to each other.

The above object is to form a channel layer in which a channel through which charged particles move is formed, and to form a charged particle supply layer for supplying charged particles to the channel layer on the channel layer. On the charged particle supply layer,
Forming a compound semiconductor layer having a composition ratio different from the stoichiometric ratio of the III-V group compound semiconductor under a predetermined growth condition such that the group III atom or the group V atom is increased; And a step of forming a gate electrode in the semiconductor device.

The above object is to form a channel layer in which a channel for moving charged particles is formed, to form a non-doped semiconductor layer having a bandgap larger than that of the channel layer on the channel layer, On the non-doped semiconductor layer, under the predetermined growth conditions, the III-V
Forming a compound semiconductor layer having a composition ratio different from the stoichiometric ratio of the group compound semiconductor such that the number of group III atoms or group V atoms is large; forming a gate electrode on the compound semiconductor layer; And a step of forming a source region and a drain region below the region sandwiching the gate electrode by adding an impurity using the gate electrode as a mask.

In the method of manufacturing a semiconductor device described above,
The predetermined growth condition is to control the molecular doses of the group III atoms and the group V atoms so that the group III atoms or the group V atoms can be effectively used.
It is desirable to increase the number of group atoms. In the above-described method for manufacturing a semiconductor device, it is desirable that the predetermined growth condition effectively increase the number of group III atoms or group V atoms by controlling the growth temperature.

In the method of manufacturing a semiconductor device described above,
As the predetermined growth condition, it is desirable to effectively increase the number of group III atoms or group V atoms by ion-implanting group III atoms or group V atoms after growing the group III-V compound semiconductor layer. In the method for manufacturing a semiconductor device described above,
Forming a second compound semiconductor layer subsequent to the step of forming the charged particle supply layer or the non-doped semiconductor layer,
It is desirable to subsequently form the compound semiconductor layer.

In the method of manufacturing a semiconductor device described above,
A step of forming a contact layer on the compound semiconductor layer; and a step of recess etching a gate electrode formation region of the contact layer to expose the compound semiconductor layer, wherein the gate electrode is exposed. It is desirable to form it on the compound semiconductor layer. In the method for manufacturing a semiconductor device described above, a step of forming a contact layer on the charged particle supply layer or the non-doped semiconductor layer, and recess etching the gate electrode formation region of the contact layer, the charged particle supply layer or And a step of exposing the non-doped semiconductor layer, wherein the compound semiconductor layer is formed on the exposed charged particle supply layer or the non-doped semiconductor layer.

In the method of manufacturing a semiconductor device described above,
Patterning the compound semiconductor layer so that only the gate electrode formation region remains, forming a contact layer on the compound semiconductor layer and the charged particle supply layer or the non-doped semiconductor layer, and the gate of the contact layer A step of recess etching the electrode formation region to expose the compound semiconductor layer, and the gate electrode is preferably formed on the exposed compound semiconductor layer.

[0023]

According to the present invention, a channel layer in which a channel through which charged particles move is formed, a charged particle supply layer for supplying charged particles to the channel layer, and a band gap smaller than the charged particle supply layer III A group V compound semiconductor, wherein the Schottky barrier height is increased.
A compound semiconductor layer having a composition ratio different from the stoichiometric ratio of the III-V compound semiconductor such that the number of group III atoms or group V atoms is increased, and a gate electrode which is Schottky-junctioned to the compound semiconductor layer are provided. Therefore, the forward rising voltage is large, the gate leakage current is small, and high-speed operation is possible.

In the above-mentioned semiconductor device, if the charged particles are electrons and the composition ratio of the compound semiconductor layer is varied so that the group III atoms are increased from the stoichiometric ratio of the group III-V compound semiconductor, the gate leakage current is reduced. Thus, an n-type transistor that operates at high speed can be realized. In the above-mentioned semiconductor device, when the charged particles are used as holes and the composition ratio of the compound semiconductor layer is changed so that the group V atoms are increased from the stoichiometric ratio of the III-V group compound semiconductor, the gate leakage current is reduced and the high speed is achieved. It is possible to realize a p-type transistor that operates in.

In the semiconductor device described above, if a second compound semiconductor layer having the same conductivity type as the charged particle supply layer is inserted between the charged particle supply layer and the compound semiconductor layer, the charged particle supply layer to the compound semiconductor layer can be obtained. It is possible to grow continuously, and the interface of the compound semiconductor layer becomes good. According to the present invention, a channel layer in which a channel through which charged particles move is formed, a non-doped semiconductor layer having a band gap larger than that of the channel layer, and a group III-V compound semiconductor having a band gap smaller than that of the non-doped semiconductor layer. And a compound semiconductor layer whose composition ratio is deviated from the stoichiometric ratio of the III-V compound semiconductor so that the number of group III atoms or group V atoms is increased so as to increase the Schottky barrier height. A gate electrode Schottky-junctioned to the compound semiconductor layer,
Since the source region and the drain region added with impurities are formed below the region sandwiching the gate electrode,
The rising voltage in the forward direction is large, the gate leakage current is small, and high-speed operation is possible.

In the semiconductor device described above, the charged particles are electrons, and the composition ratio of the compound semiconductor layer is shifted from the stoichiometric ratio of the III-V group compound semiconductor so that the group III atoms are increased, and the source region and the drain region are formed. By using the n-type impurity region, it is possible to realize an n-type transistor that operates at high speed with a small gate leakage current. In the above-described semiconductor device, charged particles are used as holes, the composition ratio of the compound semiconductor layer is shifted from the stoichiometric ratio of the III-V group compound semiconductor so that the group V atoms are increased, and the source region and the drain region are p-type. If the impurity region is used, an n-type transistor that operates at high speed with a small gate leakage current can be realized.

An n-type transistor including the above-described semiconductor device and a p-type transistor including the above-described semiconductor device are provided, and the gate electrode of the p-type transistor and the gate electrode of the n-type transistor are commonly connected to each other. By commonly connecting the drain and the drain of the n-type transistor, a low power consumption complementary transistor circuit can be realized.

According to the present invention, a step of forming a channel layer in which a channel through which charged particles move is formed, and a step of forming a charged particle supply layer for supplying charged particles to the channel layer on the channel layer. And a compound semiconductor layer having a composition ratio deviated from the stoichiometric ratio of the group III-V compound semiconductor such that the number of group III atoms or group V atoms is increased on the charged particle supply layer under predetermined growth conditions. Since the step of forming and the step of forming the gate electrode on the compound semiconductor layer are included, it is possible to manufacture a semiconductor device that has a large forward rising voltage, a small gate leakage current, and operates at high speed.

According to the present invention, a step of forming a channel layer in which a channel through which charged particles move is formed, and a step of forming a non-doped semiconductor layer having a band gap larger than that of the channel layer on the channel layer. , On the non-doped semiconductor layer, under certain growth conditions, the III
-From the stoichiometric ratio of group V compound semiconductor, group III atom or V
Forming a compound semiconductor layer having a composition ratio shifted so that the number of group atoms increases, forming a gate electrode on the compound semiconductor layer, and adding an impurity using the gate electrode as a mask Since it has a step of forming a source region and a drain region below a region sandwiching electrodes, a semiconductor device which has a large forward rising voltage, a small gate leakage current, and operates at high speed can be manufactured.

In the method of manufacturing a semiconductor device described above,
By controlling the molecular dose of group III atoms and group V atoms as a predetermined growth condition, group III atoms or group V atoms can be effectively controlled.
Group III atoms may be increased, group III atoms or group V atoms may be effectively increased by controlling the growth temperature, or group III atoms may be added after the group III-V compound semiconductor layer is grown. Or by implanting group V atoms by ion implantation, II
The number of group I atoms or group V atoms may be increased.

In the method of manufacturing a semiconductor device described above,
If the second compound semiconductor layer is formed subsequent to the step of forming the charged particle supply layer or the non-doped semiconductor layer, and the compound semiconductor layer is subsequently formed, the charged particle supply layer to the compound semiconductor layer can be continuously formed. Can grow to
The interface of the compound semiconductor layer becomes good. In the method for manufacturing a semiconductor device described above, a contact layer is formed on a compound semiconductor layer, a gate electrode formation region of the contact layer is recess-etched to expose the compound semiconductor layer, and a gate electrode is formed on the exposed compound semiconductor layer. You may do it.

Further, a contact layer is formed on the charged particle supply layer or the non-doped semiconductor layer, and the gate electrode formation region of the contact layer is recess-etched to expose the charged particle supply layer or the non-doped semiconductor layer to expose the compound semiconductor layer. It may be formed on the exposed charged particle supply layer or the non-doped semiconductor layer. Further, the compound semiconductor layer is patterned so that only the gate electrode formation region remains, a contact layer is formed on the compound semiconductor layer and the charged particle supply layer or the non-doped semiconductor layer, and the gate electrode formation region of the contact layer is recess-etched. The compound semiconductor layer may be exposed and the gate electrode may be formed on the exposed compound semiconductor layer.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.
FIG. 2 is a sectional view showing the semiconductor device according to the present embodiment.
A p-type transistor is formed in the left region and an n-type transistor is formed in the right region.

GaAs or AlG on the GaAs substrate 10
A buffer layer 11 made of aAs is formed. this
The thickness at which the hole channel is formed on the buffer layer 11 is about
14 nm i-In_0.2Ga_0.8As channel layer 12
Has been formed. Holes are provided on the channel layer 12.
Be doped impurity concentration of 2 × 10 ¹⁸
cm^-3And about 30 nm thick p-Al_0.7Ga_0.3As positive
The hole supply layer 13 is formed. On this hole supply layer 13
Has a stoichiometric amount so that As atoms, which are group V atoms, increase.
The composition ratio deviates from the theoretical ratio (stoichiometry), and the thickness is about 3
nm GaAs ^*The layer 14 is formed.

In the p-type transistor formation region on the left side, A
The gate electrode 15 mainly composed of 1 and having a thickness of about 300 nm is
GaAs in the center^*Schottky bonded to layer 14
GaAs on both sides of the electrode 15^*Be is deposited on the layer 14.
Impurity concentration 2 × 10 ¹⁸cm^-3With a thickness of about 20 nm
P-GaAs contact layer 16 is formed. Ko
On the contact layer 16, Au / Zn / Au (30 nm / 3
0 nm / 240 nm) source electrode 17 and drain
The in electrode 18 is formed.

In the n-type transistor forming region on the right side, a buffer layer 19 made of GaAs or AlGaAs is formed on the contact layer 16. This buffer layer 19
On top of which is formed an electron channel i with a thickness of about 14 nm.
A -In _0.2 Ga _0.8 As channel layer 20 is formed, and Si is provided on the channel layer 20 to supply electrons.
Impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and thickness of about 30
An n-Al _0.3 Ga _0.7 As electron supply layer 21 having a thickness of nm is formed. On this electron supply layer 21, the composition ratio deviates from the stoichiometry so that the number of Ga atoms, which are group III atoms, increases, and the composition ratio of GaAs ^{** is} about 3 nm.
The layer 22 is formed.

Further, at the center on the GaAs ^** layer 22, A
The gate electrode 23 having a thickness of about 300 nm containing l as a main component is Schottky-junctioned to form GaA on both sides of the gate electrode 23.
On the s ^** layer 22, a Si-doped impurity concentration of 2 × 1
An n-GaAs contact layer 24 having a thickness of 0 ¹⁸ cm ^-3 and a thickness of about 20 nm is formed. Au on the contact layer 24
A drain electrode 25 and a source electrode 26 made of Ge / Au (20 nm / 300 nm) are formed.

At the boundary between the p-type transistor formation region and the n-type transistor formation region, a high resistance region 27 formed by ion implantation of oxygen is formed in order to separate them, and the p-type transistor and the n-type transistor are formed. The elements are separated. A thickness of about 800 nm made of SiON is formed on the p-type transistor formation region and the n-type transistor formation region.
Is formed on the interlayer insulating film 28, and Ti / Pt / Au (30 nm / 200 nm / 800 nm) is formed on the interlayer insulating film 28.
nm) wiring layers 29, 30, 31, 32, 33 are formed.

The wiring layer 29 connected to the power supply voltage V _DD is
The wiring layers 30 and 32 connected to the source electrode 17 of the p-type transistor and connected to the input end are connected to the gate electrode 15 of the p-type transistor and the gate electrode 23 of the n-type transistor, respectively, and connected to the output end. The wiring layer 31 is
The wiring layer 3 connected to the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor and grounded
3 is connected to the source electrode 26 of the n-type transistor.

As described above, according to the present embodiment, in the p-type transistor, the stoichiometric ratio (stoichiometry) is set so that the composition ratio of the GaAs ^* layer 14 to which the gate electrode 15 is Schottky junction becomes large in As atoms. ), The barrier height of the Schottky junction is high, and the GaAs ^* layer 14
Has a bandgap larger than that of the channel layer 12. Also,
Since the source electrode 17 and the drain electrode 18 are in ohmic contact with the p-type contact layer 16, the source parasitic resistance is low. In addition, even in the n-type transistor, the gate electrode 23
Is shifted from the stoichiometric ratio (stoichiometry) so that the composition ratio of the GaAs ^** layer 22 to be Schottky junction is large, and the barrier height of the Schottky junction is high,
Moreover, the band gap of the GaAs ^** layer 22 is larger than that of the channel layer 20. Further, since the source electrode 26 and the drain electrode 25 are in ohmic contact with the n-type contact layer 24, the source parasitic resistance is low. Therefore, it is possible to realize a complementary transistor circuit which has a small gate leakage current even when the power supply voltage is increased and the device is operated at high speed, and which has low power consumption.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to the process sectional views of FIGS. First, by a MBE (Molecular Beam Epitaxial) method at a growth temperature of about 650 ° C., a buffer layer 11 made of GaAs or AlGaAs and a thickness of about 14 nm of i-In _0.2 Ga _0.8 A on a GaAs substrate 10.
s channel layer 12, Be doped impurity concentration 2 × 1
P-Al _0.7 Ga _0.3 A with a thickness of about ¹⁸ nm at 0 ¹⁸ cm ^-3
The s-hole supply layer 13 is sequentially grown (see FIG. 3A).

Subsequently, the substrate temperature is lowered to about 200.degree. C. without interrupting the growth, and the thickness of the As-rich growth condition is adjusted to about 200 under the As-rich growth condition such that the composition ratio of As atoms, which is a group V atom, becomes larger than the stoichiometric ratio. Grow a 3 nm GaAs ^* layer 14 (Fig. 3
(See (a)). For example, the As beam amount during growth is 10 ⁻⁵
Approximately 1 minute of growth was performed under an As-rich growth condition such that the amount of Torr and Ga beams was 10 ⁻⁷ Torr, and GaAs of about 3 nm was formed ^.
Form the layer 14.

Further, by setting the growth temperature lower than the growth temperature at which the stoichiometric GaAs layer is formed, the As deposition amount may be effectively increased to realize the As-rich growth condition. For example, the GaAs ^* layer 14 is formed at a growth temperature of about 180 ° C., which is about 20 ° C. lower than the growth temperature of about 200 ° C. at which a stoichiometric GaAs layer is formed.

Further, after growing the GaAs layer, As ions may be implanted to form an As-rich GaAs ^* layer 14 in which the composition ratio of As atoms is larger than the stoichiometric ratio. Then, the substrate temperature was raised again to about 650 ° C. without stopping the growth, and the Be-doped impurity concentration was 2 × 10 ¹⁸ cm ⁻³ and the thickness of the p-GaAs was about 20 nm.
A contact layer 16 is grown, and then a buffer layer 19 made of GaAs or AlGaAs, having a thickness of about 14 nm.
A thick i-In _0.2 Ga _0.8 As channel layer 20, Si-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 30 n
The n-Al _0.3 Ga _{0. 7} As electron supply layer 21 of m grows in order (see Figure 3 (a)).

Subsequently, the substrate temperature is lowered to about 200 ° C. without interrupting the growth, and the thickness is adjusted to about Ga under the Ga-rich growth condition such that the composition ratio of the Ga atom, which is a group III atom, becomes larger than the stoichiometric ratio. A 3 nm GaAs ^** layer 22 is grown (see FIG. 3 (a)). For example, the As beam amount during growth is 10
^-6 Torr, a Ga beam amount of 10 ^-7 Torr was grown for about 1 minute under a Ga-rich growth condition, and GaAs of about 3 nm was grown.
^** Form layer 22.

Further, by increasing the growth temperature higher than the growth temperature at which the GaAs layer with the stoichiometric ratio is formed, the Ga deposition amount may be effectively increased to realize the Ga-rich growth condition. For example, the GaAs ^** layer 22 is formed at a growth temperature of about 220 ° C., which is higher by about 20 ° C. than a growth temperature of about 200 ° C. at which a stoichiometric GaAs layer is formed.

Further, after the GaAs layer is grown, Ga ions may be implanted to form a Ga-rich GaAs ^** layer 22 in which the composition ratio of Ga atoms is larger than the stoichiometric ratio. Then, the substrate temperature was raised again to about 650 ° C. without interrupting the growth, and the Si-doped impurity concentration was 2 × 10 ¹⁸ cm ⁻³ and the thickness of the n-GaAs was about 20 nm.
The contact layer 24 is grown (see FIG. 3A).

Next, the element regions where the p-type transistor and the n-type transistor are formed are masked, and an element isolation region between these element regions is subjected to an acceleration voltage of 200 keV and a dose amount of 2 × 10 ¹² cm ^-2 . By implanting oxygen ions, a high resistance region 27 reaching the GaAs substrate 10 is formed (see FIG. 3B). Subsequently, the right n-type transistor formation region is masked with a resist (not shown), and the left p-type transistor formation region is etched and removed by wet etching until the p-GaAs contact layer 16 is exposed (see FIG. See b)).

Next, a resist (not shown) having openings in the formation regions of the drain electrode and the source electrode of the n-type transistor.
Is formed on the contact layer 24, and an AuGe layer having a thickness of about 20 nm and an Au layer having a thickness of about 300 nm are successively deposited on the entire surface. Then, the AuGe layer and the Au layer on the resist are removed by lift-off and alloyed at about 450 ° C. to form the drain electrode 25 and the source electrode 26 which make ohmic contact with the contact layer 24 (see FIG. 4A).

Next, a resist (not shown) having an opening in the gate electrode formation region of the n-type transistor is formed on the contact layer 24, and the contact layer 24 is recess-etched using this resist as a mask to form a GaAs ^** layer. 22 is exposed. Subsequently, an Al layer containing Al as a main component and having a thickness of about 300 nm is vapor-deposited on the entire surface, and subsequently, the Al layer on the resist is removed by lift-off, and the gate electrode 23 is Schottky-bonded to the GaAs ^** layer 22. To form (Fig. 4
(B)).

Then, similarly to the n-type transistor, p
Type transistor source electrode 17, drain electrode 18,
The gate electrode 15 is formed (see FIG. 5A). That is, a resist (not shown) having openings in the drain electrode and source electrode formation regions of the p-type transistor is formed on the contact layer 16, and an Au layer having a thickness of about 30 nm and about 30 nm are formed on the entire surface.
A Zn layer with a thickness of nm and an Au layer with a thickness of about 240 nm are successively deposited. Subsequently, the Au layer, Zn layer, and Au layer on the resist are removed by lift-off, and alloyed at about 400 ° C.,
Source electrode 17 in ohmic contact with contact layer 16
Then, the drain electrode 18 is formed (see FIG. 5A).

Subsequently, a resist (not shown) having an opening in the gate electrode formation region of the p-type transistor is formed on the contact layer 16, and the contact layer 16 is recess-etched using this resist as a mask to form the GaAs ^* layer 14 Expose the surface of. Subsequently, an Al layer containing Al as a main component and having a thickness of about 300 nm is vapor-deposited on the entire surface, and subsequently, the Al layer on the resist is removed by lift-off to form a gate electrode 15 which is Schottky bonded to the GaAs ^* layer 14. Formed (see FIG. 5A).

Next, an interlayer insulating film 28 made of SiON having a thickness of about 800 nm is deposited on the entire surface, and the gate electrode 15, the source electrode 17, and the drain electrode 18 of the p-type transistor are formed.
Gate electrode 23 and drain electrode 2 of n-type transistor
5. Open a contact hole that contacts the source electrode 26 (see FIG. 5B). Then, about 30
nm Ti layer and about 200 nm Pt layer and about 800 n
An Au layer having a thickness of m is successively deposited, and then patterned to form a wiring layer 29 for connecting the source electrode 17 of the p-type transistor to the power supply voltage V _DD and a gate electrode 15 of the p-type transistor for input terminals. A wiring layer 30 connected to
A wiring layer 31 for connecting the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor to the output terminal
, A wiring layer 32 connecting the gate electrode 23 of the n-type transistor to the input end, and a source electrode 26 of the n-type transistor
And a wiring layer 33 for grounding (see FIG. 5B). This completes the semiconductor device.

Incidentally, in order to perform a good recess etching, the GaAs ^* layer 14 and the p-GaAs contact layer 16 are formed.
Between the GaAs ^** layer 22 and the n-GaAs contact layer 2
An AlGaAs etching stopper layer with a thickness of about 3 nm is inserted between 4 and RIE by chlorine-based gas or CFC-based gas.
Therefore, the recess structure may be formed by selective dry etching.

Further, the source resistance and the drain resistance are reduced.
Therefore, in the case of a p-type transistor,
Annealing is performed after implanting Mg ions or the like into the drain region.
P ⁺A n-type transistor is formed.
After implanting Si ions etc. into the source region and the drain region
Annealed to n⁺A mold area may be formed. Furthermore, G
aAs^*Layer 14 and GaAs^**The growth of layer 22 is
About 20 lower than the normal growth temperature of the conductor layer (about 650 ° C)
Must be done at 0 ° C. At this time, the growth is suspended and the substrate
When the temperature is changed, the exposed surface of the compound semiconductor layer becomes acid.
Be converted. Especially, the surface of the AlGaAs layer is easily oxidized.
Need protection. Therefore, the controllability of the growth temperature is high.
Therefore, in order to continue continuous growth, p-Al_0.7Ga
_{0. 3}As hole supply layer 13 and GaAs^*Formed in the middle of layer 14
Impurity concentration 2 × 10 during long temperature drop¹⁸cm^-3At about thickness
A 3 nm p-GaAs layer is grown, and n-Al
_0.3Ga_0.7As electron supply layer 21 and GaAs^**Layer 22
Impurity concentration of 2 × 10¹⁸cm^-3
So as to grow an n-GaAs layer with a thickness of about 3 nm.
Good.

A semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a sectional view showing the semiconductor device according to the present embodiment. A p-type transistor is formed in the left region and an n-type transistor is formed in the right region. This embodiment is characterized in that the p-type transistor and the n-type transistor are separately grown, and the entire surface is a substantially flat element structure.

A p-type transistor is formed on the left side region of the GaAs substrate 10. A buffer layer 11 made of GaAs or AlGaAs is formed on the left side region of the GaAs substrate 10. On this buffer layer 11,
I-In having a thickness of about 14 nm in which a hole channel is formed
_{A 0.2} Ga _0.8 As channel layer 12 is formed. Be is provided on the channel layer 12 in order to supply holes.
Impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and thickness of about 30
nm p-Al _0.7 Ga _0.3 As hole supply layer 13 is formed. On this hole supply layer 13, a GaAs ^* layer 14 having a thickness of about 3 nm is formed, the composition ratio of which is deviated from the stoichiometric ratio so that the number of As atoms, which is a group V atom, increases.

Further, a gate electrode 15 having Al as a main component and having a thickness of about 300 nm is Schottky-junctioned in the center of the GaAs ^* layer 14, and GaAs ^* on both sides of the gate electrode 15 is formed ^.
On the layer 14, a Be-doped impurity concentration of 2 × 10 ¹⁸
p-GaAs contact layer 1 having a thickness of cm ^-3 and a thickness of about 20 nm
6 is formed. Au / Z on the contact layer 16
A source electrode 17 and a drain electrode 18 made of n / Au (30 nm / 30 nm / 240 nm) are formed.

An n-type transistor is formed on the right side region of the GaAs substrate 10. A buffer layer 19 made of GaAs or AlGaAs is formed on the right side region of the GaAs substrate 10. On this buffer layer 19,
I-In having a thickness of about 14 nm for forming an electron channel
_{A 0.2} Ga _0.8 As channel layer 20 is formed, and in order to supply electrons, an n-Al _0.3 Ga layer having an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 30 nm doped with Si is provided on the channel layer 20. _{The 0.7} As electron supply layer 21 is formed. On the electron supply layer 21, G that is a group III atom is
A GaAs ^** layer 22 having a thickness of about 3 nm and having a composition ratio deviated from the stoichiometric ratio so that the number of a atoms is increased is formed.

Further, at the center on the GaAs ^** layer 22, A
The gate electrode 23 having a thickness of about 300 nm containing l as a main component is Schottky-junctioned to form GaA on both sides of the gate electrode 23.
On the s ^** layer 22, a Si-doped impurity concentration of 2 × 1
An n-GaAs contact layer 24 having a thickness of 0 ¹⁸ cm ^-3 and a thickness of about 20 nm is formed. Au on the contact layer 24
A drain electrode 25 and a source electrode 26 made of Ge / Au (20 nm / 300 nm) are formed.

P-GaAs in the p-type transistor formation region
The upper surface of the contact layer 16 and the upper surface of the n-GaAs contact layer 24 in the n-type transistor formation region are substantially flush with each other without any step. p-type transistor formation region and n
At the boundary of the type transistor formation region, a high resistance region 27 formed by ion-implanting oxygen to separate them is formed.
Are formed to separate the p-type transistor and the n-type transistor from each other.

On the p-type transistor forming region and the n-type transistor forming region, a thickness of about 800 n made of SiON is formed.
m interlayer insulating film 28 is formed, and Ti / Pt / Au (30 nm / 200 nm / 80 is formed on the interlayer insulating film 28.
0 nm) wiring layers 29, 30, 31, 32, 33
Are formed. Wiring layer 2 connected to power supply voltage V _DD
9 is connected to the source electrode 17 of the p-type transistor,
The wiring layers 30 and 32 connected to the input end are connected to the gate electrode 15 of the p-type transistor and the gate electrode 23 of the n-type transistor, respectively, and the wiring layer 3 connected to the output end.
1 is connected to the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor, and the grounded wiring layer 33 is connected to the source electrode 26 of the n-type transistor.

As described above, according to this embodiment, in the p-type transistor, the composition ratio of the GaAs ^* layer 14 deviates from the stoichiometric ratio so that the number of As atoms increases, and the barrier height of the Schottky junction becomes high. , The band gap is the channel layer 12
Greater than In addition, the source electrode 17 and the drain electrode 18
Has ohmic contact with the p-type contact layer 16, so that the source parasitic resistance becomes low. Also in the n-type transistor, the composition ratio of the GaAs ^** layer 22 deviates from the stoichiometric ratio so that Ga atoms increase, and the barrier height of the Schottky junction is high, and the band gap is larger than that of the channel layer 20. Further, since the source electrode 26 and the drain electrode 25 are in ohmic contact with the n-type contact layer 24, the source parasitic resistance is low. Therefore, it is possible to realize a complementary transistor circuit which has a small gate leakage current even when the power supply voltage is increased and the device is operated at high speed, and which has low power consumption. Furthermore, since the upper surfaces of the p-type transistor formation region and the n-type transistor formation region are substantially flat, the wiring layer can be easily formed.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to the process sectional views of FIGS. First, a buffer layer 11 made of GaAs or AlGaAs is formed on a GaAs substrate 10 at a growth temperature of about 650 ° C. by an MBE method, and i-In _0.2 Ga _0.8 A having a thickness of about 14 nm.
s channel layer 12, Be doped impurity concentration 2 × 1
P-Al _0.7 Ga _0.3 A with a thickness of about ¹⁸ nm at 0 ¹⁸ cm ^-3
The s-hole supply layer 13 is sequentially grown (see FIG. 7A).

Then, the substrate temperature is lowered to about 200 ° C. without interrupting the growth, and the thickness is adjusted to about 200 nm under As-rich growth conditions such that the composition ratio of As atoms, which is a group V atom, becomes larger than the stoichiometric ratio. A 3 nm GaAs ^* layer 14 is grown (FIG. 7).
(See (a)). Then, the substrate temperature was raised again to about 650 ° C. without stopping the growth, and the Be-doped impurity concentration was 2 × 10 ¹⁸ cm ⁻³ and the thickness of the p-GaAs was about 20 nm.
The contact layer 16 is grown (see FIG. 7A).

Subsequently, a mask layer 40 made of SiON is formed on the p-GaAs contact layer 16 to mask the p-type transistor formation region on the left side (FIG. 7A).
reference). Next, using the mask layer 40 as a mask, the right n
Type contact layer 16, G in the transistor formation region
The aAs ^* layer 14, the hole supply layer 13, the channel layer 12, and the buffer layer 11 are removed by etching until the surface of the GaAs substrate 10 is exposed (see FIG. 7B).

Then, with the mask layer 40 still attached, on the GaAs substrate 10 in the n-type transistor formation region on the right side,
A buffer layer 19 made of GaAs or AlGaAs, an i-In _0.2 Ga _0.8 As channel layer 20 having a thickness of about 14 nm, n-Al _0.3 Ga having a Si-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 30 nm. _{The 0.7} As electron supply layer 21 is sequentially grown (see FIG. 7B).

Subsequently, the substrate temperature is lowered to about 200 ° C. without interrupting the growth, and the thickness is adjusted to about Ga under a Ga-rich growth condition such that the composition ratio of Ga atoms, which are group III atoms, becomes larger than the stoichiometric ratio. A 3 nm GaAs ^** layer 22 is grown (see FIG. 7B). Subsequently, the substrate temperature was raised again to about 650 ° C. without interrupting the growth, and the Si-doped impurity concentration was 2 × 10 ¹⁸ cm ⁻³ and the thickness of the n-GaA was about 20 nm.
The s contact layer 24 is grown (see FIG. 7B). Then, the mask layer 40 on the contact layer 16 is removed.

Next, the element regions where the p-type transistor and the n-type transistor are formed are masked, and an element isolation region between these element regions is subjected to an acceleration voltage of 200 keV and a dose amount of 2 × 10 ¹² cm ^-2 . By implanting oxygen ions, a high resistance region 27 reaching the GaAs substrate 10 is formed (see FIG. 7C). Next, a resist (not shown) having openings in the drain electrode and source electrode formation regions of the p-type transistor is formed on the contact layer 16, and an Au layer having a thickness of about 30 nm and a Zn layer having a thickness of about 30 nm are formed on the entire surface. 24
A 0 nm thick Au layer is subsequently deposited. Subsequently, the Au layer, the Zn layer, and the Au layer on the resist are removed by lift-off, alloying is performed at about 400 ° C., and the source electrode 17 and the drain electrode 28 that make ohmic contact with the contact layer 16 are formed (FIG. 8A). )reference).

Subsequently, a resist (not shown) having an opening in the drain electrode and source electrode formation regions of the n-type transistor is formed on the contact layer 24, and the entire surface is made to have a thickness of about 20 nm.
A thick AuGe layer and an Au layer of about 300 nm thickness are successively deposited. Subsequently, AuGe on the resist is lifted off.
The layer and the Au layer are removed and alloyed at about 450 ° C. to form a drain electrode 25 and a source electrode 26 that make ohmic contact with the contact layer 24 (see FIG. 8A).

Next, a resist (not shown) having openings in the gate electrode formation region of the p-type transistor and the gate electrode formation region of the n-type transistor is formed on the contact layer 16 and the contact layer 24, and this resist is formed. The contact layer 16 and the contact layer 24 are recess-etched as a mask to expose the surfaces of the GaAs ^* layer 14 and the GaAs ^** layer 22. Then, a thickness of about 300 with Al as the main component is formed on the entire surface.
deposited Al layer of nm, followed by an Al layer on the resist is removed by lift-off, GaAs ^* layer 14 and GaAs
^{** The} gate electrode 15 and the gate electrode 23, which are Schottky joined to the layer 22, are formed (see FIG. 8B).

Next, an interlayer insulating film 28 made of SiON having a thickness of about 800 nm is deposited on the entire surface, and the gate electrode 15, the source electrode 17, and the drain electrode 18 of the p-type transistor are formed.
Gate electrode 23 and drain electrode 2 of n-type transistor
5. Open a contact hole that contacts the source electrode 26 (see FIG. 8C). Then, about 30
nm Ti layer and about 200 nm Pt layer and about 800 n
An Au layer having a thickness of m is successively deposited, and then patterned to form a wiring layer 29 for connecting the source electrode 17 of the p-type transistor to the power supply voltage V _DD and a gate electrode 15 of the p-type transistor for input terminals. A wiring layer 30 connected to
A wiring layer 31 for connecting the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor to the output terminal
, A wiring layer 32 connecting the gate electrode 23 of the n-type transistor to the input end, and a source electrode 26 of the n-type transistor
And a wiring layer 33 for grounding (see FIG. 8C). This completes the semiconductor device.

It should be noted that in order to perform good recess etching, the GaAs ^* layer 14 and the p-GaAs contact layer 16 are formed.
Between the GaAs ^** layer 22 and the n-GaAs contact layer 2
An AlGaAs etching stopper layer with a thickness of about 3 nm is inserted between 4 and RIE by chlorine-based gas or CFC-based gas.
Therefore, the recess structure may be formed by selective dry etching.

Further, the source resistance and the drain resistance are reduced.
Therefore, in the case of a p-type transistor,
Annealing is performed after implanting Mg ions or the like into the drain region.
P ⁺A n-type transistor is formed.
After implanting Si ions etc. into the source region and the drain region
Annealed to n⁺A mold area may be formed. Furthermore, G
aAs^*Layer 14 and GaAs^**The growth of layer 22 is
About 20 lower than the normal growth temperature of the conductor layer (about 650 ° C)
Must be done at 0 ° C. At this time, the growth is suspended and the substrate
When the temperature is changed, the exposed surface of the compound semiconductor layer becomes acid.
Be converted. Especially, the surface of the AlGaAs layer is easily oxidized.
Need protection. Therefore, the controllability of the growth temperature is high.
Therefore, in order to continue continuous growth, p-Al_0.7Ga
_{0. 3}As hole supply layer 13 and GaAs^*Formed in the middle of layer 14
Impurity concentration 2 × 10 during long temperature drop¹⁸cm^-3At about thickness
A 3 nm p-GaAs layer is grown, and n-Al
_0.3Ga_0.7As electron supply layer 21 and GaAs^**Layer 22
Impurity concentration of 2 × 10¹⁸cm^-3
So as to grow an n-GaAs layer with a thickness of about 3 nm.
Good. A semiconductor device and a semiconductor device according to a third embodiment of the present invention.
The manufacturing method will be described with reference to FIGS. 9 to 11.

FIG. 9 is a sectional view showing the semiconductor device according to the present embodiment. A p-type transistor is formed in the left region and an n-type transistor is formed in the right region.
In this embodiment, a GaAs ^* layer and a GaAs ^** layer for Schottky contact are provided under the gate electrode, and p-GaAs for ohmic contact is provided under the source electrode and the drain electrode.
It is characterized in that a layer and an n-GaAs layer are provided.

A p-type transistor is formed on the left side region of the GaAs substrate 10. A buffer layer 11 made of GaAs or AlGaAs is formed on the left side region of the GaAs substrate 10. On this buffer layer 11,
I-In having a thickness of about 14 nm in which a hole channel is formed
_{A 0.2} Ga _0.8 As channel layer 12 is formed. Be is provided on the channel layer 12 in order to supply holes.
Impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and thickness of about 30
nm p-Al _0.7 Ga _0.3 As hole supply layer 13 is formed.

On this hole supply layer 13, a Be-doped impurity concentration of 2 × 10 ¹⁸ cm ^-3 and a p-thickness of about 20 nm are formed.
-A GaAs contact layer 16 is formed, and the center of the contact layer 16 is recess-etched to form the hole supply layer 1.
3 is exposed. About 3 nm thick GaAs ^* with a composition ratio deviated from the stoichiometric ratio so that the number of As atoms, which is a group V atom, is increased up to the contact layer 16 on the left and right of the recess in the center of the hole supply layer 13 ^. The layer 14 is formed. A gate electrode 15 containing Al as a main component and having a thickness of about 300 nm is Schottky-bonded on the GaAs ^* layer 14.

Openings for the source electrode and the drain electrode are formed in the GaAs ^* layer 14 on the contact layer 16 to expose the contact layer 16. Contact layer 1
6 is Au / Zn / Au (30 nm / 30 nm / 24
0 nm) source electrode 17 and drain electrode 18
Are formed. An n-type transistor is formed on the right side region of the GaAs substrate 10. GaAs substrate 1
A buffer layer 19 made of GaAs or AlGaAs is formed in the right region above 0. This buffer layer 19
On top of which is formed an electron channel i with a thickness of about 14 nm.
A -In _0.2 Ga _0.8 As channel layer 20 is formed, and Si is provided on the channel layer 20 to supply electrons.
Impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and thickness of about 30
An n-Al _0.3 Ga _0.7 As electron supply layer 21 having a thickness of nm is formed.

On this electron supply layer 21, an n-type impurity of 2 × 10 ¹⁸ cm ⁻³ with a thickness of about 20 nm doped with Si is formed.
-A GaAs contact layer 24 is formed, and the center of the contact layer 24 is recess-etched to form the electron supply layer 2.
1 is exposed. About 3 nm thick GaAs ^** with a composition ratio deviated from the stoichiometric ratio so that Ga atoms, which are group III atoms, fill the recess in the center of the electron supply layer 21 and reach the contact layers 24 on the left and right of the recess. The layer 22 is formed. On the GaAs ^** layer 22, a gate electrode 23 containing Al as a main component and having a thickness of about 300 nm is Schottky junctioned.

Openings for the source electrode and the drain electrode are formed in the GaAs ^** layer 22 on the contact layer 24 to expose the contact layer 24. Contact layer 2
A drain electrode 25 and a source electrode 26 made of AuGe / Au (20 nm / 300 nm) are formed on the surface 4. At the boundary between the p-type transistor formation region and the n-type transistor formation region, a high resistance region 27 formed by ion implantation of oxygen is formed in order to separate them, and the p-type transistor and the n-type transistor are separated from each other. ing.

On the p-type transistor forming region and the n-type transistor forming region, a thickness of about 800 n made of SiON is formed.
m interlayer insulating film 28 is formed, and Ti / Pt / Au (30 nm / 200 nm / 80 is formed on the interlayer insulating film 28.
0 nm) wiring layers 29, 30, 31, 32, 33
Are formed. Wiring layer 2 connected to power supply voltage V _DD
9 is connected to the source electrode 17 of the p-type transistor,
The wiring layers 30 and 32 connected to the input end are connected to the gate electrode 15 of the p-type transistor and the gate electrode 23 of the n-type transistor, respectively, and the wiring layer 3 connected to the output end.
1 is connected to the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor, and the grounded wiring layer 33 is connected to the source electrode 26 of the n-type transistor.

As described above, according to this embodiment, in the p-type transistor, the composition ratio of the GaAs ^* layer 14 deviates from the stoichiometric ratio so that the number of As atoms increases, and the barrier height of the Schottky junction becomes high. , The band gap is the channel layer 12
Greater than In addition, the source electrode 17 and the drain electrode 18
Has ohmic contact with the p-type contact layer 16, so that the source parasitic resistance becomes low. Also in the n-type transistor, the composition ratio of the GaAs ^** layer 22 deviates from the stoichiometric ratio so that Ga atoms increase, and the barrier height of the Schottky junction is high, and the band gap is larger than that of the channel layer 20. Further, since the source electrode 26 and the drain electrode 25 are in ohmic contact with the n-type contact layer 24, the source parasitic resistance is low. Therefore, it is possible to realize a complementary transistor circuit which has a small gate leakage current even when the power supply voltage is increased and the device is operated at high speed, and which has low power consumption. Furthermore, the source electrodes 17, 26 and the drain electrodes 18, 25
The contact layers 16 and 24 in ohmic contact with
Since it is in contact with the hole supply layer 13 and the electron supply layer 21 without interposing the As ^* layer 14 and the GaAs ^** layer 22, the ohmic resistance can be reduced.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to the process sectional views of FIGS.
First, GaAs was grown by the MBE method at a growth temperature of about 650 ° C.
On the substrate 10, a buffer layer 11 made of GaAs or AlGaAs, i-In _0.2 Ga _{0.8 with a} thickness of about 14 nm.
As channel layer 12, Be doped impurity concentration 2 ×
P-Al _0.7 Ga _0.3 with a thickness of 30 nm at 10 ¹⁸ cm ^-3
As hole supply layer 13, Be doped impurity concentration 2 ×
A p-GaAs contact layer 16 having a thickness of 10 ¹⁸ cm ⁻³ and a thickness of about 20 nm is sequentially grown (see FIG. 10A).

Then, a mask layer (not shown) made of SiON is formed on the p-GaAs contact layer 16 to mask the left p-type transistor formation region. Then, using the mask layer 40 as a mask, the contact layer 16, the hole supply layer 13, the channel layer 12, and the buffer layer 11 in the right n-type transistor formation region are removed by etching until the surface of the GaAs substrate 10 is exposed (FIG. 10).
(See (a)).

Then, with the mask layer attached, the n on the right side is
Ga on the GaAs substrate 10 in the region where the type transistors are formed.
Buffer layer 19 made of As or AlGaAs, i-In _0.2 Ga _0.8 As channel layer 2 having a thickness of about 14 nm
0, Si-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 30 nm n-Al _0.3 Ga _0.7 As electron supply layer 2
1. An n-GaAs contact layer 24 having an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ doped with Si and a thickness of about 20 nm is sequentially grown (see FIG. 10A). Then, the mask layer on the contact layer 16 is removed.

Next, the element regions where the p-type transistor and the n-type transistor are formed are masked, and an element isolation region between these element regions is subjected to an acceleration voltage of 200 keV and a dose amount of 2 × 10 ¹² cm ^-2 . By implanting oxygen, a high resistance region 27 reaching the GaAs substrate 10 is formed (see FIG. 10B). Then, in order to mask the p-type transistor formation region on the left side, the contact layer 16
A mask layer 41 made of SiON is formed thereon. Subsequently, a resist (not shown) having an opening in the formation region of the gate electrode of the n-type transistor is formed on the contact layer 24, and the contact layer 24 is recess-etched using this resist as a mask to expose the surface of the electron supply layer 21. It is exposed (see FIG. 10B).

Subsequently, the substrate temperature is set to about 200 ° C., and II
Under a Ga-rich growth condition such that the composition ratio of Ga atoms, which are group I atoms, is larger than the stoichiometric ratio, a G of about 3 nm thickness is formed.
The aAs ^** layer 22 is grown on the electron supply layer 21 in the recess portion and the contact layers 24 on the left and right of the electron supply layer 21 (see FIG. 10B). Next, a mask layer 42 made of SiON is formed on the GaAs ^** layer 22 to mask the n-type transistor formation region on the right side. Subsequently, a resist (not shown) having an opening in the region where the gate electrode of the p-type transistor is formed is formed on the contact layer 16, and the contact layer 16 is recess-etched using this resist as a mask. Is exposed (see FIG. 10C).

Then, the substrate temperature is set to about 200 ° C. and V
The composition ratio of the As atom, which is a group atom, is larger than the stoichiometric ratio
Ga with a thickness of about 3 nm under As-rich growth conditions
As ^*The layer 14 is defined as the hole supply layer 13 in the recess portion and the left side thereof.
It grows on the right contact layer 16 (see FIG. 10C).
See). Next, the drain electrode and source of the p-type transistor
The region where the electrode is formed and the drain electrode of the n-type transistor
A resist (not shown) having an opening in the region where the source electrode is formed
GaAs^*Layer 14 and GaAs^**Formed on layer 22
It Using this resist as a mask, GaAs^*Layer 14 and
And GaAs^**The layer 22 is opened and the contact layer 16 and
The contact layer 24 is exposed.

Next, about 3 is formed in the p-type transistor formation region.
0 nm thick Au layer and approximately 30 nm thick Zn layer and approximately 30 nm
A thick Au layer is successively deposited, and an AuGe layer having a thickness of about 20 nm and an Au layer having a thickness of about 300 nm are formed in the formation region of the n-type transistor.
Successive layers are deposited. Subsequently, the Au layer, the Zn layer, the Au layer, the AuGe layer, and the Au layer on the resist are removed by lift-off, alloyed at about 400 to 450 ° C., and the source electrode 17 and the drain electrode 28 which make ohmic contact with the contact layer 16 are formed. Then, a drain electrode 25 and a source electrode 26 which make ohmic contact with the contact layer 24 are formed (see FIG. 11A).

Next, a resist (not shown) having openings in the gate electrode formation region of the p-type transistor and the gate electrode formation region of the n-type transistor is formed. Then, an Al layer containing Al as a main component and having a thickness of about 300 nm is vapor-deposited on the entire surface, and then the Al layer on the resist is removed by lift-off, and the GaAs ^* layer 14 and the GaAs ^** layer 22 are Schottky bonded. The gate electrode 15 and the gate electrode 23 thus formed are formed (see FIG. 11B).

Next, an interlayer insulating film 28 made of SiON having a thickness of about 800 nm is deposited on the entire surface to form a gate electrode 15, a source electrode 17, and a drain electrode 18 of the p-type transistor.
Gate electrode 23 and drain electrode 2 of n-type transistor
5. Open a contact hole that contacts the source electrode 26 (see FIG. 8C). Then, about 30
nm Ti layer and about 200 nm Pt layer and about 800 n
An Au layer having a thickness of m is successively deposited, and then patterned to form a wiring layer 29 for connecting the source electrode 17 of the p-type transistor to the power supply voltage V _DD and a gate electrode 15 of the p-type transistor for input terminals. A wiring layer 30 connected to
A wiring layer 31 for connecting the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor to the output terminal
, A wiring layer 32 connecting the gate electrode 23 of the n-type transistor to the input end, and a source electrode 26 of the n-type transistor
And a wiring layer 33 for grounding (see FIG. 8C). This completes the semiconductor device.

The source resistance and drain resistance are reduced.
Therefore, in the case of a p-type transistor,
Annealing is performed after implanting Mg ions or the like into the drain region.
P ⁺A n-type transistor is formed.
After implanting Si ions etc. into the source region and the drain region
Annealed to n⁺A mold area may be formed. Of the present invention
A semiconductor device and its manufacturing method according to the fourth embodiment will be described.
This will be described with reference to FIGS. 12 to 14.

FIG. 12 is a sectional view showing the semiconductor device according to the present embodiment. A p-type transistor is formed in the left region and an n-type transistor is formed in the right region.
In this embodiment, a GaAs ^* layer and a GaAs ^** layer for Schottky contact are provided under the gate electrode, and p-GaAs for ohmic contact is provided under the source electrode and the drain electrode.
3rd in that it has a layer and an n-GaAs layer.
Similar to the example of Example 1, but with a GaAs ^* layer and a GaAs ^** layer.
The layer is characterized in that the layer is successively grown on the hole supply layer and the electron supply layer, and then the p-GaAs layer and the n-GaAs layer are formed.

A p-type transistor is formed on the left side region of the GaAs substrate 10. A buffer layer 11 made of GaAs or AlGaAs is formed on the left side region of the GaAs substrate 10. On this buffer layer 11,
I-In having a thickness of about 14 nm in which a hole channel is formed
_{A 0.2} Ga _0.8 As channel layer 12 is formed. Be is provided on the channel layer 12 in order to supply holes.
Impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and thickness of about 30
nm p-Al _0.7 Ga _0.3 As hole supply layer 13 is formed.

On this hole supply layer 13, the composition ratio deviates from the stoichiometric ratio so that the number of As atoms, which is a group V atom, increases in the central gate electrode formation region. A GaAs ^* layer 14 is formed, and a Be-doped p-GaAs contact layer 16 with an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 20 nm is formed in the left and right source electrode and drain electrode formation regions. ..

A gate electrode 15 containing Al as a main component and having a thickness of about 300 nm is Schottky-junctioned on the GaAs ^* layer 14, and Au / Zn / Au (3
Source electrode 1 composed of 0 nm / 30 nm / 240 nm)
7 and the drain electrode 18 are formed. An n-type transistor is formed on the right side region of the GaAs substrate 10. A buffer layer 19 made of GaAs or AlGaAs is formed on the right side region of the GaAs substrate 10. An i-In _0.2 Ga _0.8 As channel layer 20 having a thickness of about 14 nm for forming an electron channel is formed on the buffer layer 19, and Si is supplied on the channel layer 20 to supply electrons. Doped impurity concentration 2 × 1
N-Al _0.3 Ga _0.7 A with a thickness of about 30 nm at 0 ¹⁸ cm ^-3
The s electron supply layer 21 is formed.

On the electron supply layer 21, the composition ratio is deviated from the stoichiometric ratio so that the number of Ga atoms, which are group III atoms, increases in the central gate electrode formation region, and the thickness is about 3 nm.
GaAs ^** layer 22 is formed, and an n-GaAs contact layer 24 having a Si-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 20 nm is formed in the left and right source and drain electrode formation regions. ing.

On the GaAs ^** layer 22, a gate electrode 23 containing Al as a main component and having a thickness of about 300 nm is Schottky-bonded, and on the contact layer 24, AuGe / Au (2
A drain electrode 25 and a source electrode 26 of 0 nm / 300 nm) are formed. At the boundary between the p-type transistor formation region and the n-type transistor formation region, a high resistance region 27 formed by ion implantation of oxygen is formed in order to separate them, and the p-type transistor and the n-type transistor are separated from each other. ing.

On the p-type transistor formation region and the n-type transistor formation region, a thickness of SiON of about 800 n is formed.
m interlayer insulating film 28 is formed, and Ti / Pt / Au (30 nm / 200 nm / 80 is formed on the interlayer insulating film 28.
0 nm) wiring layers 29, 30, 31, 32, 33
Are formed. Wiring layer 2 connected to power supply voltage V _DD
9 is connected to the source electrode 17 of the p-type transistor,
The wiring layers 30 and 32 connected to the input end are connected to the gate electrode 15 of the p-type transistor and the gate electrode 23 of the n-type transistor, respectively, and the wiring layer 3 connected to the output end.
1 is connected to the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor, and the grounded wiring layer 33 is connected to the source electrode 26 of the n-type transistor.

As described above, according to this embodiment, in the p-type transistor, the composition ratio of the GaAs ^* layer 14 deviates from the stoichiometric ratio so that the number of As atoms increases, and the barrier height of the Schottky junction becomes high. , The band gap is the channel layer 12
Greater than In addition, the source electrode 17 and the drain electrode 18
Has ohmic contact with the p-type contact layer 16, so that the source parasitic resistance becomes low. Also in the n-type transistor, the composition ratio of the GaAs ^** layer 22 deviates from the stoichiometric ratio so that Ga atoms increase, and the barrier height of the Schottky junction is high, and the band gap is larger than that of the channel layer 20. Further, since the source electrode 26 and the drain electrode 25 are in ohmic contact with the n-type contact layer 24, the source parasitic resistance is low. Therefore, it is possible to realize a complementary transistor circuit which has a small gate leakage current even when the power supply voltage is increased and the device is operated at high speed, and which has low power consumption. Furthermore, the source electrodes 17, 26 and the drain electrodes 18, 25
The contact layers 16 and 24 in ohmic contact with
Since it is in contact with the hole supply layer 13 and the electron supply layer 21 without interposing the As ^* layer 14 and the GaAs ^** layer 22, the ohmic resistance can be reduced.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to the process sectional views of FIGS.
First, GaAs was grown by the MBE method at a growth temperature of about 650 ° C.
On the substrate 10, a buffer layer 11 made of GaAs or AlGaAs, i-In _0.2 Ga _{0.8 with a} thickness of about 14 nm.
As channel layer 12, Be doped impurity concentration 2 ×
P-Al _0.7 Ga _0.3 with a thickness of 30 nm at 10 ¹⁸ cm ^-3
The As hole supply layer 13 is sequentially grown (see FIG. 13A).

Then, the substrate temperature is maintained without interrupting the growth.
To about 200 ℃, and the composition ratio of As atoms, which are group V atoms,
As-rich growth condition in which the ratio is greater than the stoichiometric ratio
GaAs with a thickness of about 3 nm^*Growing layer 14 (Fig. 1
3 (a)). Next, forming the p-type transistor on the left side
P-GaAs contact layer 16 for masking regions
Form a mask layer (not shown) of SiON on top
It Using the mask layer 40 as a mask, the n-type transistor on the right side is
GaAs in the transistor formation region ^*Layer 14, hole supply
The layer 13, the channel layer 12, and the buffer layer 11 are made of GaAs
Etching is performed until the surface of the plate 10 is exposed (FIG. 13).
(See (a)).

Then, with the mask layer attached, the n on the right side is
Ga on the GaAs substrate 10 in the region where the type transistors are formed.
Buffer layer 19 made of As or AlGaAs, i-In _0.2 Ga _0.8 As channel layer 2 having a thickness of about 14 nm
0, Si-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of about 30 nm n-Al _0.3 Ga _0.7 As electron supply layer 2
1 are sequentially grown (see FIG. 13A).

Then, the substrate temperature is lowered to about 200 ° C. without interrupting the growth, and the thickness is adjusted to about Ga under a Ga-rich growth condition such that the composition ratio of Ga atoms, which are group III atoms, becomes larger than the stoichiometric ratio. A 3 nm GaAs ^** layer 22 is grown (see FIG. 13A). Next, a resist (not shown) masking the gate electrode formation region of the p-type transistor and the gate electrode formation region of the n-type transistor is formed, and the GaAs ^* layer 14 in the source region and the drain region 14 is formed using this resist as a mask. And the GaAs ^** layer 22 are removed by etching (see FIG. 13A).

Subsequently, the substrate temperature is set to about 650 ° C. and p
In the formation region of the n-type transistor, a Be-doped impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a p-GaAs contact layer 16 having a thickness of about 20 nm are grown, and subsequently, the formation region of the n-type transistor is doped with Si. Concentration 2 × 10 ¹⁸ cm
^{At −3} , an n-GaAs contact layer 24 having a thickness of about 20 nm is grown (see FIG. 13B).

Subsequently, the element regions where the p-type transistor and the n-type transistor are formed are masked, and an element isolation region between these element regions is subjected to an acceleration voltage of 200 keV and a dose amount of 2 × 10 ¹² cm ^-2 . By implanting oxygen ions, a high resistance region 27 reaching the GaAs substrate 10 is formed (see FIG. 13B). Next, a resist (not shown) having openings in the drain electrode and source electrode formation regions of the p-type transistor is formed on the contact layer 16, and an Au layer having a thickness of about 30 nm and a Zn layer having a thickness of about 30 nm are formed on the entire surface. A 30 nm thick Au layer is subsequently deposited. Subsequently, the Au layer, the Zn layer, and the Au layer on the resist are removed by lift-off, alloying is performed at about 400 ° C., and the source electrode 17 and the drain electrode 28 that make ohmic contact with the contact layer 16 are formed.
Are formed (see FIG. 13C).

Subsequently, a resist (not shown) having an opening in the formation region of the drain electrode and the source electrode of the n-type transistor is formed on the contact layer 24, and the entire surface is covered with about 20 nm.
A thick AuGe layer and an Au layer of about 300 nm thickness are successively deposited. Subsequently, AuGe on the resist is lifted off.
The layer and the Au layer are removed and alloyed at about 450 ° C. to form a drain electrode 25 and a source electrode 26 which make ohmic contact with the contact layer 24 (see FIG. 13C).

Next, a resist (not shown) having openings in the gate electrode formation region of the p-type transistor and the gate electrode formation region of the n-type transistor is formed on the contact layer 16 and the contact layer 24. The contact layer 16 and the contact layer 24 are recess-etched as a mask to expose the surfaces of the GaAs ^* layer 14 and the GaAs ^** layer 22. Then, a thickness of about 300 with Al as the main component is formed on the entire surface.
deposited Al layer of nm, followed by an Al layer on the resist is removed by lift-off, GaAs ^* layer 14 and GaAs
^{** The} gate electrode 15 and the gate electrode 23, which are Schottky joined to the layer 22, are formed (see FIG. 14A).

Next, an interlayer insulating film 28 made of SiON having a thickness of about 800 nm is deposited on the entire surface, and the gate electrode 15, the source electrode 17, and the drain electrode 18 of the p-type transistor are formed.
Gate electrode 23 and drain electrode 2 of n-type transistor
5. Open a contact hole that contacts the source electrode 26 (see FIG. 14B). Then, about 3 on the entire surface
0 nm thick Ti layer and approximately 200 nm thick Pt layer and approximately 800
source electrode 17 of the p-type transistor by successively depositing a Au layer having a thickness of nm and then patterning.
A wiring layer 29 connected to the power supply voltage V _DD and a wiring layer 30 for connecting the gate electrode 15 of the p-type transistor to the input terminal
And a wiring layer 3 for connecting the drain electrode 18 of the p-type transistor and the drain electrode 25 of the n-type transistor to the output terminal
1, a wiring layer 32 connecting the gate electrode 23 of the n-type transistor to the input end, and a source electrode 2 of the n-type transistor
A wiring layer 33 for grounding 6 is formed (see FIG. 14B). This completes the semiconductor device.

In order to perform good recess etching, the GaAs ^* layer 14 and the p-GaAs contact layer 16 are formed.
Between the GaAs ^** layer 22 and the n-GaAs contact layer 2
An AlGaAs etching stopper layer having a thickness of about 20 nm is inserted between 4 and RI by a chlorine-based gas or a CFC-based gas.
With E, the recess structure may be formed by selective dry etching.

Further, the source resistance and the drain resistance are reduced.
Therefore, in the case of a p-type transistor,
Annealing is performed after implanting Mg ions or the like into the drain region.
P ⁺A n-type transistor is formed.
After implanting Si ions etc. into the source region and the drain region
Annealed to n⁺A mold area may be formed. Of the present invention
A semiconductor device and its manufacturing method according to the fifth embodiment will be described.
This will be described with reference to FIGS.

FIG. 15 is a sectional view showing the semiconductor device according to the present embodiment. A p-type transistor is formed in the left region and an n-type transistor is formed in the right region.
A buffer layer 51 made of GaAs or AlGaAs is formed on a GaAs substrate 50. This buffer layer 5
1 on which a channel is formed, i-In having a thickness of about 14 nm.
_{A 0.2} Ga _0.8 As channel layer 52 is formed. On the channel layer 52, a non-doped layer having a thickness of about 30 nm
I-Al _0.5 Ga _0.5 As layer 53 is formed.
The composition ratio (x = 0.3) of the hole supply layer and the composition ratio (x = 0.7) of the electron supply layer of the above-described embodiment are substantially in between.
0.5).

In the p-type transistor formation region on the left side, i
On the —Al _0.5 Ga _0.5 As layer 53, A that is a group V atom
A GaAs ^* layer 54 having a thickness of about 3 nm, in which the composition ratio deviates from the stoichiometric ratio so that the number of s atoms increases, is formed. At the center of the GaAs ^* layer 54, a gate electrode 55 made of WSi and having a thickness of about 300 nm is Schottky-bonded.

Under the regions on both sides of the gate electrode 55, Mg
P where p-type dopant and the like is activated ion implanted ⁺
A type source region 56 and ap ⁺ type drain region 57 are formed. p ⁺ type source region 56 and p ⁺ type drain region 5
7 is formed to a depth reaching the buffer layer 51.
On the p ⁺ type source region 56 and the p ⁺ type drain region 57, Au / Zn / Au (30 nm / 30 nm / 240 n
m), a source electrode 58 and a drain electrode 59 are formed and are in ohmic contact.

In the n-type transistor formation region on the right side, i
On the -Al _0.5 Ga _0.5 As layer 53, a GaAs ^** layer 60 having a thickness of about 3 nm is formed, the composition ratio of which is deviated from the stoichiometric ratio (stoichiometry) so as to increase the number of Ga atoms which are group III atoms. Has been done. At the center of the GaAs ^** layer 60, a gate electrode 61 made of WSi and having a thickness of about 300 nm is formed.
Is Schottky joined.

Under the regions on both sides of the gate electrode 61, Si is formed.
N ⁺ activated by ion implantation of n-type dopant such as
A type source region 62 and an n ⁺ type drain region 63 are formed. n ⁺ type source region 62 and n ⁺ type drain region 6
3 is formed to a depth reaching the buffer layer 51.
A drain electrode 64 and a source electrode 65 made of AuGe / Au (20 nm / 300 nm) are formed on the n ⁺ type source region 62 and the n ⁺ type drain region 63, and are in ohmic contact.

On the p-type transistor formation region and the n-type transistor formation region, a thickness of about 800 made of SiON is formed.
an interlayer insulating film 68 having a thickness of
On top, Ti / Pt / Au (30 nm / 200 nm / 8
00 nm) wiring layers 69, 70, 71, 72, 7
3 are formed. The wiring layer 69 connected to the power supply voltage V _DD is connected to the source electrode 58 of the p-type transistor, and the wiring layers 70 and 72 connected to the input ends are the gate electrode 55 of the p-type transistor and the n-type transistor, respectively. The wiring layer 71 connected to the gate electrode 61 and connected to the output end is connected to the drain electrode 59 of the p-type transistor and the drain electrode 65 of the n-type transistor, and the grounded wiring layer 73 is the source of the n-type transistor. It is connected to the electrode 64.

As described above, according to the present embodiment, in the p-type transistor, the composition ratio of the GaAs ^* layer 54 to which the gate electrode 55 is Schottky junction deviates from the stoichiometric ratio so that the number of As atoms increases. The barrier height of the Schottky junction is high, and the band gap of the GaAs ^* layer 54 is larger than that of the channel layer 52. Further, since the source electrode 58 and the drain electrode 59 are in ohmic contact with the p ⁺ type source region 56 and the p ⁺ type drain region 57, the source parasitic resistance becomes low. Also in the n-type transistor, the composition ratio of the GaAs ^** layer 60 to which the gate electrode 61 is Schottky junction deviates from the stoichiometric ratio so that the number of Ga atoms is large, and the barrier height of the Schottky junction is high. , GaA
The band gap of the s ^** layer 60 is larger than that of the channel layer 52. Further, since the source electrode 64 and the drain electrode 65 are in ohmic contact with the n ⁺ type source region 62 and the n ⁺ type drain region 63, the source parasitic resistance becomes low. Therefore, it is possible to realize a complementary transistor circuit which has a small gate leakage current even when the power supply voltage is increased and the device is operated at high speed, and which has low power consumption.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to the process sectional views of FIGS.
First, MBE (Molecular Beam Epitaxial) method or MOCVD (Metal Organic Chemic) method.
Al Vapor Deposition: GaAs or AlGaAs buffer layer 51 on the GaAs substrate 50 at a growth temperature of about 650 ° C. by the metal organic CVD method, and an i-In _0.2 Ga _0.8 As channel layer of about 14 nm thickness in which a channel is formed. 52, undoped i-Al with a thickness of about 30 nm
The _0.5 Ga _{0. 5} As layer 53 is grown in order (FIG. 16
(See (a)).

Next, the right n-type transistor formation region is masked to lower the substrate temperature to about 200 ° C., and the left p-type transistor formation region i-Al _0.5 Ga _0.5 As layer 5 is formed.
3 under the As-rich growth condition such that the composition ratio of As atoms, which is a group V atom, is larger than the stoichiometric ratio.
A GaAs ^* layer 54 having a thickness of nm is formed (see FIG. 16B).

Then, the p-type transistor formation region on the left side is masked to lower the substrate temperature to about 200 ° C.
On the i-Al _0.5 Ga _0.5 As layer 53 in the type transistor formation region, at a substrate temperature of approximately 200 ° C.
a GaAs ^** layer 60 with a thickness of about 3 nm under rich growth conditions
Are grown (see FIG. 16B).

Next, WSi having a thickness of about 300 nm is deposited on the entire surface by a sputtering method and patterned so that the gate electrode formation regions of the p-type transistor and the n-type transistor remain, and the gate electrode is formed at the center of the GaAs ^* layer 54. 55
And a gate electrode 55 is formed at the center of the GaAs ^* layer 54 (FIG. 16C). Next, using the resist 80 having an opening in the n-type transistor formation region on the right side as a mask,
Ion implantation of an n-type dopant such as Si, and then about 7
Activate by performing a furnace annealing treatment at 50 ° C. for about 10 minutes. Alternatively, activation may be performed by lamp annealing at about 900 ° C. for about 10 seconds. Thereby, the gate electrode 6
N ⁺ type source region 62 by self-alignment on both sides of 1
And n ⁺ type drain region 63 are formed (FIG. 16).
(D)).

Next, a p-type dopant such as Mg is ion-implanted using the resist 81 having an opening in the left p-type transistor formation region as a mask, and then at about 750 ° C. for about 10 minutes.
Activate by annealing for a minute. As a result, the p ⁺ type source region 56 and the p ⁺ type drain region 57 are formed on both sides of the gate electrode 55 by self-alignment (FIG. 1).
7 (a)).

The annealing treatment for activating the n-type dopant and the p-type dopant may be collectively performed after the ion implantation. Next, a resist (not shown) having openings in the drain electrode and source electrode formation regions of the left p-type transistor is formed, and an Au layer with a thickness of about 30 nm, a Zn layer with a thickness of about 30 nm, and a layer with a thickness of about 240 nm are formed on the entire surface. The Au layer is subsequently deposited. Subsequently, A on the resist is lifted off.
The u layer, the Zn layer, and the Au layer are removed, alloyed at about 400 ° C., and the p ⁺ type source region 56 and the p ⁺ type drain region 5 are formed.
A source electrode 58 and a drain electrode 59 which are in ohmic contact with 7 are formed (see FIG. 17B).

Next, a resist (not shown) having openings in the drain electrode and source electrode formation regions of the right n-type transistor is formed, and an AuGe layer having a thickness of about 20 nm and an Au layer having a thickness of about 300 nm are successively formed on the entire surface. Vapor deposition. Subsequently, the AuGe layer and the Au layer on the resist are removed by lift-off and alloyed at about 450 ° C. to form a drain electrode 64 and a source electrode 65 which make ohmic contact with the n ⁺ type source region 62 and the n ⁺ type drain region 63. Yes (Fig. 17 (b))
reference).

Next, an interlayer insulating film 68 made of SiON having a thickness of about 800 nm is deposited on the entire surface, and a gate electrode 55, a source electrode 58 and a drain electrode 59 of the p-type transistor are formed.
Gate electrode 61 and drain electrode 6 of n-type transistor
5. Open a contact hole that contacts the source electrode 64 (see FIG. 17C). Then, about 3 on the entire surface
0 nm thick Ti layer and approximately 200 nm thick Pt layer and approximately 800
The Au electrode having a thickness of nm is vapor-deposited successively, and then patterned to form the source electrode 58 of the p-type transistor.
A wiring layer 69 connected to the power supply voltage V _DD and a wiring layer 70 for connecting the gate electrode 55 of the p-type transistor to the input terminal
And a wiring layer 7 for connecting the drain electrode 59 of the p-type transistor and the drain electrode 65 of the n-type transistor to the output end.
1, a wiring layer 72 connecting the gate electrode 61 of the n-type transistor to the input end, and the source electrode 6 of the n-type transistor
4 and the wiring layer 73 for grounding are formed (see FIG. 17C). This completes the semiconductor device.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, in the above-mentioned embodiment, the GaAs ^* layer in which As atoms are larger than the stoichiometric ratio and the GaAs ^** layer in which Ga atoms are larger than the stoichiometric ratio are used, but an AlGaAs layer may be used instead of the GaAs layer. . That is, in the p-type transistor, AlGa having more As atoms than the stoichiometric ratio is used.
An As ^* layer may be used, and an AlGaAs ^** layer in which Al atoms and Ga atoms are higher than the stoichiometric ratio may be used for the n-type transistor.

[0128]

According to the present invention, a channel layer in which a channel through which charged particles move is formed, a charged particle supply layer for supplying charged particles to the channel layer, and a band gap smaller than that of the charged particle supply layer. It is a small III-V compound semiconductor, and the III-V compound semiconductor has a stoichiometric ratio of III to III in order to increase the Schottky barrier height.
Since the compound semiconductor layer having a different composition ratio so that the number of group atoms or group V atoms is increased and the gate electrode which is Schottky-junctioned to the compound semiconductor layer are provided, the forward rising voltage is large and the gate leakage current is large. There are few, and it can be operated at high speed.

In the above-described semiconductor device, if the charged particles are electrons and the composition ratio of the compound semiconductor layer is varied so that the group III atoms are increased from the stoichiometric ratio of the group III-V compound semiconductor, the gate leakage current is reduced. Thus, an n-type transistor that operates at high speed can be realized. Further, if the charged particles are holes and the composition ratio of the compound semiconductor layer is shifted from the stoichiometric ratio of the III-V group compound semiconductor so that the group V atoms are increased,
It is possible to realize a p-type transistor that operates at high speed with a small gate leakage current.

According to the present invention, a channel layer in which a channel through which charged particles move is formed, a non-doped semiconductor layer having a band gap larger than that of the channel layer, and a band gap smaller than that of the non-doped semiconductor layer III--
A group V compound semiconductor in which the composition ratio is deviated from the stoichiometric ratio of the group III-V compound semiconductor such that the group III atom or group V atom is increased so that the Schottky barrier height is increased. Since a semiconductor layer, a gate electrode that is Schottky-junctioned to the compound semiconductor layer, and a source region and a drain region that are formed below the region sandwiching the gate electrode and that are doped with impurities are provided, a forward rise is formed. High voltage, low gate leakage current, and high speed operation.

In the above-mentioned semiconductor device, the charged particles are electrons, and the composition ratio of the compound semiconductor layer is shifted from the stoichiometric ratio of the III-V group compound semiconductor so that the group III atoms are increased, and the source region and the drain region are formed. By using the n-type impurity region, it is possible to realize an n-type transistor that operates at high speed with a small gate leakage current. Further, the charged particles are holes, the composition ratio of the compound semiconductor layer is shifted from the stoichiometric ratio of the III-V group compound semiconductor so that the number of group V atoms is large, and the source region and the drain region are p-type impurity regions. If
It is possible to realize an n-type transistor that operates at high speed with a small gate leakage current.

Further, an n-type transistor made of the above-mentioned semiconductor device and a p-type transistor made of the above-mentioned semiconductor device are provided, and the gate electrode of the p-type transistor and the gate electrode of the n-type transistor are commonly connected to each other to form the p-type transistor. By commonly connecting the drain of the transistor and the drain of the n-type transistor, a low power consumption complementary transistor circuit can be realized.

According to the present invention, the step of forming a channel layer in which a channel through which charged particles move is formed, and the step of forming a charged particle supply layer for supplying charged particles to the channel layer on the channel layer. And a compound semiconductor layer having a composition ratio deviated from the stoichiometric ratio of the group III-V compound semiconductor such that the number of group III atoms or group V atoms is increased on the charged particle supply layer under predetermined growth conditions. Since it has a step of forming and a step of forming a gate electrode on the compound semiconductor layer, it is possible to manufacture a semiconductor device which has a large forward rising voltage, a small gate leakage current, and operates at high speed.

According to the present invention, a step of forming a channel layer in which a channel through which charged particles move is formed, and a step of forming a non-doped semiconductor layer having a band gap larger than that of the channel layer on the channel layer. , On the non-doped semiconductor layer, under certain growth conditions, the III
-From the stoichiometric ratio of group V compound semiconductor, group III atom or V
Forming a compound semiconductor layer having a composition ratio shifted so that the number of group atoms increases, forming a gate electrode on the compound semiconductor layer, and adding an impurity using the gate electrode as a mask Since it has a step of forming a source region and a drain region below a region sandwiching electrodes, a semiconductor device which has a large forward rising voltage, a small gate leakage current, and operates at high speed can be manufactured.

In the method of manufacturing a semiconductor device described above,
By controlling the molecular dose of group III atoms and group V atoms as a predetermined growth condition, group III atoms or group V atoms can be effectively controlled.
Group III atoms may be increased, group III atoms or group V atoms may be effectively increased by controlling the growth temperature, or group III atoms may be added after the group III-V compound semiconductor layer is grown. Or by implanting group V atoms by ion implantation, II
The number of group I atoms or group V atoms may be increased.

In the method of manufacturing a semiconductor device described above,
If the second compound semiconductor layer is formed subsequent to the step of forming the charged particle supply layer or the non-doped semiconductor layer, and the compound semiconductor layer is subsequently formed, the charged particle supply layer to the compound semiconductor layer can be continuously formed. Can grow to
The interface of the compound semiconductor layer becomes good.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a process sectional view (1) of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view (2) of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a process sectional view (3) of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a process sectional view (1) of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process sectional view (2) of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a process sectional view (1) of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a process sectional view (2) of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a process sectional view (1) of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a process sectional view (2) of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 16 is a process sectional view (1) of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 17 is a process sectional view (2) of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

[Explanation of symbols]

1 ... III-V compound semiconductor substrate 2P, 2N ... Channel layer 3P ... Hole channel 3N ... Electron channel 4P ... Hole supply layer 4N ... Electron supply layer 5P, 5N ... Compound semiconductor layer 6P ... P-type contact layer 6N ... n-type contact layer 7P, 7N ... Gate electrode 8P, 8N ... Source electrode 9P, 9N ... Drain electrode 10 ... GaAs substrate 11 ... GaAs (AlGaAs) buffer layer 12 ... i-In _0.2 Ga _0.8 As channel layer 13 ... p-Al _0.7 Ga _0.3 As hole supply layer 14 ... GaAs ^* layer 15 ... Al gate electrode 16 ... p-GaAs contact layer 17 ... Au / Zn / Au source electrode 18 ... Au / Zn / Au drain electrode 19 ... GaAs (AlGaAs) buffer Layer 20 ... i-In _0.2 Ga _0.8 As channel layer 21 ... n-Al _0.3 Ga _0.7 As electron supply layer 22 ... G aAs ^** layer 23 ... Al gate electrode 24 ... n-GaAs contact layer 25 ... AuGe / Au drain electrode 26 ... AuGe / Au source electrode 27 ... High resistance region 28 ... SiON interlayer insulating film 29, 30, 31, 32, 33 Ti / Pt / Au wiring layer 40, 41, 42 Mask layer 50 GaAs substrate 51 GaAs (AlGaAs) buffer layer 52 i-In _0.2 Ga _0.8 As channel layer 53 i-Al _0.5 Ga _0.5 As layer 54 ... GaAs ^* layer 55 ... WSi gate electrode 56 ... p ⁺ type source region 57 ... p ⁺ type drain region 58 ... Au / Zn / Au source electrode 59 ... Au / Zn / Au drain electrode 60 ... GaAs ^** layer 61 ... WSi The gate electrode 62 ... n ⁺ -type source region 63 ... n ⁺ -type drain region 64 ... AuGe / Au drain electrode 65 ... AuGe / u source electrode 68 ... SiON interlayer insulating film 69,70,71,72,73 ... Ti / Pt / Au wiring layers 80, 81 ... resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8238 27/092 29/778 21/338 29/812 H01L 21/265 C 27/08 321 A 9171-4M 29 / 80H

Claims (17)

[Claims] 1. A channel layer in which a channel through which charged particles move is formed, a charged particle supply layer for supplying charged particles to the channel layer, and a band gap smaller than the charged particle supply layer III
In a -V compound semiconductor, the composition ratio is deviated from the stoichiometric ratio of the III-V compound semiconductor so that the Schottky barrier height is increased so that the group III atom or the group V atom is increased. A semiconductor device, comprising: a compound semiconductor layer; and a gate electrode Schottky-junctioned to the compound semiconductor layer. 2. The semiconductor device according to claim 1, wherein the charged particles are electrons, and the compound semiconductor layer has a large amount of group III atoms from the stoichiometric ratio of the group III-V compound semiconductor. A semiconductor device having a different composition ratio. 3. The semiconductor device according to claim 1, wherein the charged particles are holes, and the compound semiconductor layer has a large number of group V atoms from the stoichiometric ratio of the group III-V compound semiconductor. A semiconductor device characterized in that the composition ratio is deviated. 4. The semiconductor device according to claim 1, wherein a second compound semiconductor layer having the same conductivity type as the charged particle supply layer is provided between the charged particle supply layer and the compound semiconductor layer. A semiconductor device in which a semiconductor device is inserted. 5. A channel layer in which a channel through which charged particles move is formed, a non-doped semiconductor layer having a band gap larger than that of the channel layer, and a band gap smaller than that of the non-doped semiconductor layer.
In the case of a III-V group compound semiconductor, the composition ratio deviates from the stoichiometric ratio of the III-V group compound semiconductor so that the Schottky barrier height is increased and the number of group III atoms or group V atoms is increased. A compound semiconductor layer, a gate electrode that is Schottky-junctioned to the compound semiconductor layer, and a source region and a drain region that are formed below the region sandwiching the gate electrode and that are doped with impurities. Semiconductor device. 6. The semiconductor device according to claim 5, wherein the charged particles are electrons, and the compound semiconductor layer has a large amount of group III atoms from the stoichiometric ratio of the group III-V compound semiconductor. A semiconductor device, wherein composition ratios are different, and the source region and the drain region are n-type impurity regions. 7. The semiconductor device according to claim 5, wherein the charged particles are holes, and the compound semiconductor layer has a large number of group V atoms from the stoichiometric ratio of the group III-V compound semiconductor. The semiconductor device is characterized in that the source region and the drain region are p-type impurity regions. 8. An n-type transistor including the semiconductor device according to claim 2 or 6, and a p-type transistor including the semiconductor device according to claim 3 or 7, wherein a gate electrode of the p-type transistor and the n-type transistor are provided. A semiconductor device in which a gate electrode of a transistor is commonly connected, and a drain of the p-type transistor and a drain of the n-type transistor are commonly connected. 9. A step of forming a channel layer in which a channel through which charged particles move is formed; a step of forming a charged particle supply layer for supplying charged particles to the channel layer on the channel layer; On the particle supply layer, according to the predetermined growth conditions,
Forming a compound semiconductor layer having a composition ratio different from the stoichiometric ratio of the III-V compound semiconductor so that the number of group III atoms or group V atoms is large; and forming a gate electrode on the compound semiconductor layer A method of manufacturing a semiconductor device, comprising: 10. A step of forming a channel layer in which a channel through which charged particles move is formed, a step of forming a non-doped semiconductor layer having a band gap larger than that of the channel layer on the channel layer, and the non-doped semiconductor. On the layer, according to the predetermined growth conditions,
Forming a compound semiconductor layer having a composition ratio different from the stoichiometric ratio of the group III-V compound semiconductor so that the number of group III atoms or group V atoms is large; and forming a gate electrode on the compound semiconductor layer A method of manufacturing a semiconductor device, comprising: a step of forming a source region and a drain region below a region sandwiching the gate electrode by adding an impurity using the gate electrode as a mask. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the predetermined growth condition is effective by controlling the molecular doses of group III atoms and group V atoms so that group III atoms or group V atoms can be effectively used.
A method for manufacturing a semiconductor device, characterized in that the number of group atoms is increased. 12. The method for manufacturing a semiconductor device according to claim 9, wherein the predetermined growth condition is to effectively increase the number of group III atoms or group V atoms by controlling the growth temperature. And a method for manufacturing a semiconductor device. 13. The method of manufacturing a semiconductor device according to claim 9, wherein the predetermined growth condition is that after a group III-V compound semiconductor layer is grown, a group III atom or a group V atom is ion-implanted. A method for manufacturing a semiconductor device, characterized in that the number of group III atoms or group V atoms is effectively increased. 14. The method for manufacturing a semiconductor device according to claim 9, wherein a second compound semiconductor layer is formed subsequent to the step of forming the charged particle supply layer or the non-doped semiconductor layer,
A method of manufacturing a semiconductor device, characterized in that the compound semiconductor layer is subsequently formed. 15. The method of manufacturing a semiconductor device according to claim 9, wherein a step of forming a contact layer on the compound semiconductor layer, and recess etching of a gate electrode formation region of the contact layer. And a step of exposing the compound semiconductor layer, wherein the gate electrode is formed on the exposed compound semiconductor layer. 16. The method of manufacturing a semiconductor device according to claim 9, wherein the charged particle supply layer or the non-doped semiconductor layer comprises:
A step of forming a contact layer, and a step of recess etching the gate electrode formation region of the contact layer to expose the charged particle supply layer or the non-doped semiconductor layer, wherein the compound semiconductor layer is exposed A method of manufacturing a semiconductor device, comprising forming the charged particle supply layer or the non-doped semiconductor layer. 17. The method of manufacturing a semiconductor device according to claim 9, wherein the compound semiconductor layer is patterned so that only a gate electrode formation region remains, the compound semiconductor layer and the charged particles. On the supply layer or on the non-doped semiconductor layer, a step of forming a contact layer, and a step of recess etching the gate electrode forming region of the contact layer to expose the compound semiconductor layer, the gate electrode, A method of manufacturing a semiconductor device, comprising forming on the exposed compound semiconductor layer.