JPH08139271A - Semiconductor device - Google Patents

Abstract

PURPOSE: To enable easy control of an applied voltage and high precision resistance without enlarging a formation space of a dummy element by providing a means for applying a voltage for controlling channel formation immediately below polysilicon independently to each polysilicon. CONSTITUTION: Each of a plurality of impurity diffusion layers is separated by polysilicon and is provided on a semiconductor substrate as a resistance element of a semiconductor circuit element. For example, when three resistors are separated by two polysilicon gates 3, a central resistor R1 of three diffusion layer resistors 2 is completely separated from other resistors by a gate whose both ends are fixed to Vcc. A node of both ends of the resistor R1 is connected to nodes A, B respectively through a contact hole 1 from the diffusion layer 2. Especially, a means for applying a voltage for controlling channel formation immediately below polysilicon is provided independently to each polysilicon. Thereby, it is possible to connect adjacent diffusion layer resistors 2 parallel mutually through polysilicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device (hereinafter referred to as I
Regarding C), particularly, an analog IC or an analog IC whose characteristics are determined by the accuracy of the resistance value built in the IC.
The present invention relates to a technique effectively applied to a digital mixed IC.

[0002]

2. Description of the Related Art In recent years, high integration and high functionality of ICs have been remarkable, and in particular, in analog ICs and mixed analog-digital ICs, very high precision is required for internally generated voltages, currents, frequency components and the like. , High precision resistors are needed to generate them.

Generally, in analog ICs and analog-digital mixed ICs, the resistance of the impurity diffusion layer (hereinafter referred to as diffusion layer resistance) is widely used as the resistance.
There is a limit to the accuracy of the diffusion layer resistance,
It is not uncommon to look at the evaluation results of the completed IC and review the resistance value and remake it.

For this reason, when reviewing the resistance value of the diffusion layer resistance, conventionally, a plurality of dummy elements of the diffusion layer resistance are closely embedded in advance and the wiring layer (AL wiring, contact hole, etc.) is corrected. The resistance value of the diffusion layer resistance was varied by connecting to a dummy element having the optimum resistance value, and a highly accurate resistance was obtained.

Further, by separating the two diffusion layers with polysilicon and applying a voltage to the polysilicon,
It has been possible to obtain a highly accurate resistance by controlling the channel formation directly under the polysilicon and varying the resistance value between the two diffusion layers.

(Latest Illustrated Semiconductor Guide, Seibundo Shinkosha)
(See P62 and P63)

[0007]

DISCLOSURE OF THE INVENTION The present inventors have found the following problems as a result of examining the above prior art.

Conventionally, a dummy element is embedded in advance, the wiring layer is modified and connected to a dummy element having an optimum resistance value, and the resistance value of the diffusion layer resistance is varied to obtain a highly accurate resistance. However, in particular, in the case of obtaining a highly accurate resistance as in an analog IC, it is necessary to make many dummy elements, and there is a problem that the dummy element forming space becomes large.

Further, since the resistance value variation in the resistance using the channel control of polysilicon depends on 100% applied voltage, a highly accurate resistance can be obtained due to manufacturing variations of diffusion layers, applied voltage variations, and the like. Therefore, it is difficult to control the applied voltage.

An object of the present invention is to provide a technique capable of easily controlling an applied voltage and obtaining a highly accurate resistance without increasing a space for forming a dummy element.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

A semiconductor device in which a semiconductor circuit element is formed on a semiconductor substrate, and a plurality of impurity diffusion layers are provided on the semiconductor substrate as polysilicon resistors are separated by polysilicon as resistance elements of the semiconductor circuit element. A control voltage applying unit for applying a voltage for controlling the channel formation directly below the polysilicon is independently provided for each polysilicon.

[0014]

According to the above means, a semiconductor circuit element is formed on a semiconductor substrate, and a plurality of impurity diffusion layers are provided on the semiconductor substrate as resistance elements of the semiconductor circuit element, each of which is separated by polysilicon. In the semiconductor device, the control voltage applying means for applying a voltage for controlling the channel formation directly under the polysilicon is independently provided for each polysilicon, so that the control voltage is applied to each of the plurality of polysilicons. Depending on the control voltage, it is possible to connect adjacent diffusion layer resistors in parallel via polysilicon depending on whether or not a channel directly under the polysilicon can be formed, and the resistance value can be changed by combining more than the number of conventional dummy elements. Therefore, it is possible to obtain a highly accurate resistance.

Further, since the resistance value is changed by the combination of the diffusion layer resistances, the resistance value can be changed without depending on 100% voltage control, and the applied voltage can be easily controlled, so that a highly accurate resistance can be obtained. Is possible.

The structure of the present invention will be described below together with embodiments.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining a diffusion layer resistance in a semiconductor device which is an embodiment of the present invention.

In FIG. 1, 1 is a contact hole and 2 is a contact hole.
Is a diffusion layer resistance (P type diffusion layer) formed by doping impurities, 3 is a polysilicon gate, R1 is nodes A and B
The resistance between them is shown respectively.

In the semiconductor device of this embodiment shown in FIG. 1A, the diffusion layer resistor 2 is connected to the Locos (Local Oxidation of).
Silicon) and each isolation is realized by self-alignment of the polysilicon gate 3.

In FIG. 1A, the case where three resistors are separated by two polysilicon gates 3 is taken up.

Then, the two polysilicon gates 3
Are electrically connected to the electrode pads padA and B that are electrically connected.

At this time, a voltage which cannot be used as a channel is applied to the gate immediately below the gate (here, Vcc),
The P type diffusion layer 2 is divided into three P type diffusion layer resistors.

In FIG. 1 (A), of the three P-type diffusion layer resistors, the central resistor R1 is completely separated from the other resistors by a gate fixed to Vcc on both sides, and the resistor R1 is separated. The nodes at both ends are respectively connected to the nodes A and B by aluminum wiring from the diffusion layer through contact holes (interlayer film drilling).

FIG. 1B is a sectional view taken along line XX shown in FIG.

As shown in FIG. 1B, the semiconductor device of this embodiment is provided with two polysilicon gates 3 which divide the P-type diffusion layer 2 surrounded by Locos into three.

Next, a method of varying the value of the resistance R1 between the nodes A and B in the semiconductor device of this embodiment described above will be described.

FIG. 1C shows a structure in which a GND level voltage is applied to padA of the electrode pads padA and B electrically connected to the two polysilicon gates 3 shown in FIG. Is.

As shown in FIG. 1C, when the voltage level of padA is changed from Vcc to GND, a channel is formed immediately below the gate connected to it, whereby the above-mentioned R1 is provided between nodes A and B. In addition, a resistance component R3 in which a resistance component R3 due to the diffusion layer on the right side and a component of an ON resistance (this resistance has almost the same structure as that of Mos) R2 directly under the gate are connected in parallel appears (R at this time). , R1, R2, R3 have a relationship of 1 / R = 1 / R ₁ +1
/ R ₂ + 1 / R ₃ ).

Therefore, in this embodiment, by changing the potential of the gate on the padA side from Vcc to GND, the resistance value between the nodes A and B is lowered and can be made variable.

Similarly, the same applies to padB. Further, although the P-type diffusion layer 2 is separated into three in the present embodiment, a large number of the P-type diffusion layers 2 are two-dimensionally expanded and separated. The resistance value between the nodes A and B can be made analog variable by voltage control to some pads.

The variable diffusion layer resistance in the semiconductor device shown in FIG. 1C uses the limited voltage value of the control signals (Vcc, GND) generated inside the semiconductor device. , B are provided outside the semiconductor device, and the ON resistance R2 shown in FIG. 1C is controlled by voltage control from the outside, and the diffusion layer resistance can be changed to a desired value with high precision.

Next, FIG. 2 will be described with reference to an example of a system using the variable resistance value of the diffusion layer in the semiconductor device of this embodiment shown in FIG.

As shown in FIG. 2, the diffusion layer resistance R described above is used.
1 and the reference resistor R are connected in series between Vcc and GND, and the node between these resistors is connected to the VREF source (reference voltage generation BLo).
CK) output and VCO20 (Voltage Controled Oscr
The system used as the reference power source of the ator) will be mentioned.

The system configuration shown in FIG. 2 is a PLL.
(Phase-Locked Loop) 22 calculates a reference frequency and Vco output frequency, and the output is converted to an analog level voltage value by a DAC (D / A Convertor) and input to Vco.

When it is determined that the calculation result in the PLL is far from locking the PLL, it is sent to the diffusion layer resistor R1 in VREF as a control signal,
This changes the resistance ratio in VREF and changes the output voltage.

By sending the changed voltage to Vco, the operation speed in the loop circuit is improved.

Further, the present invention is not limited to such a system, but can be applied to a PLL synthesizer used for a radio telephone or the like, a hard disk driver for specifying an oscillation frequency, and the like.

As described above, a semiconductor circuit element is formed on a semiconductor substrate, and a plurality of impurity diffusion layers are provided on the semiconductor substrate as resistance elements of the semiconductor circuit element, separated by polysilicon. In the semiconductor device, the control voltage applying means for applying a voltage for controlling the channel formation directly under the polysilicon is independently provided for each polysilicon, so that the control voltage is applied to each of the plurality of polysilicons. Depending on the control voltage, it is possible to connect adjacent diffusion layer resistors in parallel via polysilicon depending on whether or not a channel directly under the polysilicon can be formed, and the resistance value can be changed by combining more than the number of conventional dummy elements. Therefore, it is possible to obtain a highly accurate resistance without increasing the formation space of the dummy element.

Further, since the resistance value is changed by the combination of the diffusion layer resistances, the resistance value can be changed without depending on 100% voltage control, and the applied voltage can be easily controlled, so that a highly accurate resistance can be obtained. Is possible.

Further, according to the present invention, since the diffusion layer resistance is varied by voltage control, the level can be easily changed even when two or more power sources are shared in the semiconductor device including the system shown in FIG. In addition, it is possible to change the product of 5V to the product of 3.3V.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0043]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

A control voltage can be applied to each of a plurality of polysilicons, and it is possible to connect adjacent diffusion layer resistors in parallel with each other via polysilicon depending on whether or not a channel directly below the polysilicon can be formed by the control voltage. Since the resistance value can be changed by combining more than the number of conventional dummy elements, and the resistance value can be changed by the combination of diffusion layer resistors, the resistance value can be changed without depending on 100% voltage control. It becomes possible to easily control the applied voltage and to obtain a highly accurate resistance without increasing the space for forming.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a diffusion layer resistance in a semiconductor device that is an embodiment of the present invention.

FIG. 2 is a diagram showing a system example using variable diffusion layer resistance values in the semiconductor device of the present embodiment.

[Explanation of symbols]

1 ... Contact hole, 2 ... P-type diffusion layer, 3 ... Polysilicon gate, R1 ... Resistance between nodes A and B (diffusion layer resistance), R2 ... ON resistance, R3 ... Diffusion layer resistance, 20 ... VC
O, 21 ... DAC, 22 ... PLL.

Claims (3)

[Claims] 1. A semiconductor device in which a semiconductor circuit element is formed on a semiconductor substrate, and a plurality of impurity diffusion layers are provided on the semiconductor substrate as polysilicon elements separated by polysilicon, respectively, as resistance elements of the semiconductor circuit element. A semiconductor device, characterized in that each polysilicon is independently provided with a control voltage applying means for applying a voltage for controlling the channel formation directly below the polysilicon. 2. The semiconductor device according to claim 1, wherein the control voltage applying unit applies a control signal generated inside the semiconductor device to the polysilicon. 3. The semiconductor device according to claim 1, wherein the control voltage applying unit is provided with an external electrode electrically connected to the polysilicon, and a control voltage from the outside of the semiconductor device is applied to the external electrode. A semiconductor device characterized by being applied.