JPH08139240A - Method for mounting semiconductor element - Google Patents

Method for mounting semiconductor element

Info

Publication number
JPH08139240A
JPH08139240A JP27197594A JP27197594A JPH08139240A JP H08139240 A JPH08139240 A JP H08139240A JP 27197594 A JP27197594 A JP 27197594A JP 27197594 A JP27197594 A JP 27197594A JP H08139240 A JPH08139240 A JP H08139240A
Authority
JP
Japan
Prior art keywords
semiconductor element
flat plate
attached
conductive flat
heat conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27197594A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kono
一博 河野
Yusuke Ito
祐介 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GE Healthcare Japan Corp
Original Assignee
GE Yokogawa Medical System Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GE Yokogawa Medical System Ltd filed Critical GE Yokogawa Medical System Ltd
Priority to JP27197594A priority Critical patent/JPH08139240A/en
Publication of JPH08139240A publication Critical patent/JPH08139240A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To achieve a method for mounting a semiconductor element where a heat sink can be mounted while maintaining the flatness of the semiconductor element without requiring an exclusive tool or operation when soldering a plurality of semiconductor elements to a circuit substrate and mounting the heat sink. CONSTITUTION: A semiconductor element is mounted on one surface of a flat plate of thermal conductor (Step 1), the electrode lead of the semiconductor element is connected to a circuit substrate which is laid out with a specific space to the thermally conductive flat plate via solder (Step 3), and a heat sink is mounted to the other surface of the thermally conductive flat plate (Step 4).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は放熱板が取り付けられる
半導体素子の実装方法に関し、更に詳しくは、複数の半
導体素子を回路基板に取り付けた際の各半導体素子の平
面度の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor element on which a heat dissipation plate is attached, and more particularly to improving the flatness of each semiconductor element when a plurality of semiconductor elements are attached to a circuit board.

【0002】[0002]

【従来の技術】電源装置や増幅装置の出力段に用いる半
導体素子(ダイオード,トランジスタ,FET等)には
放熱板が取り付けられていることが多い。
2. Description of the Related Art A heat sink is often attached to a semiconductor element (diode, transistor, FET, etc.) used in an output stage of a power supply device or an amplifier.

【0003】このような場合の半導体素子の実装方法に
ついて、図4を参照して手順を説明する。ここでは、L
字形に折り曲げられた電極リード(以下、単にリードと
言う)を備えた半導体素子をLMT(LEAD MOUNT TECHN
OLOGY:リード穴挿入実装技術)により回路基板に取り付
ける場合を考える。また、ここでは説明を簡単にするた
めに、3個の半導体素子を回路基板に取り付ける場合を
想定するが、半導体素子の個数はこれに限定されるもの
ではない。
A procedure for mounting the semiconductor element in such a case will be described with reference to FIG. Here, L
LMT (LEAD MOUNT TECHN) is a semiconductor device equipped with electrode leads bent in a letter shape (hereinafter simply referred to as leads).
OLOGY: Lead hole insertion mounting technology). Further, here, in order to simplify the description, it is assumed that three semiconductor elements are attached to the circuit board, but the number of semiconductor elements is not limited to this.

【0004】半導体素子21,22,23はそれぞれリ
ード21a,22a,23aを備えている。そして、こ
れらのリードを折り曲げてそれぞれを回路基板10のリ
ード穴(以下、単に穴と言う)11b,12b,13b
に挿入する。
The semiconductor elements 21, 22, 23 have leads 21a, 22a, 23a, respectively. Then, these leads are bent to form lead holes (hereinafter, simply referred to as holes) 11b, 12b, 13b of the circuit board 10.
To insert.

【0005】各リードが穴に挿入されると、各半導体素
子が破線Aにおいて平面となるように押さえつけた状態
で各リード21a,22a,23aの先端部分とパター
ン11a,12a,13aとがはんだ付けされる。この
ようなリード付き部品のはんだ付けは、一般にフロー・
ソルダリング等の自動はんだ付け装置により行われる。
When the respective leads are inserted into the holes, the tip portions of the leads 21a, 22a, 23a and the patterns 11a, 12a, 13a are soldered while the semiconductor elements are pressed so as to be flat on the broken line A. To be done. Soldering of such leaded components is generally
It is performed by an automatic soldering device such as soldering.

【0006】最後に、各半導体素子21〜23のそれぞ
れについて、ねじ31〜33を用いて放熱板40に取り
付けるようにする。
Finally, each of the semiconductor elements 21 to 23 is attached to the heat dissipation plate 40 by using screws 31 to 33.

【0007】[0007]

【発明が解決しようとする課題】以上のような半導体素
子の実装におけるはんだ付けにおいては、放熱板40を
取り付けるために破線Aの平面度を保つことが極めて重
要である。この平面度が保たれることで半導体素子と放
熱板40との接触状態が良好になり、放熱の効率が一定
になるからである。
In the soldering for mounting the semiconductor element as described above, it is extremely important to maintain the flatness of the broken line A in order to attach the heat sink 40. This is because maintaining the flatness improves the contact state between the semiconductor element and the heat dissipation plate 40 and makes the heat dissipation efficiency constant.

【0008】しかし、複数の半導体素子を実装する際に
は、はんだ付けの段階において破線Aの平面度を維持す
ることが極めて困難である。従って、はんだ付けの際に
破線Aの平面度を維持するための専用の治具を用いて複
数の半導体素子を押さえつけるような作業が必要になっ
ている。
However, when mounting a plurality of semiconductor elements, it is extremely difficult to maintain the flatness of the broken line A at the soldering stage. Therefore, it is necessary to hold down a plurality of semiconductor elements by using a dedicated jig for maintaining the flatness of the broken line A during soldering.

【0009】本発明は上記問題を解決するためになされ
たもので、その目的は、複数の半導体素子を回路基板に
はんだ付けして放熱板を取り付ける際に、専用の治具や
作業を必要とせずに半導体素子の平面度を維持して放熱
板を取り付けることが可能な半導体素子の実装方法を実
現することである。
The present invention has been made to solve the above problems, and an object thereof is to require a dedicated jig or work when mounting a heat sink by soldering a plurality of semiconductor elements to a circuit board. It is another object of the present invention to realize a mounting method of a semiconductor element, which can attach a heat sink while maintaining the flatness of the semiconductor element.

【0010】[0010]

【課題を解決するための手段】前記の課題を解決する第
1の手段は、半導体素子を熱伝導性平板の一方の面に取
り付け、前記熱伝導性平板と所定の間隔を有するように
配置された回路基板に前記半導体素子の電極リードをは
んだを介して接続し、前記熱伝導性平板の他方の面に放
熱板を取り付けることを特徴とする半導体素子の実装方
法である。
A first means for solving the above-mentioned problems is to mount a semiconductor element on one surface of a heat-conductive flat plate, and arrange the semiconductor element so as to have a predetermined distance from the heat-conductive flat plate. An electrode lead of the semiconductor element is connected to the circuit board via solder, and a heat dissipation plate is attached to the other surface of the heat conductive flat plate.

【0011】前記の課題を解決する第2の手段は、半導
体素子を熱伝導性平板の一方の面にネジを用いて取り付
け、前記熱伝導性平板と所定の間隔を有するように配置
された回路基板に前記半導体素子の電極リードをはんだ
を介して接続し、前記熱伝導性平板の他方の面に、前記
半導体素子を前記熱伝導性平板に対して取り付けたネジ
を用いて放熱板を取り付けることを特徴とする半導体素
子の実装方法である。
A second means for solving the above-mentioned problems is to mount a semiconductor element on one surface of a heat conductive flat plate by using a screw and to arrange the circuit so as to have a predetermined distance from the heat conductive flat plate. The electrode lead of the semiconductor element is connected to the substrate through the solder, and the heat dissipation plate is attached to the other surface of the heat conductive flat plate by using the screw for attaching the semiconductor element to the heat conductive flat plate. Is a method of mounting a semiconductor element.

【0012】[0012]

【作用】課題を解決する第1の手段である半導体素子の
実装方法では、まず半導体素子が熱伝導性平板の一方の
面に取り付けられ、次に前記熱伝導性平板と所定の間隔
を有するように配置された回路基板に前記半導体素子の
電極リードがはんだを介して接続され、そして前記熱伝
導性平板の他方の面に放熱板が取り付けられる。これに
より、複数の半導体素子を回路基板にはんだ付けして放
熱板を取り付ける際に、専用の治具や作業を必要とせず
に半導体素子の平面度を維持して放熱板を取り付けるこ
とが可能になる。
In the method for mounting a semiconductor element, which is the first means for solving the problems, the semiconductor element is first attached to one surface of the heat conductive flat plate, and then has a predetermined distance from the heat conductive flat plate. The electrode lead of the semiconductor element is connected to the circuit board arranged on the substrate via solder, and a heat radiating plate is attached to the other surface of the heat conductive flat plate. This makes it possible to attach the heat sink while maintaining the flatness of the semiconductor elements without the need for a special jig or work when soldering multiple semiconductor elements to the circuit board and attaching the heat sink. Become.

【0013】課題を解決する第2の手段である半導体素
子の実装方法では、まず半導体素子が熱伝導性平板の一
方の面にネジを用いて取り付けられ、次に前記熱伝導性
平板と所定の間隔を有するように配置された回路基板に
前記半導体素子の電極リードがはんだを介して接続さ
れ、そして前記熱伝導性平板の他方の面に、前記半導体
素子が前記熱伝導性平板に対して取り付けたネジを用い
て放熱板に取り付けられる。これにより、複数の半導体
素子を回路基板にはんだ付けして放熱板を取り付ける際
に、専用の治具や作業を必要とせずに半導体素子の平面
度を維持して放熱板を取り付けることが可能になる。
In a semiconductor element mounting method which is a second means for solving the problem, the semiconductor element is first attached to one surface of the heat conductive flat plate by using a screw, and then the heat conductive flat plate and a predetermined surface are mounted. The electrode leads of the semiconductor element are connected to the circuit board arranged so as to have a gap via solder, and the semiconductor element is attached to the heat conductive plate on the other surface of the heat conductive plate. It is attached to the heat sink using the screws. This makes it possible to attach the heat sink while maintaining the flatness of the semiconductor elements without the need for a special jig or work when soldering multiple semiconductor elements to the circuit board and attaching the heat sink. Become.

【0014】[0014]

【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図1は本発明の一実施例の半導体素子の実
装方法を示すフローチャートである。図2は本実施例の
半導体素子の実装方法によって取り付けを行った様子を
示す断面構成図である。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a flowchart showing a method of mounting a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional configuration diagram showing a state in which the semiconductor element is mounted by the mounting method according to this embodiment.

【0015】ここでは、説明を簡単にするために、半導
体素子(ダイオード,トランジスタ,FET)の数が3
である場合を例にして説明する。但し、実際には、半導
体素子の数はこれに限られるものではない。また、半導
体素子21〜23はリード付き部品であるものとし、L
MT(リード穴挿入実装技術)により各リードと回路基
板10のパターンとがはんだ付けで接続される。また、
各半導体素子21〜23は放熱板にネジ止めするための
穴21b〜23bを有している。
Here, in order to simplify the explanation, the number of semiconductor elements (diodes, transistors, FETs) is three.
Will be described as an example. However, in reality, the number of semiconductor elements is not limited to this. Further, the semiconductor elements 21 to 23 are assumed to be leaded parts, and L
Each lead and the pattern of the circuit board 10 are connected by soldering by MT (lead hole insertion mounting technique). Also,
Each of the semiconductor elements 21 to 23 has holes 21b to 23b for screwing to the heat dissipation plate.

【0016】ここで、図1及び図2を参照して、本実施
例の半導体素子の実装方法を手順に従って説明する。ま
ず、半導体素子21〜23を伝熱性平板としての銅板5
0上に載置する(図2(a))。尚、この銅板50は、
半導体素子21〜23の穴21b〜23bに対応した位
置にネジ穴51a〜53aを備えているものとする。そ
して、それぞれの穴の位置をあわせた状態でネジ31〜
33により半導体素子21〜23を銅板50に取り付け
る(図1ステップ)。尚、必要に応じてシリコングリ
ス等を塗布しておく。
Here, with reference to FIGS. 1 and 2, a method of mounting the semiconductor device of this embodiment will be described in accordance with procedures. First, the semiconductor element 21-23 is a copper plate 5 as a heat conductive flat plate.
0 (FIG. 2 (a)). The copper plate 50 is
It is assumed that the semiconductor elements 21 to 23 have screw holes 51a to 53a at positions corresponding to the holes 21b to 23b. Then, with the positions of the holes aligned, screws 31 to 31
The semiconductor elements 21 to 23 are attached to the copper plate 50 by 33 (step in FIG. 1). If necessary, silicon grease or the like is applied.

【0017】この実施例で用いる銅板50が構成する伝
熱性平板は、各半導体素子と後述する放熱板との間で平
面度を維持しつつ、放熱を行うものである。従って、取
り付け段階においては平面度を維持する治具としての役
割を持ち、実装完了後は放熱板としての役割を果たすも
のである。このため、熱伝導度の高い材質が好ましく、
一般には銅やアルミで構成することが好適である。ただ
し、これ以外でも熱伝導度が高いものであれば、金属に
限らず用いることは可能である。
The heat conductive flat plate formed by the copper plate 50 used in this embodiment radiates heat while maintaining flatness between each semiconductor element and a heat radiating plate which will be described later. Therefore, it has a role as a jig for maintaining the flatness in the mounting stage, and a role as a heat dissipation plate after the mounting is completed. Therefore, a material with high thermal conductivity is preferable,
Generally, it is preferable to use copper or aluminum. However, other than this, as long as it has high thermal conductivity, it is possible to use not only metal but also metal.

【0018】次に、スペーサ61,62を用いて銅板5
0と所定の間隔を維持するようにして、また、穴11b
〜13bにリード21a〜23aを挿入するようにして
回路基板10を取り付け固定する(図1ステップ,図
2(b))。
Next, the copper plate 5 is formed by using the spacers 61 and 62.
0 and a predetermined distance are maintained, and the hole 11b
The circuit board 10 is attached and fixed so that the leads 21a to 23a are inserted into the electrodes 13a to 13b (FIG. 1 step, FIG. 2B).

【0019】そして、回路基板10の各パターン11a
〜13aと各リード21a〜23aとをはんだ付けによ
り接続する(図1ステップ,図2(c))。この各半
導体素子21〜23はスペーサ61,62で固定された
銅板50に既に取り付けられているので、複数の半導体
素子の間で平面度を維持するために専用の治具や押さえ
つけの作業は不要になる。従って、容易にはんだ付けが
行える。ここでは、フロー・ソルダリング等の各種のは
んだ付けが可能である。
Then, each pattern 11a of the circuit board 10
13a and the leads 21a to 23a are connected by soldering (FIG. 1 step, FIG. 2C). Since each of the semiconductor elements 21 to 23 is already attached to the copper plate 50 fixed by the spacers 61 and 62, no dedicated jig or pressing work is required to maintain the flatness between the plurality of semiconductor elements. become. Therefore, soldering can be easily performed. Various types of soldering such as flow soldering are possible here.

【0020】このはんだ付け完了後、放熱板40の取り
付けを行う。銅板50の半導体素子21〜23が取り付
けられた面と反対面に、必要に応じて絶縁シート70を
挟んだ状態で放熱板40を取り付ける(図1ステップ
,図2(d))。この段階では、銅板50と放熱板4
0との間の取り付けであるので、平面度については全く
問題がない。従って、熱伝導についても部分的なムラや
ばらつきが生じることはない。また、平面同士の取り付
けであるので、作業効率も著しく改善される。尚、この
銅板50と放熱板40との取り付けは、図示しない端部
でネジ止め等により行われる。
After the soldering is completed, the heat sink 40 is attached. The heat sink 40 is attached to the surface of the copper plate 50 opposite to the surface on which the semiconductor elements 21 to 23 are attached, with the insulating sheet 70 sandwiched as necessary (FIG. 1 step, FIG. 2D). At this stage, the copper plate 50 and the heat sink 4
Since it is mounted between 0 and 0, there is no problem in terms of flatness. Therefore, there is no partial unevenness or variation in heat conduction. Further, since the flat surfaces are attached to each other, work efficiency is significantly improved. The copper plate 50 and the heat sink 40 are attached to each other by screwing or the like at an end (not shown).

【0021】図3はこの銅板50と放熱板40との取り
付けの他の例を示す断面構成図である。前述の例では取
り付け用のネジを用いるとしたが、各半導体素子を銅板
50に止めるネジとして銅板及び半導体素子の厚みより
も長いネジを用いる(若しくは薄い銅板を用いる)よう
にして、銅板には穴を設けておいて一体にネジ止めする
ことも可能である。このように一体にネジ止めすること
で、半導体素子,銅板,放熱板の密着度が更に高まる利
点も生じる。ただし、半導体素子と銅板とを取り付けた
状態で一度ネジ止めし、放熱板を取り付ける段階でネジ
をいったん緩めて再度締め直す必要がある。尚、この場
合、はんだ付けの際には、ナット等で半導体素子と銅板
とを仮止めしておくことも可能である。
FIG. 3 is a sectional view showing another example of how the copper plate 50 and the heat sink 40 are attached. Although the mounting screws are used in the above-described example, the screws that are longer than the thickness of the copper plate and the semiconductor device are used as the screws for fixing each semiconductor element to the copper plate 50 (or a thin copper plate is used). It is also possible to provide holes and screw them together. By integrally screwing in this manner, there is an advantage that the degree of adhesion between the semiconductor element, the copper plate, and the heat dissipation plate is further increased. However, it is necessary to fix the semiconductor element and the copper plate with screws once, and loosen the screws and re-tighten at the stage of mounting the heat sink. In this case, it is possible to temporarily fix the semiconductor element and the copper plate with a nut or the like at the time of soldering.

【0022】以上詳細に説明したように、半導体素子を
熱伝導性平板の一方の面に取り付け、前記熱伝導性平板
と所定の間隔を有するように配置された回路基板に前記
半導体素子の電極リードをはんだを介して接続し、前記
熱伝導性平板の他方の面に放熱板を取り付ける半導体素
子の実装方法によれば、複数の半導体素子を回路基板に
はんだ付けした後に放熱板を取り付ける際に既に平面度
が確保されているので、専用の治具や作業を必要とせず
に半導体素子の平面度を維持して放熱板を取り付けるこ
とが可能になる。
As described in detail above, the semiconductor element is attached to one surface of the heat conductive flat plate, and the electrode lead of the semiconductor element is mounted on the circuit board arranged so as to have a predetermined distance from the heat conductive flat plate. According to the mounting method of the semiconductor element in which the heat radiating plate is attached to the other surface of the heat conductive flat plate by connecting via the solder, when the heat radiating plate is already attached when the plurality of semiconductor elements are soldered to the circuit board, Since the flatness is ensured, the heat dissipation plate can be attached while maintaining the flatness of the semiconductor element without requiring a dedicated jig or work.

【0023】また、半導体素子を熱伝導性平板の一方の
面にネジを用いて取り付け、前記熱伝導性平板と所定の
間隔を有するように配置された回路基板に前記半導体素
子の電極リードをはんだを介して接続し、前記熱伝導性
平板の他方の面に、前記半導体素子を前記熱伝導性平板
に対して取り付けたネジを用いて放熱板を取り付ける半
導体素子の実装方法によれば、複数の半導体素子を回路
基板にはんだ付けした後に放熱板を取り付ける際に既に
平面度が確保されているので、専用の治具や作業を必要
とせずに半導体素子の平面度を維持して放熱板を取り付
けることが可能になり、共通のネジで熱伝導性平板と放
熱板とが取り付けられているので放熱効率が向上する。
Further, the semiconductor element is attached to one surface of the heat conductive flat plate by using screws, and the electrode leads of the semiconductor element are soldered to the circuit board arranged so as to have a predetermined distance from the heat conductive flat plate. According to the mounting method of the semiconductor element, the heat radiating plate is attached to the other surface of the heat conductive flat plate by using a screw that attaches the semiconductor element to the heat conductive flat plate. Since the flatness is already secured when mounting the heat sink after soldering the semiconductor element to the circuit board, the heat sink is mounted while maintaining the flatness of the semiconductor element without the need for a dedicated jig or work. Since the heat conductive flat plate and the heat radiating plate are attached with a common screw, the heat radiating efficiency is improved.

【0024】[0024]

【発明の効果】以上詳細に説明したように、本発明の半
導体素子の実装方法では、まず半導体素子が熱伝導性平
板の一方の面に取り付けられ、次に前記熱伝導性平板と
所定の間隔を有するように配置された回路基板に前記半
導体素子の電極リードがはんだを介して接続され、そし
て前記熱伝導性平板の他方の面に放熱板が取り付けられ
る。これにより、複数の半導体素子を回路基板にはんだ
付けして放熱板を取り付ける際に、専用の治具や作業を
必要とせずに半導体素子の平面度を維持して放熱板を取
り付けることが可能になる。
As described in detail above, in the method of mounting a semiconductor element of the present invention, the semiconductor element is first attached to one surface of the heat conductive flat plate, and then the heat conductive flat plate and the predetermined distance from each other. The electrode leads of the semiconductor element are connected to the circuit board arranged so as to have solder via solder, and a heat radiating plate is attached to the other surface of the heat conductive flat plate. This makes it possible to attach the heat sink while maintaining the flatness of the semiconductor elements without the need for a special jig or work when soldering multiple semiconductor elements to the circuit board and attaching the heat sink. Become.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体素子の実装手
順を示すフローチャートである。
FIG. 1 is a flowchart showing a mounting procedure of a semiconductor element in an embodiment of the present invention.

【図2】本発明の一実施例で用いられる半導体素子の構
成を示した構成図である。
FIG. 2 is a configuration diagram showing a configuration of a semiconductor device used in an embodiment of the present invention.

【図3】本発明の一実施例で用いられる半導体素子の構
成を示した構成図である。
FIG. 3 is a configuration diagram showing a configuration of a semiconductor device used in an embodiment of the present invention.

【図4】従来の半導体素子の実装方法の構成例を示す構
成図である。
FIG. 4 is a configuration diagram showing a configuration example of a conventional semiconductor element mounting method.

【符号の説明】[Explanation of symbols]

10 回路基板 11a〜13a パターン 11b〜13b 穴 21〜23 半導体素子 21a〜23a リード 31〜33 ネジ 40 放熱板 50 銅板 61,62 スペーサ 70 絶縁シート 10 circuit board 11a-13a pattern 11b-13b hole 21-23 semiconductor element 21a-23a lead 31-33 screw 40 heat sink 50 copper plate 61,62 spacer 70 insulating sheet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を熱伝導性平板の一方の面に
取り付け、 前記熱伝導性平板と所定の間隔を有するように配置され
た回路基板に前記半導体素子の電極リードをはんだを介
して接続し、 前記熱伝導性平板の他方の面に放熱板を取り付けること
を特徴とする半導体素子の実装方法。
1. A semiconductor element is attached to one surface of a heat conductive flat plate, and an electrode lead of the semiconductor element is connected via solder to a circuit board arranged so as to have a predetermined distance from the heat conductive flat plate. Then, a heat dissipation plate is attached to the other surface of the heat conductive flat plate.
【請求項2】 半導体素子を熱伝導性平板の一方の面に
ネジを用いて取り付け、 前記熱伝導性平板と所定の間隔を有するように配置され
た回路基板に前記半導体素子の電極リードをはんだを介
して接続し、 前記熱伝導性平板の他方の面に、前記半導体素子を前記
熱伝導性平板に対して取り付けたネジを用いて放熱板を
取り付けることを特徴とする半導体素子の実装方法。
2. A semiconductor element is attached to one surface of a heat conductive flat plate with a screw, and electrode leads of the semiconductor element are soldered to a circuit board arranged so as to have a predetermined distance from the heat conductive flat plate. A mounting method of a semiconductor element, characterized in that a heat dissipation plate is attached to the other surface of the heat conductive flat plate by using a screw that attaches the semiconductor element to the heat conductive flat plate.
JP27197594A 1994-11-07 1994-11-07 Method for mounting semiconductor element Pending JPH08139240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27197594A JPH08139240A (en) 1994-11-07 1994-11-07 Method for mounting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27197594A JPH08139240A (en) 1994-11-07 1994-11-07 Method for mounting semiconductor element

Publications (1)

Publication Number Publication Date
JPH08139240A true JPH08139240A (en) 1996-05-31

Family

ID=17507414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27197594A Pending JPH08139240A (en) 1994-11-07 1994-11-07 Method for mounting semiconductor element

Country Status (1)

Country Link
JP (1) JPH08139240A (en)

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