JPH08137435A - Driving device for display device - Google Patents

Abstract

PURPOSE: To prevent overvoltages from being impressed on switching elements even in the case driving various kinds of display devices in the driving device of a matrix type display device. CONSTITUTION: In a driving device provided with a row side driver IC20 successively impressing scanning voltages on row lines LROW of an EL panel 2 in synchronization with a synchronizing signal HSYNC from the outside and a column side driver IC30 impressing voltages having polarities opposite to scanning voltages to column lines LCOL of the EL panel 2 in synchronization with the synchronizing signal HSYNC, a control circuit 21 provided in the IC20 and successively outputting driving signals to respective driver circuits DROW performing voltage impressions and groundings to respective row lines is constituted so as to shift the output timing of the driving signals by a time set with the DIP switch DSW of the outside of the IC20. Thus, timings of voltage impressions and groundings of the row lines and the column lines are shifted, overvoltage to a driver circuit are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for driving a matrix type display device in which scanning electrodes and data electrodes are provided on both surfaces of a display layer.

[0002]

2. Description of the Related Art Conventionally, as a driving device for a matrix type display device, a display voltage having a polarity different from that of a scanning voltage is applied to a data electrode forming a pixel to be displayed between the scanning electrode and a scanning electrode. There is known a drive device which displays the pixel and, at the end of the display control, grounds the electrodes to which the scanning voltage and the display voltage are applied to discharge the electric charge accumulated in the display pixel.

[0003]

However, in the matrix type display device, the time constants of the current paths on the scanning electrode side and the data electrode side are different. Therefore, in this type of driving device, a voltage is simultaneously applied to each electrode. When applied or when the electrodes to which voltage is applied are grounded simultaneously, the potential of the electrode with a large time constant (electrode with slow charge / discharge) has a small time constant due to the effect of charge storage of the display pixel. It changes following the potential change of (the electrode side where charge and discharge is fast),
There is a problem that an overvoltage larger than the voltage during display control is applied to the switching element in the drive circuit connected to the electrode side having a large time constant. Note that, hereinafter, a potential change on the electrode side having a large time constant, which follows the potential change on the electrode side having a small time constant, is referred to as a spike.

Therefore, it is possible to insert a resistor in advance in the current path from the switching element to each electrode to make the time constants of both electrodes match, but the number of electrodes (size)
When driving a display device with different electrical characteristics,
Since the time constant on each electrode side is different, the resistor must be replaced each time. Therefore, it has been difficult to drive various display devices with the conventional drive device.

The present invention has been made in view of these problems, and prevents overvoltage from being applied to the switching element even when driving various display devices having different time constants on the scanning electrode side and the data electrode side. It is an object of the present invention to provide a drive device for a display device that can do the above.

[0006]

In order to achieve the above object, the present invention according to claim 1 provides a display layer whose optical characteristics are changed by application of a driving voltage, and a display layer parallel to one surface of the display layer. A plurality of scanning electrodes disposed on the other surface of the display layer, and a plurality of data electrodes disposed on the other surface of the display layer in parallel to each other so as to be orthogonal to the scanning electrodes. A driving device of a display device, which is provided in a matrix type display device in which pixels are formed at intersections, and applies a predetermined voltage to each of the scan electrodes and the data electrodes to display an image, wherein the plurality of scan electrodes include: A plurality of scanning switching elements for applying a predetermined scanning voltage with respect to the ground potential, and a plurality of data electrodes with a predetermined polarity with respect to the ground potential and a polarity opposite to the scanning voltage, respectively. Display A plurality of display switching elements for applying a voltage, a plurality of grounding switching elements for grounding the scan electrodes and the data electrodes, and a plurality of scanning switching elements at predetermined scan timings sequentially for a predetermined time. When the scanning voltage is sequentially applied to the scanning electrodes by turning on the scanning switching elements, the switching elements for grounding connected to the scanning electrodes are turned on and the scanning voltage is applied from the pixel to which the scanning voltage is applied. A scanning control unit for discharging electric charges and a display switching element connected to a data electrode forming a pixel to be displayed based on display data for one scan electrode sequentially input from the outside in synchronization with the scanning timing. Is turned on for a predetermined time to control display / non-display of each pixel formed by the scan electrodes to which the scan voltage is applied. At the same time, the scanning switching element is turned off, and at the same time, the grounding switching element connected to the data electrode is turned on to discharge electric charge from the pixel to which the display voltage is applied, and the scanning control means. Means for relatively changing the timing at which the means turns on the scanning switching element and the timing at which the display control means turns on the display switching element, and the on-timing timing for changing the timing changing means Setting means for externally setting the deviation time.

According to a second aspect of the present invention, in the drive device according to the first aspect, the scanning control means and the display control means receive a synchronization signal from the outside, which indicates the scanning timing. After measuring a preset predetermined time, it is configured to turn on the scanning switching element and the display switching element, respectively, the timing changing means, among the scanning control means and the display control means It is characterized in that either one of them changes the above-mentioned predetermined time.

According to a third aspect of the present invention, in the driving device according to the first or second aspect, the driving device forms a plurality of scanning electrodes and a plurality of data electrodes on the EL light emitting layer. It is a drive device for an EL display device.

[0009]

In the driving device according to the first aspect of the present invention, the scanning control means turns on the scanning switching elements respectively connected to the scanning electrodes at predetermined scanning timings for a predetermined time, A scan voltage is sequentially applied to each scan electrode, each scan switching element is turned off, and at the same time, a ground switching element connected to the scan electrode is turned on to discharge electric charge from the pixel to which the scan voltage is applied. . Then, the display control means determines the display switching element connected to the data electrode forming the pixel to be displayed based on the display data for one scan electrode sequentially input from the outside in synchronization with the scan timing. Turns on for a period of time to control the display / non-display of each pixel formed by the scan electrode to which the scan voltage is applied, and turns off the scan switching element, and at the same time, switches the grounding connected to the data electrode. Turn on the element,
The charge is discharged from the pixel to which the display voltage is applied.

Further, the timing changing means sets the timing at which the scanning control means turns on the scanning switching element and the timing at which the display control means turns on the display switching element from the outside through the setting means. Only the time difference is changed relatively.

That is, in the present invention, the setting means is used to
It is possible to arbitrarily shift the timing at which the scanning switching element is turned on and the timing at which the display switching element is turned on, and accordingly, the scanning switching element is turned off to ground the scanning electrode side. The timing at which the switching element is turned on and the timing at which the display switching element is turned off and the grounding switching element on the data electrode side is turned on can also be shifted.

For example, in the case of a display device in which the time constant on the scanning electrode side is larger than that on the data electrode side, the on timing of the scanning switching element is relatively earlier than the on timing of the display switching element. When the voltage is applied (charged), the display voltage is applied to the data electrode after the voltage on the scan electrode side has almost reached the scan voltage, and the voltage on the scan electrode side has reached almost 0 V when the load is discharged. After that, the data electrode may be grounded. Then, a spike on the scan electrode side when a voltage is applied is generated with a reverse polarity with respect to the scan voltage, and a spike on the scan electrode side when a charge is discharged is generated with a reference of 0V.
It is possible to prevent overvoltage from being applied to the switching element on the scan electrode side.

On the other hand, in the case of a display device in which the time constant on the data electrode side is larger than that on the scan electrode side, the on timing of the display switching element is relatively earlier than the on timing of the scanning switching element. When the voltage is applied (charged), the scan voltage is applied to the scan electrode after the voltage on the data electrode side has almost reached the display voltage, and the voltage on the data electrode side is almost 0 when the load is discharged.
The scan electrode may be grounded after reaching V. Then, when the voltage is applied, the spikes on the data electrode side are generated with the opposite polarity with respect to the display voltage, and the spikes on the data electrode side during charge discharge are generated with 0V as the reference, and the switching element on the data electrode side is generated. It is possible to prevent overvoltage from being applied.

As described above, according to the driving device of the present invention, according to the magnitude characteristics of the time constant viewed from the respective electrode sides of the display device,
By arbitrarily shifting the ON timing of each switching element, it is possible to prevent an overvoltage from being applied to the switching element connected to each electrode, and it is possible to drive various display devices.

Next, in the driving device according to the second aspect, the scanning control means and the display control means have a predetermined time set when an external synchronization signal indicating the scanning timing is input. After the time is counted, the scanning switching element and the display switching element are turned on. Also,
The timing changing unit changes the predetermined time period measured by either the scanning control unit or the display control unit.

Therefore, a simple circuit is provided for the timing of turning on the scanning switching element and the grounding switching element on the scanning electrode side and the timing of turning on the display switching element and the grounding switching element on the data electrode side. It can be changed relative to the configuration.

In the invention described in claim 1 or 2, the pixel formed by the scan electrode and the data electrode in a liquid crystal display device, an EL display device, or the like has a capacitance, and a pixel between the electrodes is formed. A driving device that drives a display device in which electric charges remain in the display pixels after a voltage is applied can be applied. However, as described in claim 3, a plurality of scanning electrodes and a plurality of data electrodes are respectively provided in the EL light emitting layer. If it is applied to a drive device that drives the formed EL display device, a greater effect can be obtained.

That is, in the case of an EL display device, in order to cause the EL element formed of the scan electrode and the data electrode to emit light,
Since it is necessary to apply a high voltage of, for example, 200 V or more between the electrodes, a high breakdown voltage element is used as a switching element for controlling EL element light emission. In this case,
Since the overvoltage generated during charging and discharging also becomes a high voltage, the breakdown voltage of the switching element must be increased accordingly. However, if the present invention according to claim 1 or claim 2 is applied to such an EL display device, an overvoltage that occurs during charging and discharging can be satisfactorily suppressed. It is not necessary to set the breakdown voltage higher in consideration of the spike, and the drive device can be easily realized.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the entire display device of the embodiment. Reference numeral 2 denotes a matrix-type thin film EL panel (hereinafter, EL panel), which includes a plurality of row lines (scan electrodes) arranged in parallel with each other and a plurality of column lines arranged in parallel with each other so as to be orthogonal to the row lines. (Data electrodes) are formed on both sides of the EL light emitting layer, so that EL elements are provided in the horizontal and vertical directions. The display screen of the EL panel 2 is vertically divided into two by vertically dividing all the column lines.

The display device converts the image signal from the computer 4 into a digital signal (hereinafter referred to as display data) so that the EL panel 2 displays a desired image corresponding to the image signal output from the computer 4. A / D converter 6, a timing circuit 8 for generating various timing signals necessary for display control, and a video RAM for temporarily storing the display data input from the A / D converter 6 (hereinafter, referred to as
VRAM) 12 and display data input from the A / D converter 6 are sequentially fetched and stored in the VRAM 2, and
Based on the display data stored in the VRAM 12 and the display data input from the A / D converter 6, a control signal for display control is output to each of the row side driver IC 20 and the column side driver IC 30 provided in the EL panel 2. An EL controller 10 and a dip switch DSW as setting means for adjusting the operation timing of the low side driver IC 20 are provided.

The low side driver IC 20 is the EL panel 2
The scanning voltage is sequentially applied to each of the row lines. The column-side driver IC 30 applies a display voltage to each of the column lines of the EL panel 2 corresponding to the display data, and controls the number of EL elements formed between each row line to which the scanning voltage is applied and each column line. Controls light emission / non-light emission. Then, each of these driver ICs 20 and 30 can individually apply a voltage to a plurality of column lines.

In this embodiment, the EL panel 2 is vertically divided into two parts, and the driver ICs 20 and 30 for driving are provided for each of the two divided display screens. The upper and lower half screens of the EL panel 2 can be scanned twice each during the display time in which the image signal is output.

Next, the row-side driver ICs 20 are divided into groups for each half screen of the EL panel 2, and the row-side driver ICs 20 in the same group cooperate with each other and sequentially with respect to the row lines of the EL panel 2. Apply a scanning voltage.
Then, each row-side driver IC 20 responds to the control signal from the EL controller 10 for each field in which the application of the scanning voltage to the row lines of the half screen of the EL panel 2 is completed in all the driver ICs 20 in the same group. , The scan voltage is switched to a positive scan voltage (+ 125V) or a negative scan voltage (-125V).

Further, each row side driver IC 20 sequentially applies a scanning voltage to a plurality of row lines that it is responsible for, so that each row line LROW, as shown in FIG.
, LROW2, ..., and a plurality of driver circuits DROW1, DROW2, ..., which individually apply a scan voltage, and control for sequentially outputting drive pulses to these circuits according to a control signal output from the EL controller 10. Circuit 21
It consists of and. The control circuit 21 receives an n-bit (3 bits in this embodiment) signal set to either a high level or a low level by an externally provided dip switch DSW.

On the other hand, the column-side driver IC 30 is EL
The column-side driver ICs 30 are divided into groups for each half-screen column line of the panel 2, and the column-side driver ICs 30 in the same group each latch the display data for one row output from the EL controller 10, and the row-side driver IC 20 causes the display data to be displayed. When the scanning voltage is applied, the display voltage corresponding to the display data is applied to all the column lines at the same time. Further, each column-side driver IC 30 normally scans a negative voltage (-125V) if the scanning voltage is positive only when the voltage of each column line is grounded and the voltage is held at 0V to cause the EL element to emit light. If the voltage is negative, a display voltage having a polarity opposite to the scanning voltage, such as a positive voltage (+ 125V), is applied.

Then, each column side driver IC 30 is
Similar to the row side driver IC 20, in order to apply a display voltage to each of a plurality of column lines, as shown in FIG. 2, a plurality of display voltages are individually applied to each of the column lines LCOL1, LCOL2 ,. Driver circuits DCOL1, DCOL2, ... And further, a data latch circuit (not shown) for latching the display data for one row output from the EL controller 10, and the display data latched by the data latch circuit. EL controller 1
Control circuit 31 for generating a drive pulse for applying a positive or negative display voltage from each driver circuit DCOL1, DCOL2, ... To the column lines LCOL1, LCOL2 ,.
It has.

The sync signal HSYNC and the clock signal CLK are input as control signals from the EL controller 10 to the control circuits 21 and 31 in the driver ICs 20 and 30, respectively. Next, the row side driver circuit DROWn in each row side driver IC 20 and the column side driver circuit DCOLm in each column side driver IC 30 are respectively configured as shown in FIG.

That is, the low side driver circuit DROWn is
A positive voltage output circuit 24 that outputs a positive scanning voltage, a negative voltage output circuit 26 that outputs a negative scanning voltage, and a positive or negative scanning voltage output from each voltage output circuit 24, 26 to the low line LROWn. The column side driver circuit DCOLm includes a voltage applying circuit 28 for applying a positive voltage output circuit 34 that outputs a positive display voltage, a negative voltage output circuit 36 that outputs a negative display voltage, and each of these voltage outputs. The voltage application circuit 38 applies the positive or negative display voltage output from the circuits 34 and 36 to the column line LCOLm.

The positive voltage output circuits 24 and 34, the negative voltage output circuits 26 and 36, and the voltage application circuits 28 and 38 respectively apply a positive or negative voltage to the row line or the column line, or each of them. It is a circuit for switching between grounding the line and setting it in a floating state, and has exactly the same configuration.

In the following, taking the low side driver circuit DROWn as an example, each of the above circuits 24, 34, 26, 36, 28, 3 will be described.
The configuration of No. 8 will be described. The positive voltage output circuit 24 is a P-channel enhancement type high breakdown voltage MOS-FET (hereinafter referred to as P-channel transistor) for outputting a positive voltage to the voltage application circuit 28 via the positive voltage output line HVCC.
TR12 and positive voltage output line HVCC are grounded to 0V
Channel enhancement type, high breakdown voltage, MOS-FET (hereinafter N channel transistor) T
R13, a pair of resistors R11 and R12 for dividing the positive power supply voltage (+ 125V), and these resistors R11 and R1.
N-channel transistor TR11 connected in series to 2
It consists of and.

The source of the P-channel transistor TR12 and one end of the voltage dividing resistor R11 are connected to a positive voltage supply line from a power supply device (not shown), and the sources of the N-channel transistors TR11 and TR13 are the ground line GND.
Is connected to (0V) and is a P-channel transistor TR12.
The drains of the N-channel transistor TR13 and the N-channel transistor TR13 are connected to the positive voltage output line HVCC, and the gate of the P-channel transistor TR12 is connected to the voltage dividing resistor R1.
It is connected to the connection point of 1 and R12.

A positive voltage application signal HCL from the control circuit 21 is applied to the gate of the N-channel transistor TR11.
Kn is input, and the positive voltage discharge signal HSIG from the control circuit 21 is input to the gate of the N-channel transistor TR13.
n is input. In this positive voltage output circuit 24,
Positive voltage application signal HCLKn and positive voltage discharge signal HSIG
If both n are at the low level (0 V), the N-channel transistors TR11 and TR13 are turned off.
At this time, since no current flows through the resistors R11 and R12, the gate of the P-channel transistor TR12 has the same potential as the source, and the P-channel transistor TR12 is also turned off. Therefore, the positive voltage output line HVCC
Is in a floating state.

On the other hand, when the positive voltage application signal HCLKn becomes High level (+ 5V which is the same as the operating voltage in the driver IC in this embodiment), the N-channel transistor TR11 is turned on and current flows through the resistors R11 and R12. , The divided voltage generated at the connection point (intermediate voltage of 0 to 125V) is P
It is applied to the gate of the channel transistor TR12.
As a result, the P-channel transistor TR12 is turned on, +125 V is applied to the positive voltage output line HVCC, and this positive voltage is output to the voltage application circuit 28.

On the contrary, the positive voltage discharge signal HSIGNn is Hi.
When the gh level (+ 5V) is reached, the N-channel transistor TR13 is turned on, so that the positive voltage output line H
VCC is connected to the ground line GND. Next, the negative voltage output circuit 26 outputs the negative voltage to the voltage applying circuit 28 via the negative voltage output line LVBB and the N-channel transistor TR23, and the negative voltage output line LVBB.
A P-channel transistor TR22 for grounding
It is composed of a pair of resistors R21 and R22 for dividing the negative power supply voltage (-125V), and a P-channel transistor TR21 connected in series to these resistors R11 and R12.

Then, the N-channel transistor TR23
Source and one end of the voltage dividing resistor R22 are connected to a negative voltage supply line from a power supply device (not shown), and the source of the P-channel transistor TR22 is the ground line GND.
, The operating voltage of the driver IC is applied to the source of the P-channel transistor TR21, and the N-channel transistor TR23 and the P-channel transistor T
The drains of R22 are respectively connected to the negative voltage output line LVBB.
, The gate of the N-channel transistor TR23 is connected to the connection point of the voltage dividing resistors R21 and R22, and P
The negative voltage application signal LCLKn from the control circuit 21 is input to the gate of the channel transistor TR21. When the negative voltage discharge signal LSIGn output from the control circuit 21 is at High level, the negative voltage output circuit 26
A drive circuit 26a for generating a negative drive signal for turning on the P-channel transistor TR22 is provided.

In the negative voltage output circuit 26, the negative voltage application signal LCLKn is at high level and the negative voltage discharge signal L is
If SIGn is at low level, the P-channel transistors TR21 and TR22 are turned off. At this time, since no current flows through the resistors R21 and R22,
The gate of the N-channel transistor TR23 has the same potential as the source, and the N-channel transistor TR23 also turns off.
State. Therefore, the negative voltage output line LVBB is in a floating state.

On the other hand, when the negative voltage application signal LCLKn becomes low level (0V), the P-channel transistor TR2
When 1 is turned on, a current flows through the resistors R21 and R22, and the divided voltage (intermediate voltage of -125V to + 5V) generated at the connection point is applied to the gate of the N-channel transistor TR23. As a result, the N-channel transistor TR23
Is turned on, -125 V is applied to the negative voltage output line LVBB, and this negative voltage is output to the voltage application circuit 28.

On the contrary, when the negative voltage discharge signal LSIGn becomes High level, the drive circuit 26a outputs a negative drive voltage to the gate of the P-channel transistor TR22, so that the P-channel transistor TR22 is turned on, The negative voltage output line LVBB is grounded to the ground line GND.

Next, in the voltage application circuit 28, the source is connected to the positive voltage output line HVCC, the drain is connected to the low line LROWn, and the gate is the positive voltage output line H.
A P-channel transistor TR31 connected to a connection point of resistors R31 and R32 for voltage division provided between VCC and the ground line GND, a source connected to the negative voltage output line LVBB, and a drain connected to the low line LROW.
An N-channel transistor TR41 connected to n and having a gate connected to a connection point of resistors R41 and R42 for voltage division provided between the negative voltage output line LVBB and the ground line GND.

When a positive voltage is output from the positive voltage output circuit 24 to the positive voltage output line HVCC, the voltage applying circuit 28 turns on the P-channel transistor TR31 and applies a positive scanning voltage to the row line LROWn. Conversely, when a negative voltage is output from the negative voltage output circuit 26 to the negative voltage output line LVBB, the N-channel transistor TR41 is turned off.
Then, a negative scanning voltage is applied to the row line LROWn. Further, when the positive voltage output line HVCC is grounded by the positive voltage output circuit 24, the P-channel transistor TR
31 through the parasitic diode D31 of the low line LR
Until the OWn becomes approximately 0V, the positive charges accumulated in all the EL elements Sn formed by the row line LROWn are discharged, and conversely, the negative voltage output circuit 26 grounds the negative voltage output line LVBB. N-channel transistor TR
41 through the parasitic diode D41 of the low line LR
The negative charges accumulated in all the EL elements Sn formed by the row line LROWn are discharged until OWn becomes approximately 0V.

Therefore, in the low side driver circuit DROWn, the positive voltage application signal HCLKn and the positive voltage discharge signal HS output from the control circuit 21 to the circuit DROWn.
When both IGn and the negative voltage discharge signal LSIGn are at the low level and the negative voltage application signal LCLKn is at the high level, the row line LROWn is controlled to the floating state, and in this state, when the positive voltage application signal HCLKn changes to the high level. , When a positive scanning voltage is applied to the low line LROWn and the negative voltage application signal LCLKn changes to the low level, the negative scanning voltage is applied to the low line LROWn. When the positive voltage discharge signal HSIGn becomes High level after the application of the positive scanning voltage, the low line LROW
n is grounded, the positive charges accumulated in the EL element are discharged until the row line LROWn becomes 0 V, and conversely, after the negative scanning voltage is applied, when the negative voltage discharge signal LSIGn becomes High level, LROWn is grounded, and the negative charge accumulated in the EL element is discharged until the row line LROWn becomes 0V.

As described above, since the column side driver circuit DCOLm has the same structure as the row side driver circuit DROWn, the positive voltage application signal HCLK output from the control circuit 31 in the column side driver IC 30.
m, positive voltage discharge signal HSIGm, negative voltage application signal LCL
Upon receiving Km and the negative voltage discharge signal LSIGm, the low-side driver circuit DROWn operates in the same manner.

Next, the control circuit 21 provided in the low-side driver IC 20 counts the rising edges of the clock signal CLK from the EL controller 10 as shown in FIG.
The counter 40 that is reset when SYNC is at the low level and the digital value of the 3-bit signal that is set to either the high level or the low level by the dip switch DSW are preset, and the preset value and the count value of the counter 40 And the comparator 42 that outputs a high-level signal and the high-level signal from the comparator 42 are latched, and the synchronization signal H
The latch circuit 44 that is reset when SYNC is at the low level, and the output signal ASIG from the latch circuit 44 are Lo
Every time the w level is changed to the High level, the signal HCLKn,
The control signal generator 22 sequentially outputs HSIGn, LCLKn, and LSIGn in a predetermined pattern described later.

The control signal generator 22 includes a positive voltage application signal generator 22a, which outputs a positive voltage application signal HCLKn.
A positive voltage discharge signal generation unit 22b that outputs a positive voltage discharge signal HSIGn, a negative voltage application signal generation unit 22c that outputs a negative voltage application signal LCLKn, and a negative voltage discharge signal LSIG.
It is composed of a negative voltage discharge signal generation unit 22d that outputs n, and each generation unit 22a to 22d outputs each driver circuit D.
To ROWn, each of the above signals HCLKn, HSIG
n, LCLKn, LSIGn are output.

Here, the dip switch DSW is a plurality (three in this embodiment) of switches SW1 to SW3 arranged in parallel, and the low side driver IC 20 of each switch.
The contact on the side opposite to is connected to the ground line (0V). The external terminals of the low-side driver IC 20 connected to each switch are pulled up to 5V by pull-up resistors Ra to Rc in the IC 20, and the pulled-up signal lines D1 to D3 are used as comparators. 42 has been input. Then, when the count value of the counter 40 reaches the digital value represented by the voltage level of the signal lines D3, D2, D1, the comparator 42 outputs a high level signal to the latch circuit 44.
Output to.

For example, each switch of the dip switch DSW is "ON, OFF, O" in order from SW3 to SW1.
When set to "N", the signal lines D3, D
Since the voltage levels of 2, D1 are "Low, High, Low", the comparator 42 outputs a High level signal when the count value of the counter 40 becomes "2". Then, in this case, as illustrated in FIG. 5, the synchronization signal HSYNC from the EL controller 10 changes from the low level to
When it becomes High level, the counter 40 makes the clock signal CL
The rising edge of K is counted, and the count value is "2".
Then, a high-level signal is output from the comparator 42, the signal is latched by the latch circuit 44, and from that point until the next synchronization signal HSYNC becomes a low level, the latch circuit 44 outputs a high-level output signal ASIG. Is output. Therefore, the synchronization signal HSYNC
Every time the clock signal CLK rises twice after changing from the low level to the high level, the rising edge of the signal ASIG is input from the latch circuit 44 to the control signal generating section 22.

Then, the control signal generator 22 outputs each signal HCLKn, HSIGn, LCLKn, LSIGn for applying the scanning voltage to each row side driver circuit DROWn every time the output signal ASIG of the latch circuit 44 rises.
Are sequentially output, and the scanning voltage is sequentially applied to the plurality of row lines that the self is responsible for.

On the other hand, although not shown, the control circuit 31 provided in the column side driver IC 30 is also provided with a counter, a comparator, a latch circuit, and a control signal generating section, like the control circuit 21 shown in FIG. However, the following 2
The points are different. (1) The comparator has a fixed value N (for example, "4").
Is preset, and the clock signal CLK is changed after the synchronization signal HSYNC changes from Low level to High level.
Every time the signal rises N times, the rising edge of the signal ASIG is input from the latch circuit to the control signal generator. (2) The control signal generator identifies the column line LCOLm to which the EL element to emit light is connected based on the display data for one row from the EL controller 10 latched by the data latch circuit, and the control signal generator outputs from the latch circuit. Signal AS
When IG rises, the signals HCLKm, HSIGm, LCLKm, and LSIGm for applying the display voltage are output to the driver circuit DCOLm corresponding to the column line.

That is, in the control circuit 31 of the column side driver IC 30, the synchronization signal HSYNC changes from low level to high level.
When the clock signal CLK changes to the level and rises N times, it operates so as to apply the display voltage to the EL element to emit light at that time. Next, the control circuit 2 in each of the driver ICs 20 and 30 when the EL panel 2 is actually driven
The basic operation of Nos. 1 and 31 will be described based on the time charts shown in FIGS. In addition, the following FIG. 6 and FIG.
In the following description, it is assumed that the comparator 42 in the row side control circuit 21 is preset with the same value (the fixed value N) as the comparator in the column side control circuit 31 by the DIP switch DSW. .

FIG. 6 shows a control operation when the EL panel 2 is driven by a positive voltage, in which a positive scanning voltage is applied to the row line and a negative display voltage is applied to the column line to cause the EL element to emit light. There is. As shown in FIG. 6, the control circuit 2
The control signal generator 22 of No. 1 outputs the positive voltage application signal HCLK, the positive voltage discharge signal HSIG, and the negative voltage discharge signal LSIG among the control signals output to all the driver circuits DROW.
Initialize the low voltage application signal LCLK to the low level and the high level, respectively, to bring all the row lines LROW into the floating state (F). Then, the synchronization signal HS
When YNC changes from the low level to the high level, the clock signal CLK rises N times and the output signal ASIG of the latch circuit 44 changes from the low level to the high level, the control signal generation unit 22 outputs the low signal in the first row. Line LR
The positive voltage application signal HCLK1 for OW1 is kept for a predetermined time T
Switch to High level only, and P in the positive voltage output circuit 24
A positive scanning voltage is applied to the row line LROW1 via the channel transistor TR12 (scanning switching element).

On the other hand, the control signal generator of the control circuit 31 is
Normally, of the control signals output to all the driver circuits DCOL, the positive voltage application signal HCLK is set to Low level, and the positive voltage discharge signal HSIG, the negative voltage application signal LCLK, and the negative voltage discharge signal LSIG are set to High level, respectively. , Ground all column lines LCOL. Then, the synchronization signal HS
When YNC changes from the low level to the high level, the clock signal CLK rises N times and the output signal ASIG of the latch circuit changes from the low level to the high level, the column line LCOLm forming the EL element to emit light. The negative voltage application signal LCLKm and the negative voltage discharge signal LSIGm for
The level is switched, and a negative display voltage is applied to the column line LCOLm via the N-channel transistor TR23 (display switching element) in the negative voltage output circuit 36.

As a result, a voltage (250 V) required for light emission is simultaneously applied to both ends of the EL element S1m to be issued in the first row, and the EL element is charged by this voltage to emit light, and the other EL elements. The scanning voltage is 125
Only V is applied and no light is emitted.

In this way, when the display control of the first row is executed and a predetermined time T elapses after the output signal ASIG of the latch circuit 44 changes to the High level, the control signal generator 22 of the control circuit 21 applies the positive voltage. The signal HCLK1 is switched to low level, and the positive voltage discharge signal HSIG1 is switched to high level. At the same time, the control signal generator of the control circuit 31 controls the negative voltage application signal LCLKm and the negative voltage discharge signal L to be negative.
Switch SIGm to High level.

As a result, the positive voltage output circuit 24 starts from the first row row line LROW1 to which the positive scanning voltage is applied.
The negative charge is discharged from the column line LCOLm to which the negative display voltage is applied by discharging the positive charges accumulated in all the EL elements in the first row through the N-channel transistor TR13 (switching element for grounding) in The negative charge accumulated in the EL element S1m is discharged through the P-channel transistor TR22 (grounding switching element) in the output circuit 36.

Next, in the control circuit 21, when the output signal ASIG of the latch circuit 44 changes from the low level to the high level, the control signal generating section 22 switches the positive voltage discharge signal HSIG1 to the low level, and the one line The row line LROW1 of the eye is returned to the floating state (F), and the application of the positive scanning voltage (display control) and the grounding (discharge) are repeated for the row lines LROW2 of the second and subsequent rows as well. Further, the control signal generator of the control circuit 31 also repeats the application (display control) of the negative display voltage and the grounding (discharge) to the column line forming the EL element to emit light, similarly to the above.

On the other hand, when the EL panel 2 is driven at a negative voltage, the control circuits 21 and 31 in the driver ICs 20 and 30 are operated as shown in FIG.
It operates as shown in. That is, the difference between the case of driving the negative voltage and the case of driving the positive voltage is as follows. At the time of driving the negative voltage, the negative scanning voltage is applied to the row line and the positive display voltage is applied to the column line to drive the EL element. Make it glow.

Control signal generator 22 of control circuit 21
Switches the negative voltage application signal LCLKn to a low level during display control, and applies a negative scanning voltage to the low line LROWn via the N-channel transistor TR23 (scanning switching element) in the negative voltage output circuit 26. At the time of discharging, the negative voltage discharge signal LSIGn is switched to the high level, and the negative charges are discharged from all the EL elements of the row line LROWn via the P-channel transistor TR22 (grounding switching element) in the negative voltage output circuit 26. The control signal generator of the control circuit 31 is
The positive voltage application signal HCLKm is switched to the high level and the positive voltage discharge signal HSIGm is switched to the low level, and the column line LCOL is switched via the P-channel transistor TR12 (display switching element) in the positive voltage output circuit 34.
When a positive display voltage is applied to m, the positive voltage application signal HCLKm is set to low level during positive discharge, and the positive voltage discharge signal HSIG is set to
m is switched to High level respectively, and the positive charge accumulated in the EL element Snm is discharged through the N-channel transistor TR13 (grounding switching element) in the negative voltage output circuit 34.

As described above, in the present embodiment, the scanning voltage is applied in order from the first row row line, and during the application of the scanning voltage, the scanning voltage is applied to the column line forming the EL element to emit light. By applying a display voltage having a polarity opposite to that of, the light emission / non-light emission of the EL elements is controlled for each row of the EL panel 2, and each time the display control for one row is completed,
Ground each line to which the scanning voltage and display voltage are applied,
The charge accumulated in the EL element is discharged by applying the scanning voltage and the display voltage.

By the way, as in the above example, the control circuit 21
The preset value of the comparator 42 in the control circuit 31
If the same value N as the preset value of the internal comparator is set, the control signal for the low side driver circuit DROWn is switched (HCLKn = Hig during positive voltage driving).
h, LCLKn = Low during negative voltage driving, switching the timing of applying the scanning voltage to the row line LROWn, and the control signal for the column side driver circuit DCOLm (LCLKm = Low during positive voltage driving, LSIGm =
Low, HCLKm = High, HSIGm when driving negative voltage
= Low), the timing of applying the display voltage to the column line LCOLm matches. Furthermore, in this case, the control signal for the low-side driver circuit DROWn is switched (HCLKn = Low, HSIGn = Hi during positive voltage driving).
gh, LCLKn = High when driving a negative voltage, LSIGn =
High), switching the timing of grounding the low line LROWn and the control signal for the column side driver circuit DCOLm (LCLKm = High, L during positive voltage driving)
SIGm = High, HCLKm = Low during negative voltage drive,
HSIGm = High), and the timing of grounding the column line LCOLm matches.

Then, when the scanning voltage and the display voltage are simultaneously applied to each line in this way to charge the EL element,
Also, when the lines are grounded at the same time to discharge the charges accumulated in the EL element, there is no problem if the time constants of the charge / discharge path on the row line side and the charge / discharge path on the column line side match. However, in the EL panel 2, since the time constants on the respective line sides are usually different, an overvoltage is applied to the transistor connected to the line with the larger time constant during charging and discharging.

A case in which the time constant on the row line side is larger than the time constant on the column line side will be described by taking positive voltage driving as an example. In FIG. 3, the low side driver circuit D
When the positive voltage application signal HCLKn to ROWn changes from the low level to the high level, the low side driver circuit DRO
From the Wn positive voltage supply line (+125 V) to the EL element S
The charging of positive charges to the nm is started via the P-channel transistors TR12 and TR31. At the same time, when the negative voltage application signal LCLKm to the column side driver circuit DCOLm changes from the high level to the low level, the negative voltage supply line (-125V) of the column side driver circuit DCOLm to the EL element Snm to the N-channel transistor. Charging of negative charges is started via TR23 and TR41. However, in this case, since the charging speed on the column line side is faster, as shown in part a of FIG. 8 showing the voltage change of the row line and the column line, the low line is caused by the action of charge storage of the EL element Snm. LROWn
Is temporarily pulled to the negative voltage side, causing spikes in the low line. As a result, the P-channel transistor TR in the low side driver circuit DROWn
12, an overvoltage larger than the scanning voltage is applied between the source and drain of TR31.

In FIG. 3, the low side driver circuit D
When the positive voltage discharge signal HSIGNn to ROWn changes from the low level to the high level, P from the EL element Snm to the ground line GND of the low side driver circuit DROWn
Parasitic diode D31 of channel transistor TR31
And the discharge of positive charges is started via the N-channel transistor TR11. At the same time, the negative voltage discharge signal LSIGm to the column side driver circuit DCOLm changes to Lo.
When the w level changes to the High level, the EL element Snm
From the negative side to the ground line GND of the column side driver circuit DCOLm via the parasitic diode D41 of the N-channel transistor TR41 and the P-channel transistor TR22. However, in this case as well, since the discharge rate on the column line side is faster, the voltage of the row line LROWn is temporarily pushed up to the positive voltage side by the action of charge storage of the EL element Snm as shown in part b of FIG. It will be spoiled and a spike will occur on the low line. As a result, an overvoltage larger than the scanning voltage is applied between the drain and the source of the N-channel transistor TR11 in the low side driver circuit DROWn.

Therefore, when the scanning voltage and the display voltage are simultaneously applied to the row line and the column line respectively, and when the lines are simultaneously grounded after the voltage is applied, there is a concern that each transistor is deteriorated by the overvoltage.
However, in the display device of the present embodiment, the synchronizing signal HSY is output from the row side driver circuit DROW to the row line LROW.
Since the timing of applying the scanning voltage in synchronization with NC can be arbitrarily adjusted by the dip switch DSW, it is possible to prevent the occurrence of overvoltage as described above.

That is, when the time constant on the row line side is larger than the time constant on the column line side as in the above-mentioned example, the comparator 42 in the row side driver IC 20 (control circuit 21) is operated by the dip switch DSW. The column-side driver IC 30 (control circuit 3
It may be set to a value smaller than the preset value N of the comparator in 1).

Then, as shown in FIGS. 9 and 10, which show the positive voltage driving operation and the negative voltage driving operation, respectively, as shown in FIGS.
Low-side driver IC 20 after SYNC has started
The time T1 until the output signal ASIG of the latch circuit 44 rises and the time T2 until the output signal ASIG of the latch circuit of the column side driver IC 30 rises are
The time T1 becomes shorter. As a result, the switching timing of each control signal to the row side driver circuit DROWn is relatively earlier than the switching timing of each control signal to the column side driver circuit DCOLm by the difference between the time T1 and the time T2.

Therefore, during positive voltage driving, as shown in FIG. 9, after the positive voltage application signal HCLKn to the low side driver circuit DROWn changes to the High level, the EL element Snm is charged and the low line LROWn of the low line LROWn is charged. After the voltage rises to almost the scanning voltage, the negative voltage application signal LCLKm and the negative voltage discharge signal LSIGm to the column side driver circuit DCOLm are changed to the Low level, and the positive voltage application signal to the row side driver circuit DROWn is changed. HCLK
After n changes to the Low level and the positive voltage discharge signal HSIGn changes to the High level, the EL element Snm is discharged and the voltage of the row line LROWn drops to almost 0 V, and then the negative voltage to the column side driver circuit DCOLm is reached. The voltage application signal LCLKm and the negative voltage discharge signal LSIGm can be changed to the high level.

On the other hand, even at the time of driving the negative voltage, as shown in FIG. 10, after the negative voltage application signal LCLKn to the low side driver circuit DROWn changes to the low level, the EL element Snm is charged and the low line LROWn of the low line LROWn is charged. After the voltage drops to almost the scanning voltage, the positive voltage application signal HCLKm to the column side driver circuit DCOLm is changed to High level, the positive voltage discharge signal HSIGm is changed to Low level, and the low side driver circuit DROWn is changed. The negative voltage application signal LCLKn and the negative voltage discharge signal LSIGn of
After changing to the gh level, the EL element Snm is discharged and the voltage of the row line LROWn rises to almost 0V, and then the positive voltage application signal HCLKm to the column side driver circuit DCOLm is set to the low level and the positive voltage discharge signal is set. HSIG
You can change m to High level respectively.

As a result, as shown in FIGS. 9 and 10,
When a voltage is applied, a spike on the low line LROWn side can be generated with a polarity opposite to that of the scan voltage, and a spike on the low line LROWn side can be generated with a reference of approximately 0 V when the EL element Snm is discharged.
It is possible to prevent application of an overvoltage equal to or higher than the scanning voltage to each transistor of the row side driver circuit DROWn.

When driving an EL panel in which the time constant on the column line side is larger than the time constant on the row line side, the preset value of the comparator 42 in the row side driver IC 20 is changed by the dip switch DSW. It may be set to a value larger than the preset value N of the comparator in the column driver IC 30.

As described above, according to the display device of the present embodiment, the row side driver I is driven by the dip switch DSW commonly connected to all the row side driver ICs 20.
A driver circuit DROW provided in the C20 and a driver circuit DCO provided in the column side driver IC 30
Since the drive timing with respect to the synchronization signal HSYNC with L can be arbitrarily adjusted, it is possible to prevent an overvoltage from being generated when applying a voltage to the EL element and discharging an electric charge from the EL element. it can. Therefore, it is not necessary to use transistors having a higher withstand voltage than necessary as the transistors forming each of the driver circuits DROW and DCOL, and the cost can be reduced.

Moreover, the low-side driver IC 2 of this embodiment
0 and the column-side driver IC 30 drive E
Since the drive timing of each driver circuit DROW, DCOL can be optimally shifted according to the size characteristic of the time constant viewed from each line side of the L panel, EL panels of various sizes having different numbers of row lines and column lines are provided. Can be used for.

Further, for example, when the magnitude relation of the time constants on the row line side and the column line side changes depending on the number of column lines to which the display voltage is applied, the row side driver circuit DROW and the column side driver circuit. DCOL
In the charge / discharge path between the EL element in either one of
A resistor having a predetermined value may be inserted in advance and the time constant on one line side may be intentionally increased, and then the drive timing of each driver circuit DROW, DCOL may be shifted by the dip switch DSW.

In the above embodiment, the low side driver IC
Although the dip switch DSW is provided on the switch 20 to change the drive timing of the row side driver circuit DROW, the column side driver IC 30 is provided with the dip switch DSW to change the drive timing of the column side driver circuit DC.
The drive timing of the OL may be changeable. Further, by providing a dip switch on both driver ICs 20 and 30 so that the drive timings of both driver circuits DROW and DCOL can be changed respectively, a wider range of adjustments can be made.

In the above embodiment, the voltage is applied to the row line and the column line for the same time T. However, the column side driver IC 30 is used by the EL controller 10.
Even when performing the light emission time control such as changing the voltage application time to the column line in response to the command from the, the timing of applying the voltage to each line or the timing of grounding each line is relatively set by the dip switch DSW. Moreover, since it can be arbitrarily shifted, overvoltage to the switching element can be prevented.

Further, in the above-mentioned embodiment, the EL panel having the EL light emitting layer which emits light by the application of the driving voltage is driven. However, in the present invention, the light transmission characteristic is changed by the application of the driving voltage. The present invention can also be applied to a liquid crystal display device including a liquid crystal layer.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display device according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of row-side and column-side driver ICs according to an embodiment.

FIG. 3 is an electric circuit diagram showing a configuration of row-side and column-side driver circuits according to an embodiment.

FIG. 4 is a block diagram showing a configuration of a control circuit provided in the row side driver IC of the embodiment.

FIG. 5 is a time chart explaining operations of a counter, a comparator, and a latch circuit which form a control circuit of the embodiment.

FIG. 6 is a time chart showing a basic operation when driving a positive voltage according to the embodiment.

FIG. 7 is a time chart showing a basic operation when driving a negative voltage according to the embodiment.

FIG. 8 is an explanatory diagram illustrating a spike that occurs in a row line according to the embodiment.

FIG. 9 is a time chart for explaining the operation of the row-side and column-side driver ICs when the EL panel is driven by a positive voltage.

FIG. 10 is a time chart explaining the operation of the row-side and column-side driver ICs when the EL panel is driven by a negative voltage.

[Explanation of symbols]

2 ... EL panel 10 ... EL controller 20 ...
Row-side driver IC 30 ... Column-side driver ICs 21, 31 ... Control circuit DROWn ... Row-side driver circuit DCOLm ... Column-side driver circuit 22 ... Control signal generator 24, 34 ... Positive voltage output circuit 26, 36 ... Negative voltage output circuit 28, 38 ... Voltage application circuit 40 ... Counter 42 ... Comparator 44 ... Latch circuit DSW ... DIP switch

Claims (3)

[Claims] 1. A display layer whose optical characteristics are changed by application of a driving voltage, a plurality of scanning electrodes arranged in parallel with each other on one surface of the display layer, and a scanning electrode on the other surface of the display layer. A plurality of data electrodes are arranged in parallel to each other so as to be orthogonal to each other, and provided in a matrix type display device in which pixels are formed at respective intersections of the data electrodes and the scanning electrodes,
A drive device of a display device for displaying an image by applying a predetermined voltage to each of the scan electrode and the data electrode, wherein a predetermined scan voltage based on a ground potential is applied to each of the plurality of scan electrodes. A plurality of scanning switching elements for, to the plurality of data electrodes, respectively, a plurality of display switching elements for applying a predetermined display voltage having a polarity opposite to the scanning voltage with reference to the ground potential, A plurality of grounding switching elements for grounding the scan electrodes and the data electrodes, respectively, and a plurality of scanning switching elements are sequentially turned on for a predetermined time at predetermined scan timings to sequentially apply a scan voltage to each scan electrode. At the same time, the scanning switching elements are turned off, and at the same time, the grounding switching element connected to the scanning electrode is turned on to change the scanning voltage. It is connected to a scanning control means for discharging an electric charge from the applied pixel and a data electrode forming a pixel to be displayed on the basis of display data for one scanning electrode which is sequentially input from the outside in synchronization with the scanning timing. The display switching element is turned on for a predetermined time to control display / non-display of each pixel formed by the scan electrodes to which the scan voltage is applied, and at the same time, the scan switching element is turned off. Display control means for turning on a grounding switching element connected to an electrode to discharge electric charge from a pixel to which a display voltage is applied; timing for the scanning control means to turn on the scanning switching element; Timing changing means for relatively changing the timing at which the control means turns on the display switching element; Driving device for a display device characterized by comprising setting means for setting the delay times of the ON timing externally grayed changing means alters the. 2. The scanning control means and the display control means measure a predetermined time set in advance when an external synchronizing signal indicating the scanning timing is input, and then, the scanning switching element and the scanning switching element. It is configured to turn on each of the display switching elements, and the timing changing unit changes the predetermined time period measured by either one of the scanning control unit and the display control unit. Item 2. A drive device for a display device according to item 1. 3. The driving device for an EL display device, wherein the driving device is formed by forming a plurality of scanning electrodes and a plurality of data electrodes on an EL light emitting layer, respectively. Display device driving device.