JP2781975B2 - Drive circuit for EL display device - Google Patents

Abstract

PURPOSE:To prevent an afterimage from being formed on the EL display device by applying a specific binary signal to a capacitor and turning on and off a switching element, and applying a dummy pulse to the capacitor right before the binary signal is applied. CONSTITUTION:The EL display device 20 is interposed between row-side and column-side electrodes arrayed in a matrix direction and driven by setting the potentials of the respective row-side electrode and respective column-side electrodes. A composite row driving circuit is supplied with control signals A, B, and C based upon a vertical synchronous rise detection, an odd-row and even-row detection, and a clocking and vertical synchronous polarity detection signal and the capacitor 523 of an output circuit 522 is charged electrostatically with the dummy pulse contained in the signal A right before the device 201 is scanned. Consequently, the FET 525 of the output circuit 522 is securely turned on as the signal A rises and the rounding of the output waveform of a composite driving output PROW is eliminated to prevent the afterimage from appearing on the device 201.

Description

The present invention relates to a driving circuit for an EL display device.

[Conventional technology]

FIG. 3 shows the configuration of the EL display device. In the figure, a strip-shaped transparent electrode 1 made of In ₂ O ₃ is formed on a glass substrate 101.
02 are provided in parallel, and for example, Y ₂ O ₃ , Si ₂ N ₄ , Ta ₂
A dielectric material layer 103 such as O ₅ and Al ₂ O ₃ , an EL layer 104 made of ZnS doped with an activator such as Mn, and Y ₂ O ₃ and Si
_{2 N 4, Ta 2 O 5} , Al 2 O vapor deposition dielectric material layer 103 ', such as _3,
Three-layer thin film EL laminated by sputtering method
An element is provided, and a strip-shaped back electrode 105 made of Al is provided on the element in parallel with a direction perpendicular to the transparent electrode 102.

Since the above-mentioned thin-film EL element has the EL layer 104 interposed between the two electrodes between the dielectric materials 103 and 103 ', it can be regarded as a capacitive element equivalently. In addition, as is apparent from the voltage-luminance characteristics shown in FIG.
It is driven by applying a relatively high voltage of about 0V.

In this way, the thin-film EL element requires a relatively high driving voltage of about 200 V, and is driven using a high-breakdown-voltage MOS field-effect transistor. For this reason, a high voltage MOS integrated circuit in which a high voltage MOS field effect transistor and a logic circuit for switching this transistor are integrated on the same chip is provided as a drive circuit dedicated to the thin film EL element.

FIG. 5 illustrates a circuit configuration for driving the EL display device. Here, the EL display device 201 is used as a terminal of the personal computer 301.

First, the EL display device 201 and the column electrode X ₁ to X ₆₄₀ column side is arranged in the X direction, and the row electrodes Y ₁ to Y ₂₀₀ in arranged in the Y-direction line side. Therefore, the EL display device 201 has a pixel matrix of 640 × 200 dots. The row-side ICs 210 and 220 include, as output stages, field-effect transistors (hereinafter referred to as FETs) 211 and 221 connected to odd-numbered and even-numbered row electrodes, respectively, and selectively turn on and off these FETs. To On the other hand, the column-side IC 230 includes FETs 231 and 232 as output stages for each odd-numbered column electrode, and selectively turns these FETs on and off. The column-side IC 240 includes FETs 241 and 242 as output stages for each even-numbered column electrode, and selectively turns these FETs on and off.

Now, a television signal indicating an image is output from the personal computer 301, and the television signal is applied to the image conversion unit 302. The television signal includes a horizontal synchronization signal, a vertical synchronization signal, a data signal, and a clock signal. When the television signal is input, the image conversion unit 302 removes a blanking period included in the television signal, converts the television signal to be compatible with the EL cover device 201, and converts the horizontal signal converted for EL. Sync signal
HS, the vertical synchronizing signal VS, the data signal DIN and the clock signal CKD are sent to the control circuit 303. The control circuit 303 processes these signals, and the EL display device 303 processes these signals on the column side and the row side of the EL display device 201, respectively.

First, when performing the processing on the column side of the EL display device 201, the control circuit 303 outputs the data signal DIN (PIN) for each pixel in one row and 640 columns while the horizontal synchronization signal HS (shown in FIG. 6) is at a high level. 6) and a clock signal CKD (shown in FIG. 6) are input, and the data signal DIN for each pixel of 640 columns is distributed to odd and even numbers. That is, the clock signal CKD is divided by 2 to form a divide-by-2 clock signal CLK, and the inverted divide-by-2 clock signal ▲
KK is formed, and the odd-numbered odd data signal Dodd is obtained by latching the data signal DIN at the rise of the divided-by-2 clock signal CLK, and the data signal DIN is set as the even data signal Deven. And the control circuit 303
Sends the inverted-divided-two clock signal ▲ K and the odd-numbered data signal Dodd to the column-side IC 230,
Divided clock signal ▲ ▼ K and even data signal Dev
n is sent to the column side IC 240.

Inverted divided-by-2 clock signal ▲ ▼ K in column side IC230
And the odd data signal Dodd is input to the shift register 233. The shift register 233 outputs the inverted divided-by-2 clock signal.
At the rising edge of K, odd-numbered data signals Dodd are sequentially stored. Further, the column side IC 240 inputs the inverted divided-by-2 clock signal ▼ K and the even-numbered data signal Deven to the shift register 243. The shift register 243 outputs the even-numbered data signal Deven at the rise of the inverted divided-by-2 clock signal ▲ ▼ K.
Are sequentially stored, so that only the data signals except the odd-numbered data signals of the even-numbered data signals Deven, that is, only the even-numbered data signals of the data signal DIN are stored. As a result, the shift register 233 of the column-side IC 230 stores odd-numbered data indicating the brightness of the odd-numbered pixel among the pixels of one row and 640 columns, and the shift register 243 of the column-side IC 240 stores the pixel of one row and 640 columns. Among them, the even data indicating the brightness of the even-numbered pixel is stored.

Next, the control circuit 303 sets the column latch signal LACOL (shown in FIG. 6) to a high level after the transmission of the data signal DIN of one row and 640 rows is completed, that is, after the horizontal synchronizing signal HS falls. The column latch signal LACOL is input to the latch circuits 234 and 244 of the column-side ICs 230 and 240, respectively.

The latch circuit 234 of the column-side IC 230 outputs the column latch signal L
When ACOL rises, odd data is latched from the shift register 233, and a high-level or low-level signal is applied to each AND circuit 235 corresponding to the odd-numbered column electrode based on the odd-numbered data. For example, a latch circuit
234 applies a high-level signal to the AND circuit 235 corresponding to the column electrode in the first column if the pixel in the first row and first column is “bright”, and if the pixel in the first row and third column is “dark”. For example, a low-level signal is applied to an AND circuit 235 corresponding to the third column electrode X3.

On the other hand, when the column latch signal LACOL rises, the latch circuit 244 of the column side IC 240 latches even data from the shift register 243, and based on the even data, the AND circuit 245 corresponding to the even-numbered column electrode is driven high. Apply a level or low level signal, respectively. For example, the latch circuit 244 applies a high-level signal to the AND circuit 245 corresponding to the column electrode X2 in the second column if the pixel in the first row and second column is “bright”, and the pixel in the first row and fourth column is If "dark", a low-level signal is applied to the AND circuit 245 corresponding to the fourth column electrode X4.

Next, the control circuit 303 supplies an odd row enable signal ENodd and an even row enable signal ENeven described later.
And outputs a column output enable signal COLOE (shown in FIG. 6) synchronized with the horizontal synchronizing signal HS to the column-side ICs 230 and 240 during scanning. This column output enable signal COLOE is applied to each column side IC230,
Added to 240 AND circuits 235,245 respectively.

When the column output enable signal COLOE rises to a high level, the AND circuit 235 of the column side IC 230
A high-level or low-level signal based on the odd-numbered data from the shift register 233 is supplied to the FET 231 and the knot circuit 236.
To the FET 232 via. For example, the AND circuits 235 corresponding to the column electrodes X ₁ of the first column is added to the first row and the first column of pixels corresponds to the first column a high level signal if the "bright" column electrodes X ₁ FET231 . As a result, the FET 231 is turned on, and a voltage of +80 V from the column voltage supply unit 601 is applied to the _first column electrode X1. The AND circuit 235 corresponding to the _third column electrode X ₃ outputs a low level signal to the knot circuit 236 corresponding to the _third column electrode X ₃ if the pixel in the first row and third column is “dark”. Add to In response, a high-level signal is output from the knot circuit 236 to the FET.
Was added to 232, the FET is turned on, the third column the column electrode X ₃ is grounded.

On the other hand, when the column output enable signal COLOE rises to a high level, the AND circuit 245 of the column side IC 240 outputs a high level or low level signal based on the even data from the shift register 243 to the FET 241 and the knot circuit 246. Via FET242. For example, an AND circuit 245 which corresponds to the second row in the column electrode X ₂ is (1, 2) th pixel outputs a high level signal if the "bright", thereby the second column to the column electrode X ₂ The corresponding FET 241 is turned on, and a voltage of +80 V from the column voltage supply unit 601 is applied to the _second column electrode X2. Further, the AND circuit 245 which corresponds to the column electrode X ₄ of the fourth column first row 4 column of pixels outputs a low level signal if the "dark", thereby the fourth column to the column electrode X ₄ corresponding FET242 is turned on, the fourth column the column electrode X ₄ is grounded.

Therefore, each of the column electrodes X _{1 to} X ₆₄₀ is applied with +80 V when the pixel is “bright” and grounded when the pixel is “dark”, corresponding to the pixels in one row and 640 columns. Each of the column electrodes X _{1 to} X corresponding to such a pixel in one row and 640 columns
_{The 640} potential is set by the column output enable signal CO.
It is held until the LOE falls, that is, while the horizontal synchronization signal HS is almost at a high level. And during this period, 2 rows 64
Data signals DIN corresponding to pixels in column 0 are distributed to odd-numbered and even-numbered data, and are loaded from the control circuit 303 into the shift registers 233 and 243. further,
Odd data and even data are latched by the latch circuits 234 and 244 from the shift registers 233 and 243 at the rise of the column latch signal LACOL, and thereafter, the column electrodes X are raised at the rise of the column output enable signal COLOE.
Potential of ₁ to X ₆₄₀ are respectively set in accordance with the brightness of pixels in two rows and 640 columns.

In this manner, the potential of each of the column electrodes X _{1 to} X ₆₄₀ is set in accordance with the brightness of the pixels of 640 columns for each of the rows 1 to 200.

Next, processing on the row side of the EL display device 201 will be described. First, the control circuit 303 inputs the vertical synchronization signal VS (shown in FIG. 6) from the image processing unit 302,
The horizontal synchronizing signal HS is input every 200 rows of scanning in one cycle of the vertical synchronizing signal VS. Then, the control circuit 303 supplies the row data signal Dro for 200 rows at the rise of the vertical synchronization signal VS.
w, and sends this row data signal Drow to each row-side IC 210 and 220. Each of the row-side ICs 210 and 220 inputs the row data signal Drow to each of the shift registers 212 and 222, respectively, and stores row data in these shift registers 212 and 222.

Further, the control circuit 303 forms a row clock signal Crow (shown in FIG. 6) obtained by dividing the horizontal synchronization signal HS by 1/2, and sends this row clock signal Crow to each row-side IC 210, 220. The row side IC 210 inputs the row clock signal Crow to the shift register 212. When the shift register 212 receives the row clock signal Crow, it outputs a high-level signal Q ₁ (shown in FIG. 6) to the AND circuit 213 corresponding to the row electrode Y ₁ based on the row data.
Add for one cycle of w. On the other hand, the row-side IC 220 inputs the row clock signal Crow to the shift register 222. Shift register 222 is the row clock signal in response to Crow, the high level on the basis of the raw data signal Q ₁ row electrodes Y ₂
And the row clock signal Crow 1
Add during the cycle. Therefore, the high level signal Q1 to the AND circuits 213 and 223 corresponding to each row electrodes Y _1, Y ₂ is applied between the two cycles between clogging horizontal synchronizing signal HS of the same one period of the row clock signal Crow.

Further, the control circuit 303 sends an odd-numbered row enable signal E Nodd and an even-numbered row enable signal E Neven synchronized with the horizontal synchronization signal HS to the respective row-side ICs 210 and 220. The row-side IC 210 inputs the odd-numbered row enable signal E Nodd to all the AND circuits 213 corresponding to the odd-numbered row electrodes. At this time, since the AND circuit 213 corresponding to the row electrode Y ₁ receives the high-level signal Q ₁ from the shift register 212, it applies a high-level signal to the FET 211 via the OR circuit 214. Then, the odd-numbered AND circuit 213 corresponding to the row electrodes enter a low-level signal based from the shift register 212 to the raw data, the OR circuit 21 a signal Therefore low level except the row electrodes Y ₁
Add to 4. The control circuit 303 is a vertical synchronization signal
The row strobe signal S Trow (shown in FIG. 6) which is at least high level during the period when VS is high level is output, and this row strobe signal S Trow is inverted through the knot circuit 215 of the low side IC 210 and all To the OR circuit 214. Therefore, OR circuit 2 corresponding to the row electrodes Y ₁
High-level signal from 14 is applied to the FET 211, FET 211 corresponding to the row electrodes Y ₁ is turned on. Further, the low level signal from the OR circuit 214 corresponding to the odd-numbered row electrodes except for the row electrodes Y ₁ is added to the FET 211, the row electrode Y
_The odd-numbered FETs 211 except ₁ are turned off.

On the other hand, in the low-side IC 220, the even-number row enable signal E Nev
en and all AND circuits 22 corresponding to even-numbered row electrodes
Enter 3 At this time, the AND circuit 223 corresponding to the row electrode Y ₂ outputs the high-level signal Q from the shift register 222.
_{Since 1} is input, the high level signal is
To the FET 221 via. Then, the AND circuit corresponding to the even-numbered row electrodes except for the row electrode Y ₂ 223 inputs the low level of the signal based on the raw data from the shift register 222, added to the signal of this for a low level to the OR circuit 224. In addition, all the OR circuits 224 input the inverted output of the knot circuit 225 to which the row strobe signal S Trow is input. Thus, from the OR circuit 224 corresponding to the row electrodes Y _2, a high level signal is applied to the FET 221, FET 221 corresponding to the row electrodes Y ₂ is turned on. Further, the low level signal from the OR circuit 224 corresponding to the even-numbered row electrodes except for the row electrode Y ₂ is applied to FET 221, FET 221 of the even-numbered row electrodes except for the row electrode Y ₂ is turned off.

That is, added to the AND circuits 213 and 223 the row clock signal Crow from the control circuit 303 signals to Q ₁ a high level from the shift registers 212 and 222 during the high level corresponding to each row electrodes Y ₁ and Y ₂ ,
At this time, the odd row enable signal E Nodd and the even row enable signal E Neven are supplied to the AND circuits 213 and 223.
Are sequentially added. Accordingly, the FETs 211 and 221 connected to the row electrodes Y ₁ and Y ₂ are sequentially turned on.

When the row clock signal Crow being output from the control circuit 303 then rises, the AND circuit signal Q ₂ of the high level from the shift register 212 and 222 corresponding to each column electrode Y ₃ and Y ₄ 213 and 223
Is output to And these AND circuits 213 and 2
23 has an odd enable signal E from the control circuit 303.
Since Nodd and the even enable signal ENeven are sequentially applied, a high-level signal is sequentially applied from the AND circuits 213 and 223 to the respective FETs 211 and 221 via the respective OR circuits 214 and 224. As a result,
Each FET211 and 221 are sequentially turned on is connected to the respective row electrodes Y ₃ and Y _4.

Similarly, each of the row electrodes Y _{1 to} Y ₂₀₀
The FET 211 and each FET 221 are sequentially turned on for each row of the row electrodes Y _{1 to} Y ₂₀₀ .

Now, the composite row drive circuit 401 responds to the control of the control circuit 303 so that the horizontal synchronizing signal HS
6, the composite row drive output Prow (shown in FIG. 6) is output to the FETs 211 and 221 of the row-side ICs 210 and 220. This composite row drive output signal Prow
Indicates −120 V when the horizontal synchronization signal HS is at a high level. On the other hand, each FET 211 and each FET 221 are turned on for each row of each row electrode Y _{1 to} Y ₂₀₀ in synchronization with the horizontal synchronization signal HS. Therefore, −120 V is sequentially applied to each of the row electrodes Y _{1 to} Y ₂₀₀ via each of the FETs 211 and 221.

Here, for example, when the -120V is applied to the row electrodes Y _1, the data signal D of each column electrode X ₁ to X ₆₄₀ is the first row
+80 V is applied or grounded depending on the brightness based on IN. At this time, if the column electrodes X ₁ is assumed to be applied to the corresponding + 80V to "bright", the column electrodes Y ₁ is -
Since the voltage is 120 V, the potential difference at the intersection between the column electrode X ₁ and the row electrode Y ₁ is +80 V − (− 120 V) = 200 V, and the pixel of the thin-film EL element corresponding to the intersection emits light. Further, when the column electrode X ₃ is assumed to be grounded corresponding to "dark", the column electrode X ₃ since the row electrodes Y ₁ is -120V
Potential difference on the intersection of the row electrodes Y ₁ is 0V - (- 120V) = 1
20V, and the pixel of the thin film E element corresponding to the intersection does not emit light. Likewise, the row electrode Y ₁ and each of the column electrodes X _2, X ₄
Data signal DI potential difference first line on each intersection to X ₆₄₀
Each pixel is set to 200 V or 120 V based on N, whereby each pixel corresponding to each intersection emits light or does not emit light. Further, each of the row electrodes Y ₂ to
Each time −120 V is sequentially applied to Y ₂₀₀ , each of column electrodes X ₁ to X ₁ to Y ₂ based on each data signal DIN of the second to the 200 th rows.
X ₆₄₀ is or ground is applied to the + 80V. As a result, pixels of 640 × 200 dots in the EL display device 201 selectively emit light, and one pixel is projected on the EL display device 201. Thereafter, similarly, in response to the television signal continuously output from the personal computer 301, the EL
Pixels are sequentially projected on the display device 201.

By the way, the composite row drive circuit 401
The control circuit 303 is configured as shown in the figure.
, The signals A, B and C shown in FIG.

In the composite row drive circuit 401, a signal C shown in FIG. 8 is input from a terminal 501, and the signal C is applied to a waveform circuit 503 via a buffer 502. Waveform circuit 503
When the signal C goes high, the voltage at the tap position of the semi-fixed resistor 505 connected in series with the capacitor 504 becomes N-c
Added to the gate of hFET506. At this time, the gate bias voltage is obtained by dividing the reverse bias voltage of the Zener diode 507 by the tap of the semi-fixed resistor 505, and the bias of the N-ch FET 506 is set to be shallow by the tap position. Therefore, the N-ch FET 506 has a constant output current I
₅₀₆ flows.

In the output circuit 510, the output current _I506
511 is gradually charged, and the terminal voltage V _{511 of the} capacitor 511 is stored.
Gradually falls to -120 V applied to the N-ch FET 506. The terminal voltage V ₅₁₁ of the capacitor 511 is applied to the gate of the P-chFET ₅₁₂ . Since the P-chFET 512 has the drain connected to the ground via the resistor 513, it is used as a source follower circuit.

Next, when the signal C becomes low level, the gate bias voltage of the N-chFET 506 drops until the N-chFET 506 is turned off. At this time, the signal A input from the terminal 520 becomes high level and is applied to the waveform circuit 522 via the inversion buffer 521. In the waveform circuit 522, when the signal A goes high, the voltage at the tap position of the semi-fixed resistor 524 connected in series with the capacitor 523 drops, and this voltage becomes P-c
The P-chFET 525 is turned on because it is added to the gate of the hFET 525. The gate bias voltage of the P-chFET 525 is obtained by dividing the reverse bias voltage of the Zener diode 526 by the tap of the semi-fixed resistor 524, and the bias of the P-chFET 525 is set to be shallow by the tap position. Therefore, a constant output current I ₅₂₅ flows from the P-chFET ₅₂₅ to the capacitor 511 of the output circuit 510 via the diode 527.

Therefore, the already charged capacitor 511 is gradually discharged, and the terminal voltage V _{511 of the} capacitor ₅₁₁ becomes −120 V
To 0V gradually. Accordingly, the gate voltage of the P-ch FET 512 of the source follower circuit gradually increases.

Thus, when the signal C rises, the capacitor 511 becomes N-chF
The terminal voltage V ₅₁₁ is charged by a constant output current I ₅₀₆ flowing through the ET ₅₀₆ , and accordingly, the terminal voltage V ₅₁₁ gradually decreases to −120 V.
Also, when the signal A rises, the capacitor 511 becomes a P-ch FET 525.
Is discharged by a constant output current I ₅₂₅ flowing therethrough, and accordingly, the terminal voltage V 511 gradually increases to OV. As a result, the terminal voltage V ₅₁₁ of the capacitor 511 becomes a trapezoidal wave in response to the signals C and A, and the voltage signal of this trapezoidal wave becomes P
-Added to the gate of chFET512.

The P-ch FET 512 is used as a source follower circuit as described above, and has a trapezoidal terminal voltage V
Since it added to _511, thereby the voltage V ₅₁₃ of the trapezoidal wave P shown in FIG. 8 is generated at the terminal of the resistor 513. The voltage V ₅₁₃ of the trapezoidal wave P is applied to the automatic switching circuit 530. Diode 53 in automatic switching circuit 530
1. A potential based on the voltage V ₅₁₃ of the trapezoidal wave P is generated between the parallel circuit composed of the capacitor 532 and the resistor 533 and the Zener diode 534, and the N-ch FET 535 is turned on. Therefore, the voltage V of the trapezoidal wave P output from the output circuit 510
₅₁₃ is the FET2 of the low side IC via the automatic switching circuit 530.
Added to 11 and 221.

Here, the period when the signal C is at the high level, that is, the trapezoidal wave P
During the period in which the voltage V ₅₁₃ falls and maintains approximately −120 V, one of the FETs 211 and 221 of the low-side IC is on. Therefore, it falls from 0V and falls approximately -12.
The voltage V ₅₁₃ maintaining 0 V is applied from the output circuit 510 to the row electrode of one row via the automatic switching circuit 530 and the FET whose row side IC is turned on. At this time, a voltage of +80 V can be applied to each of the column electrodes X _{1 to} X ₆₄₀ through the FET 231 or FET 241 of the column side IC, or the column electrode X
Or it is grounded via FET242. For this reason,
The row electrode to which 120 V is applied and the column electrodes X _{1 to} X
_On each intersection with ₆₄₀ , a potential difference of 200 V or 120 V is set in the forward direction, and pixels on each intersection emit or do not emit light.

Next, the signal A becomes high level and the voltage V of the trapezoidal wave P becomes
During the period when ₅₁₃ falls from approximately −120 V to approximately 0 V, each of the column electrodes X _{1 to} X ₆₄₀ is grounded via the FETs 232 and 242 of the column side IC. At this time, the P-ch FET 525 of the waveform circuit 522 →
Diode 527 → Diode 515 of output circuit 510 → N-chF
Parasitic diode D2 of ET535 → Parasitic diode D1 of low-side IC FET → Row electrode → Thin film EL element → Column electrode → Column side
A current flows through the paths of the FETs 232 and 242 of the IC, and approximately -12
The charge of the EL display device 201 charged by applying 0 V is discharged. Accordingly, the voltage of the row electrodes substantially -120V is applied rises like the voltage V ₅₁₃ of the trapezoidal wave P from approximately -120V to approximately 0V. The terminal voltage V ₅₁₃ of the resistor 513 becomes to 0V, and the charge of the capacitor 532 in the automatic switching circuit 530 is discharged through the diode 531. As a result, the gate side of the N-ch FET 535 becomes the ground potential,
FET535 turns off.

Next, when the scanning of all 200 rows in the EL display device 201 is completed and the vertical synchronizing signal VS falls, the signal B rises and goes high. This signal B is supplied from the terminal 541 to the inversion buffer 542.
To the output circuit 543. In the output circuit 543, when the signal B goes high, the voltage at the tap position of the semi-fixed resistor 545 connected in series with the capacitor 544 drops, and this voltage is applied to the gate of the P-ch FET 546.
chFET546 turns on. The gate bias voltage of the P-chFET 546 is obtained by dividing the reverse bias voltage of the zener diode 547 by the tap of the semi-fixed resistor 545, and the bias of the P-chFET 546 is set to be shallow by the position of the tap. Therefore, a constant output voltage I ₅₄₆ is output from the P-chFET ₅₄₆ .

At this time, the column output enable signal COLOE
Is low level, so the column side IC 230, 240 FET
232 and 242 are turned on, and all the column electrodes are grounded. Therefore, the constant output current I from the P-chFET 546
₅₄₆ is a parasitic diode D1 in the low-side IC FETs 211 and 221.
→ Row electrode → Thin film EL element → Column electrode → Column side IC FE
It flows on the route of T232,242. Accordingly, the EL display device 201
Row electrode gradually rises to a voltage Vpos of +200 V applied to the drain side of the P-chFET 546. Therefore,
A voltage of 200 V in the reverse direction of the trapezoidal wave M shown in FIG. 8 is applied to the EL display device 201.

Further, the signal A rises at the fall of the signal B, and the signal A is applied to the ground circuit 551. In the grounding circuit 551, the signal A is added to the semi-fixed resistor 552.
Is applied to the gate of the N-ch FET 553, and the N-ch FET 553 is turned on. At this time, since the row strobe signal STrow is at low level, the F
ET211,221 is on. In this case, the column side IC
Diode D2 in FET232 and 242 → column electrode →
An EL display device in which a current flows through the thin film EL element → row electrode → row FET 211,221 of the IC → diode 554 of the ground circuit 551 → N-chFET 553, and the row electrode is charged to + 200V.
The charge of 201 is discharged. Here, by adjusting the tap position of the semi-fixed resistor 552 in the ground circuit 551, N
The bias of the -ch FET ₅₅₃ is set shallow so that a constant output current I ₅₅₃ flows through the N-ch FET ₅₅₃ . Therefore, the EL display device 201 is discharged with the output current I ₅₅₃ of the N-ch FET _553, and the voltage of the row electrode becomes trapezoidal wave M shown in FIG.
Gradually drops from 200V to 0V as shown.

As described above, at the rise of the signal B, the EL display device 201 is charged by the output current I ₅₄₆ from the P-ch FET ₅₄₆ , and the voltage of the low electrode gradually rises to +200 V. After that, the output of the N-ch FET 553 becomes high at the high level of the signal A. EL display device 2 with current I ₅₅₃
01 is discharged, and the voltage of the row electrode gradually falls from + 200V to 0V. That is, the EL display device 201 is refreshed by the trapezoidal wave M indicating the reverse voltage of the maximum value of 200V.

Next, the column voltage supply section 601 is configured as shown in FIG. 9, and receives the signal D shown in FIG. 8 from the control circuit 303.

In the column voltage supply unit 601, a signal D is input from a terminal 611, and the signal D is applied to a waveform circuit 613 via an inversion buffer 612. In the waveform circuit 613, when the signal D becomes high level, the voltage at the tap position of the semi-fixed resistor 615 connected in series to the capacitor 614 drops, and this voltage becomes P-chF
The P-chFET 616 is turned on because it is applied to the gate of the ET 616. The gate bias voltage of the P-chFET 616 is obtained by dividing the reverse bias voltage of the Zener diode 617 by the tap of the semi-fixed resistor 615, and the bias of the P-chFET 616 is set to be shallow by the tap position. Therefore, a constant output current I ₆₁₆ is output from the P-chFET ₆₁₆ .

In the output circuit 620, the output current _I616
621 is gradually accumulated, and the terminal voltage V _{621 of the} capacitor 621 is
Gradually rises to 80 V applied to the P-chFET 616. The terminal voltage V ₆₂₁ of the capacitor 621 is applied to the gate of the N-ch FET 622. This N-chFET622 has a drain resistor
Since it is connected to the ground via 623, it is used as a source follower circuit.

Thereafter, when the signal D goes low, the P-chFET 616
Gate bias voltage rises until the P-chFET 616 is turned off.

On the other hand, the signal D is input to the grounding circuit 631 via the inverting buffer 624. When the signal D becomes low level, the voltage at the tap position of the semi-fixed resistor 633 rises,
-ChFET 634 is turned on, and a constant output current I ₆₃₄ flows. Therefore, the already charged capacitor 621 is gradually discharged, and the terminal voltage V _{621 of the} capacitor ₆₂₁ becomes 80 V
From 0 V to 0 V, so that the gate voltage of the N-ch FET 622 of the source follower circuit gradually decreases.

As described above, when the signal D rises, the capacitor 621 is charged by the output current I ₆₁₆ and the terminal voltage V ₆₂₁ gradually increases. When the signal D falls, the capacitor 621 is discharged by the output current I ₆₃₄ and the terminal voltage V ₆₂₁ is increased. Descend gradually. As a result, the terminal voltage V ₆₂₁ of the capacitor 621 becomes a trapezoidal wave voltage signal of the trapezoidal wave is applied to the gate of the N-chFET622.

The N-ch FET 622 is used as a source follower circuit as described above, and has a trapezoidal terminal voltage V _{621 at} its gate.
Is added to the terminal of the resistor 623,
A trapezoidal wave S shown in FIG. This trapezoidal wave S is on the column side
Added to IC FETs 231 and 241.

Here, the period when the signal D is at the high level, that is, the trapezoidal wave S
Is rising and maintaining 80V, the F of the column side IC
ET231 and 241 are selectively turned on. Therefore, 0
The voltage rising from V and maintaining 80 V is applied from the output circuit 620 to the respective column electrodes via the FETs 231 and 241 in which the column-side IC is turned on. At this time, since any of the row electrodes Y _{1 to} Y ₂₀₀ is applied with a voltage of −120 V through the FET of the row side IC, the row electrode to which −120 V is applied and the row electrode to which 80 V is applied are applied. A potential difference of 200 V is set in the forward direction on each intersection with each column electrode, and a pixel on each intersection emits light.

[Problems to be solved by the invention]

Incidentally, in the composite row drive circuit 401 shown in FIG. 7, the signal A is at a low level (ground potential).
Output of the inversion buffer 521 is high level (+ 12V)
Then, the capacitor 523 is charged with the output voltage of 12 V. When the signal A subsequently becomes high level, the output of the inversion buffer 521 becomes low level (ground potential), and the previously charged capacitor 523 is discharged. Then, as the capacitor 523 discharges, the semi-fixed resistor 524
Side voltage V ₅₂₃ drops to -12 V, which causes P-chFE
T525 turns on.

However, if the output of the inverting buffer 521 has been at the ground potential for a long time, all the charges of the capacitor 523 are discharged, and the voltage V ₅₂₃ rises from −12 V to the ground potential. In this state, even if the output of the inversion buffer 521 becomes 12 V in response to the signal A, this output voltage 12 V
Is short, the capacitor 523 cannot be charged sufficiently. For this reason, immediately after the output of the inversion buffer 521 becomes the ground potential, even if the capacitor 523 that has not been sufficiently charged is discharged, the voltage V ₅₂₃ does not drop from the ground potential to −12V. Therefore, the gate voltage of the P-chFET 525 did not drop sufficiently, and the P-chFET 525 could not be turned on.

If the P-chFET 525 cannot be turned on in this way,
After the capacitor 511 in the output circuit 510 is charged to -120 V in response to the signal C, the P-ch FET 5 responds to the signal A.
When it is discharged through 25, are not sufficiently discharged, the voltage V ₅₁₁ because this was not fit raised to the ground potential from -120 V. As a result, if voltage V ₅₁₁ is a gate voltage, P
-Ch FET 512 does not operate normally, and therefore the output voltage V ₅₁₃
In other words, a phenomenon occurs in which the waveform of the composite row drive output Prow becomes dull.

For example, the reverse voltage 200V of the trapezoidal wave M shown in FIG.
After refreshing in addition to the display device 201, the signal A is set to a high level (12 V) to turn on the N-ch FET 553 of the ground circuit 551, thereby discharging all the charges of the EL display device 201. At this time, the time during which the signal A is at the high level is long, and accordingly, the output of the inversion buffer 521 becomes the ground potential. Therefore, the capacitor 523 in the waveform circuit 522 is completely discharged. Thereafter, even when the signal A goes low at the start of scanning of the EL display device 201 and the output of the inversion buffer 521 goes high, the capacitor 523 is not sufficiently charged. Further, even if the signal A becomes high level and the output of the inversion buffer 521 becomes low level and the insufficiently charged capacitor 523 is discharged, the voltage V523 becomes −12.
It does not descend to V. As a result, the voltage V _{511 of the} capacitor 511 did not completely rise because the P-ch FET 525 was not completely turned on, so that the output voltage V ₅₁₃ of the P-ch FET 512, that is, the trapezoidal wave P shown in FIG. 8, did not rise sufficiently. . When the trapezoidal wave P does not rise sufficiently to the ground potential due to such a phenomenon, the charge of the EL display device 201 is sufficiently discharged after -120 V of the trapezoidal wave P is applied to the EL display device 201. Therefore, there is a problem that an afterimage is generated.

Therefore, an object of the present invention is to provide a driving circuit of an EL display device in which a voltage waveform applied to an electrode of the EL display device does not become dull.

[Means for solving the problem]

According to the present invention, a thin-film EL element is interposed between a row-side electrode and a column-side electrode arranged in a matrix direction, and a potential of each of the row-side electrode and the column-side electrode is selectively set. In the drive circuit of the EL display device that drives the thin-film EL element by setting to, a switching element that grounds the electrode when turned on, a resistor element and a capacitor that have one terminal grounded are connected in series. A series circuit in which a potential between the resistance element and the capacitor is applied to the switching element; and a ground potential between the resistance element and the capacitor by applying a binary signal consisting of a predetermined positive potential and a ground potential to the capacitor. And a negative potential, whereby the switching element is turned off and on, and a dummy pulse is applied to the capacitor immediately before applying the binary signal. Characterized in that a control means for applying.

[Action]

According to the present invention, the dummy pulse is applied to the capacitor immediately before the binary signal is applied to the capacitor, that is, when the binary signal is applied to the capacitor in a state where the charge of the capacitor is completely discharged. Immediately thereafter, that is, before the electric charge of the capacitor is completely discharged by the dummy pulse, a ground potential and a negative potential are generated between the resistance element and the capacitor by applying a binary signal to the capacitor.
For this reason, the negative potential generated between the resistance element and the capacitor has an appropriate value from the beginning when a binary signal is applied to the capacitor.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a control circuit to which an embodiment of the present invention is applied. The control circuit of this embodiment is used as the control circuit 303 shown in FIG. FIG. 1 particularly shows a portion that operates on the row electrode side, and omits a portion that operates on the column electrode side.

In FIG. 1, a vertical synchronizing rising detection and holding circuit 1 receives a vertical synchronizing signal VS (shown in FIG. 6) and outputs a detection signal G which rises to a high level when the vertical synchronizing signal VS rises. Output. This detection signal G is applied to the odd-row even-row detection circuit 2 and the edge detection circuit 3. Also,
An inverted detection signal obtained by inverting the detection signal G is applied to the pattern generator 4 from the vertical synchronization rising detection and holding circuit 1.

The odd-row / even-row detection circuit 3 is reset when the detection signal G rises, and thereafter sequentially detects the fall of the horizontal synchronization signal HS (shown in FIG. 6) after the rise of the vertical synchronization signal VS,
Every time the horizontal synchronizing signal HS falls, odd and even rows of horizontal scanning in the image are alternately detected, and a detection signal I indicating one of the detected odd and even rows is applied to the pattern generator 4. . That is, the detection signal I alternates between a high level and a low level every time the horizontal synchronizing signal HS falls, whereby the EL display 201
The odd rows and the even rows of the row electrodes Y _{1 to} Y ₂₀₀ are shown alternately from the first row.

On the other hand, the counter set clear circuit 5 outputs the horizontal synchronization signal HS
And resets the counter 6 every time the horizontal synchronizing signal HS falls after the rising of the vertical synchronizing signal VS. Each time the counter 6 is reset, it counts 64 μsec from the reset time based on the clock signal Cosc from the oscillator 7. Then, the counter 6 is 64 μsec from the reset time.
Is added to the putter generator 4 indicating the period up to the end of the time measurement. Here, a period from the reset time of the counter 6 to the end time of the clock, that is, 64 μsec, is substantially equal to one cycle of the horizontal synchronization signal HS.

Further, the vertical synchronizing polarity detecting circuit 8 receives the horizontal synchronizing signal HS and the vertical synchronizing signal VS. Each time the horizontal synchronizing signal HS falls, the vertical synchronizing signal VS is at a high level or a low level at the falling point. Is detected, and the vertical synchronization signal VS
Is applied to the pattern generator 4.

The pattern generator 4 includes an inversion detection signal from the vertical synchronization rising detection and holding circuit 1, a detection signal I from the odd row and even row detection circuit 2, a clock signal K from the counter 6, and a detection signal P from the vertical synchronization polarity detection circuit 8. And sends out various control signals and signals A, B, and C to the composite row drive circuit 401 via the latch circuit 9 based on these input signals.

That is, in the pattern generator 4, when the vertical synchronizing signal VS rises, whereby the inversion detection signal from the vertical synchronizing rising detection and holding circuit 1 changes from high level to low level, the row data signal Drow responds to this.
(Shown in FIG. 6) as a control signal. And
When the detection signal I from the odd-row / even-row detection circuit 2 is at a high level, that is, when the detection signal I indicates the low-row electrode in the EL display device 201, the timing signal K from the counter 6 indicates An odd row enable signal E Nodd (shown in FIG. 6) synchronized with the cycle of 64 μsec is transmitted as a control signal. When the detection signal I from the odd-row / even-row detection circuit 2 is at a low level, that is, when the detection signal I indicates the row electrode of the even-row in the EL display device 201, the clock signal K from the counter 6 is output. The even row enable signal E Neven (shown in FIG. 6) synchronized with the cycle of 64 μsec indicated by (1) is transmitted as a control signal. Further, the odd row enable signal E Nodd and the even row enable signal E Neve
A row clock signal Crow and a column output enable signal COLOE corresponding to n are output as control signals.

On the other hand, in the pattern generator 4, during the period when the vertical synchronizing signal VS is at a high level, and thus when the inversion detection signal from the vertical synchronizing rising detection and holding circuit 1 is at a low level, the odd row enable signal E Nodd and the even row A signal C (second signal) substantially synchronized with the logical sum of the enable signal E Neven
(Shown in the figure), and during the period when the vertical synchronizing signal VS is at the high level, the signal A which is an inverted signal of the signal C is transmitted.
(Shown in FIG. 2). The signal C is applied to a terminal 501 (shown in FIG. 7) of the composite row drive circuit 401, and the signal A is applied via an OR circuit 10 to a terminal 520 (shown in FIG. 7) of the composite row drive circuit 401. Can be

As described above, from the pattern generator 4, as various control signals, a row data signal Drow, an odd row enable signal E Nodd, an even row enable signal E Neven, a row clock signal Crow, a column output enable signal COLOE, and the like are transmitted. Control signals other than the output enable signal COLOE are applied to the low-side IC shown in FIG. The signal C and the signal A sent from the pattern generator 4 are applied to the composite row drive circuit 401.

As a result, as described above, the F
The ETs 211 and 221 are sequentially turned on, and the composite low drive circuit 401 outputs the signal C at a high level of -120 V
, A composite row drive output signal Prow (trapezoidal wave P shown in FIG. 2) at the high level of the signal A and the ground potential is sent to the FETs 211 and 221, whereby the row electrodes Y _{1 to} Y ₂₀₀ in the EL display device 201 are output. , A voltage of -120 V is sequentially applied.

Note that, as shown in FIG.
The column output enable signal COLOE rises in sequence slightly after the rise of each of the Nodd and even-number row enable signals ENeven. In this case, the odd row enable signal E Nodd and the even row enable signal
-120V to the row electrode in synchronization with one of E Neven
And +80 V is applied to the column electrode in synchronization with the column output enable signal COLOE, so that a slight delay occurs after the -120 V is applied from the row electrode side at the intersection of these row and column electrodes. Thus, +80 V is applied from the column electrode side. Therefore,
The potential difference on the intersection gradually increases, which results in EL
An excessive rush current is prevented from flowing through the display device 201.

Next, in FIG. 1, when the vertical synchronization signal VS falls, the vertical synchronization polarity detection circuit 8 thereafter detects that the vertical synchronization signal VS is at the low level at the falling of the horizontal synchronization signal HS,
The detection signal P indicating the low level of the vertical synchronization signal VS is applied to the pattern generator 4. When the pattern generator 4 receives the detection signal P indicating the low level of the vertical synchronization signal VS, it changes the standby reset signal U from the low level to the high level. This standby reset signal U is applied to the vertical synchronization rising detection and holding circuit 1 and the counter set clear circuit 5.

The vertical synchronization rising detection and holding circuit 1 outputs a standby reset signal U
Becomes high level, the detection signal G is changed from high level to low level, and the inversion detection signal is changed from low level to high level. At this time, when the detection signal G becomes low level, the odd-row even-number row detection circuit 2 stops detecting the falling of the horizontal synchronizing signal HS, and keeps the detection signal I at low level.

When the standby reset signal U becomes high level, the counter set clear circuit 5 stops the operation of resetting the counter 6 every time the horizontal synchronizing signal HS falls, and free-runs the counter 6 as it is. Thus, the counter 6 counts the time by 64 μm based on the clock signal Cosc from the oscillator 7.
This is longer than sec, that is, continues beyond one cycle of the horizontal synchronization signal HS.

Here, after the pattern generator 4 inputs the detection signal P indicating that the vertical synchronization signal VS from the vertical synchronization polarity detection circuit 8 has become low level, the pattern generator 4 becomes high level from the vertical synchronization rising detection holding circuit 1. In addition to the input of the inversion detection signal, the detection signal I, which is kept at the low level from the odd-numbered-even-numbered row detection circuit 2, is input. As a result, since the column output enable signal COLOE last falls, the pattern generator 4
Row clock signal Crow as various control signals, odd row enable signal E Nodd, even row enable signal E Ne
While keeping the ven and column output enable signals COLOE at a low level, the signals C and A are kept at a low level.

That is, the period vertical synchronizing signal VS is at the high level for each row electrodes Y ₁ to Y ₂₀₀ in the EL display device 201 -120
A voltage of V is sequentially applied, thereby completing the scanning and displaying one pixel on the EL display device 201. Thereafter, when the vertical synchronization signal VS becomes low level, the scanning is temporarily stopped.

At this time, the pattern generator 4 is inputting a clock signal Kf indicating the time that is being measured by the counter 6 that continues to run free. The time indicated by the clock signal Kf is an elapsed time from the first falling edge of the horizontal synchronization signal HS after the falling of the vertical synchronization signal VS.

Here, based on the time indicated by the clock signal Kf, the pattern generator 4 maintains the output signal B at a high level for about 200 μsec after the horizontal scanning of the EL display device 201 is stopped. This signal B is applied to a terminal 541 (shown in FIG. 7) of the composite row drive circuit 401. When the signal B goes high, the composite row drive circuit 401 applies a +200 V composite row drive output signal Prow (trapezoidal waveform M shown in FIG. 2) to the FETs 211 and 221 in the row-side ICs 210 and 220 shown in FIG. . This voltage 200V is applied to each row electrodes Y ₁ to Y ₂₀₀ through the parasitic diode of the respective FET211,221. Therefore, a reverse voltage of 200 V is applied to the EL display device 201 for approximately 200 μsec, thereby refreshing the EL display device 201.

Next, the pattern generator 4 sets the signal B based on the clock signal Kf from the counter 6 to a high level for a short time.
After elapse of 200 μsec, the signal B is changed to the low level, and the signal A is changed to the high level. This signal A is applied to a terminal 520 (shown in FIG. 7) of the composite row drive circuit 401. As a result, the composite row drive output signal P
The row output line is grounded through a composite row drive circuit 401.

At this time, the pattern generator 4 changes the row strobe signal STrow as a control signal from a high level to a low level. For this reason, FET21 of low side IC210,220
1,221 is turned on, so that each row electrode Y _{1 to} Y ₂₀₀
Grounded via 211, 221 and composite row drive circuit 401. As a result, the charge of the EL display device 201 that was charged at the time of the previous refresh is discharged.

Thus, when the vertical synchronizing signal VS is at the high level, the EL display device 201 is scanned and an image is taken out.
When S goes low, the EL display device 201 is refreshed.

Thereafter, the vertical synchronizing signal VS rises and goes high again. At this time, the vertical synchronization rising detection and holding circuit 1 is in a standby state in response to the high-level standby reset signal US, and when the vertical synchronization signal VS rises to a high level, the inversion detection signal falls to low. Level and
The detection signal G rises to a high level. When the detection signal G becomes high level, the odd-numbered-even-numbered row detection circuit 2 restarts detecting the falling of the horizontal synchronizing signal HS, and outputs high-level and low-level detection signals indicating odd-numbered rows and even-numbered rows of horizontal scanning. Send again. When the inversion detection signal goes low, the pattern generator 4 turns the signal A low and sets the standby reset signal U low. When the standby reset signal U goes low, the counter set clear circuit 5 resets the counter 6 every time the horizontal synchronizing signal HS falls. Each time the counter 6 is reset, one cycle of the horizontal synchronizing signal HS,
The timing signal K indicating 64 μsec is applied to the pattern generator 4 again.

Therefore, the pattern generator 4 outputs the vertical synchronizing signal
When VS rises, various control signals necessary for scanning are transmitted again from the subsequent fall of the horizontal synchronizing signal HS. As a result, scanning of the EL display device 201 is performed again, and EL
The next image is displayed on the display device 201.

By the way, when the vertical synchronization signal VS rises and the detection signal G output from the vertical synchronization rising detection and holding circuit 1 rises accordingly, the edge detection circuit 3 detects the rise of the detection signal G and outputs two pulses, for example. Is sent. Since these pulses pass through the OR circuit 10, the logical sum of each pulse and the signal from the pattern generator 4 is formed,
A signal indicating this logical sum is sent to the composite row drive circuit 401 as a signal A. Therefore, this signal A
Contains two dummy pulses dp corresponding to the respective pulses as shown in FIG. These dummy pulses dp are in a period from the rise of the vertical synchronization signal VS to the fall of the next horizontal synchronization signal HS, that is, the EL display device 20.
Occurs before the start of one scan. For this reason,
The respective dummy pulses dp do not affect the scanning of the EL display device 201. Note that these dummy pulses d
The pulse width of p is set to, for example, about 10 μsec to 30 μsec.

Now, the signal A is applied to the terminal 520 of the composite row drive circuit 401 shown in FIG. 7, and as described above, the signal A is at the high level during the period from the fall of the signal B to the rise of the vertical synchronization signal VS. Has been maintained. As a result, the N-ch FET 553 in the ground circuit 551 is turned on, and the charge of the EL display device 201 charged by the refresh is discharged.

On the other hand, since the signal A is at the high level during the period,
The output of the inverting buffer 521 becomes the ground potential, so that all the charges of the capacitor 523 in the waveform circuit 522 are discharged. However, immediately after the period, two dummy pulses dp of the signal A are applied to the inversion buffer 521, and the inversion buffer 521 outputs two pulses corresponding to each of the dummy pulses dp. As a result, the capacitor 523 repeats charging and discharging twice, and accumulates electric charge.

That is, when the signal A is at the ground potential immediately before the first dummy pulse dp, the output of the inversion buffer 521 becomes high level (+12 V), and at this time, the capacitor 523 is charged. When the output of the inversion buffer 521 becomes low level (ground potential) in response to the first dummy pulse dp, the charge of the capacitor 523 is slightly discharged, and accordingly, the voltage V ₅₂₃ on the semi-fixed resistor 524 side of the capacitor 523 is discharged. Descends. Next, when the signal A becomes the ground potential immediately before the second dummy pulse dp, the capacitor 523 is further charged by the output voltage of the inversion buffer 521 + 12V. Then, when the output of the inversion buffer 521 becomes the ground potential in response to the second dummy pulse dp, the charge of the capacitor 523 is slightly discharged, and the voltage V ₅₂₃ drops again accordingly.

When the two pulses output from the inversion buffer 521 are applied to the capacitor 523, the capacitor 523 can quickly accumulate electric charges. Immediately after this, when the signal A falls with the rise of the signal B, the output voltage of the inversion buffer 521 becomes + 12V. At this time, since the capacitor 523 has already accumulated a certain amount of charge, it is further charged and sufficiently charged. As a result, when the output of the inverting buffer 521 becomes the ground potential at the next rise of the signal A, the voltage V525 drops to -12 V with the discharge of the fully charged capacitor 523, and the P-ch FET 525 is reliably turned on. .

Therefore, when the signal C is at a high level, the EL display 201
-120 V is applied to the _first row electrode Y1, and the charged electric charge of the EL display device 201 at this time is completely discharged through the P-chFET 525 which is surely turned on when the signal A is at the high level.

That is, as shown in FIG. 2, the composite row drive output Prow reliably rises to the ground potential with the rise of the signal A from the beginning of scanning. Therefore, an afterimage does not occur in the EL display device 201.

As described above, in this embodiment, the output circuit is driven by the dummy pulse included in the signal A immediately before scanning of the EL display device 201 is performed.
Since the electric charge is previously stored in the capacitor 523 of the 522, the P-chFET 525 of the output circuit 522 is reliably turned on with the rise of the signal A during the scanning of the EL display device 210, so that the composite low drive output Signal Prow
Output waveform does not become dull, so the EL display device
There is no afterimage in 201. Although the case where two dummy pulses are included in the signal A has been described as an example, the present invention is not limited to this, and one dummy pulse or three or more dummy pulses may be appropriately included in the signal A. Although the output circuit 522 in the composite row drive circuit 401 has been illustrated, the switching element is turned on by a voltage drop due to the charging and discharging of the capacitor similarly to the output circuit 522, and thus the voltage waveform applied to the EL display device 201 is changed. If it is to be formed, the present invention can be applied effectively.

〔The invention's effect〕

As described above, according to the present invention, when a binary signal is applied to a capacitor in a state where all the charges of the capacitor have been discharged, a binary signal is applied after a dummy pulse is applied to the capacitor. Therefore, the negative potential generated due to the charging and discharging of the capacitor to which the binary signal is added can be set to an appropriate level from the beginning. Therefore, the switching element is reliably turned on by the negative potential, and the voltage waveform applied to the electrode of the EL display device through the switching element does not become dull.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a control circuit to which one embodiment of the present invention is applied, FIG. 2 is a timing chart showing signals in the embodiment shown in FIG. 1, and FIG. FIG. 4 is a graph showing a voltage-luminance characteristic of the EL display device, FIG. 5 is a block circuit diagram showing a device using the EL display device as a terminal of a personal computer, and FIG. 7 is a timing chart showing each signal in the device shown in FIG. 7, FIG. 7 is a circuit diagram showing a composite row drive circuit in the device shown in FIG. 5, and FIG. 8 is a conventional circuit diagram in the composite row drive circuit shown in FIG. FIG. 9 is a circuit diagram showing a column voltage supply unit in the device shown in FIG. 1 ... vertical synchronous rising detection and holding circuit, 2 ... odd and even row detection circuit, 3 ... edge detection circuit, 4 ... pattern generator, 5 ... counter set clear circuit, 6 ...
Counter 7 Oscillator 8 Vertical sync polarity detection circuit 9 Latch circuit 10 OR circuit 210 and 220
Row side IC, 230, 240 ... Column side IC, 301 ... Personal computer, 302 ... Image conversion unit, 303 ... Control circuit, 401 ... Composite row drive circuit, 601 ...
... Column voltage supply section.

Claims (1)

(57) [Claims] A thin film EL element is interposed between a column electrode sequentially arranged in a row direction and extending in a column direction and a row electrode sequentially arranged in a column direction and extending in a row direction. A vertical synchronization signal, a data signal and a clock signal, and selectively setting respective potentials of the column electrode and the row electrode in the synchronization period indicated by the vertical synchronization signal based on the data signal. A first capacitor that has a driving period for driving the thin-film EL element and a refresh period for performing a refresh process for refreshing the column electrode and the row electrode outside the synchronization period indicated by the vertical synchronization signal, and performs charge and discharge of electric charge; The first switching element (51) uses the voltage of (511) as a switching voltage.
2) turning on and off, and applying an electric voltage to the first capacitor (511) in synchronization with a leading edge of the horizontal synchronizing signal, and an output circuit (510) for applying the electric potential to the low electrode when on. A first circuit (503) for turning on the output circuit by charging, forming a pulse leading edge in synchronization with a pulse trailing edge of the pulse for performing the refresh and a pulse trailing edge of the horizontal synchronization signal; A first pulse generating circuit that forms a first pulse signal (signal A in FIG. 8) that forms a leading pulse in synchronization with a trailing edge of the horizontal synchronizing signal; The second capacitor (52
3) charging / discharging the charge, turning on the second switching element (525) based on the negative potential generated at the time of charging, discharging the first capacitor (511), and discharging the output circuit of the output circuit. A second circuit for turning off the first switching element (512) and forming a closed circuit for discharging the electric charge of the low electrode by the electric potential applied to the low electrode to return the electric potential of the low electrode to the reference initial electric potential. A driving circuit for an EL display device, comprising: a second pulse signal comprising one or more pulses from a leading edge of the vertical synchronizing signal to a first leading edge of the horizontal synchronizing signal. A second pulse generation circuit that generates a logical sum circuit (10) that generates a logical sum signal (signal A in FIG. 2) of a logical sum of the first pulse signal and the second pulse signal And the second circuit (522) comprises: The logical OR signal (signal A in FIG. 2) is used as the first pulse signal, and the second pulse signal between the leading edge of the vertical synchronizing signal and the first leading edge of the horizontal synchronizing signal is used as the first pulse signal. EL that charges and discharges the second capacitor (523) repeatedly by a corresponding dummy pulse in the logical sum signal to reliably operate the second switching element (525). A driving circuit of a display device.