JPH04282610A - Active matrix display device - Google Patents

Abstract

PURPOSE:To eliminate the influence of punch-through effect upon the display quality even when plural scanning electrodes are selected at the same time on the auxiliary capacity connection type active matrix display device on which the scanning electrodes are shared. CONSTITUTION:For the simultaneous selective scan driving of plural scanning electrodes of an active matrix display panel which has a thin film transistor(TFT), a liquid crystal display element 4, and a capacitor 4 in each of areas surrounded with plural matrix-wired signal electrodes Y and scanning electrodes X, a control means which performs control so as to drive selective scanning electrodes while the OFF timing of a selective scan signal applied to respective liquid crystal display element 3 through two scanning electrodes of odd and even lines selected in a selective scan period is given a time difference t between the respective selective scanning electrodes is provided, and this control means consists of an odd electrode scan side driver 11 and an even electrode scan side driver 12 provided corresponding to the scanning lines for the odd and even lines.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an active matrix display device having an active switching element in each pixel in a flat display, and more particularly to an active matrix display device having an auxiliary capacitor connected in parallel with the display element in an alternating current manner. It is related to.

0002

2. Description of the Related Art A typical active matrix display device is an active matrix display device used in monitor TVs and various terminal display devices. In conventional active matrix display panels, an auxiliary capacitor with a capacity several times that of the liquid crystal display element is connected in parallel with each liquid crystal display element in order to suppress changes in load capacitance due to the dielectric anisotropic characteristics of the liquid crystal display element. has been done. However, in order to form the auxiliary capacitor, an independent auxiliary capacitor electrode must be provided for applying a potential, and a dedicated mask for this purpose is required in the process. Regarding the auxiliary capacitance electrode, a method that allows a simple process is to share a part of the bus electrode for controlling the active element as the auxiliary capacitance electrode.

FIG. 5 is a circuit diagram showing a pixel configuration of an active matrix display panel in a conventional active matrix display device. In FIG. 5, a plurality of signal electrodes Y
Among them, the j-th signal electrode Yj is commonly connected to the source electrode of the thin film transistor 1 as a switching element, and supplies a signal voltage corresponding to the display data signal to the source electrode of the thin film transistor 1. Further, the scanning side driver 2 selectively sequentially applies a gate voltage to the gate electrode of the thin film transistor 1 via each of the scanning electrodes X every scanning period to perform line sequential scanning. This thin film transistor 1
The drain electrode is connected to the pixel electrode of the liquid crystal display element 3 that displays one pixel, and supplies a driving voltage to the liquid crystal display element 3 via the drain electrode of the thin film transistor 1. Further, the drain electrode of this thin film transistor 1 is connected to an auxiliary capacitor 4.
one end of the auxiliary capacitor 4, and the other end of the auxiliary capacitor 4 is connected to the adjacent scan electrode X, for example, the i-th scan electrode X among the scan electrodes X.
auxiliary capacitor 4 to which i is connected via thin film transistor 1
In this case, it is connected to the adjacent scanning electrode Xi-1. The other end of the liquid crystal display element 3 is connected to a counter electrode 5 that is commonly connected to each liquid crystal display element 3. A pixel 6 is constituted by a set of the thin film transistor 1, the liquid crystal display element 3, and the auxiliary capacitor 4. As shown in this example, for example, the gate electrode of the thin film transistor 1 is connected to the scan electrode Xi, and the method of connecting the auxiliary capacitor 4 to the scan electrode Xi-1 at the previous stage is referred to as a front-stage gate-connected auxiliary capacitor. It is called. On the other hand, as shown in FIG. 6, the gate electrodes of the thin film transistors 1 are connected to each other,
For example, for the i-th scan electrode Xi of the scan electrodes X, a method in which the auxiliary capacitor 4 is connected to the subsequent scan electrode Xi-1 is called a rear-stage gate-connected auxiliary capacitor. In this example, the scanning side driver 2 in FIG. 5 is divided into an odd electrode side driver 2a and an even electrode side driver 2b corresponding to the scanning electrodes of odd and even lines, respectively. Note that 7 is a parasitic capacitance between the gate and drain of the thin film transistor 1.

The operation of the conventional active matrix display device having the above-mentioned front-stage gate-connected auxiliary capacitance structure will be described below. When performing line sequential scanning using the scanning driver 2, various display modes (for example, 1280x
960 dots, 640 x 480 dots, 640
×240 dots, etc.) or to configure one pixel with multiple dots to increase redundancy against pixel defects, the conventional selection of one scan electrode per scan period must be changed from the conventional selection of one scan electrode per scan period to the selection of multiple scan electrodes. It is necessary to drive simultaneous selection. In such simultaneous selection scan driving of a plurality of scan electrodes, the scan electrode X1 as shown in FIG.
, X2 , scanning electrodes X3 , X4 , ... scanning electrodes X
Sequentially and simultaneously select two scanning electrodes of odd and even lines such as n-1 and Xn (simultaneous on, simultaneous off)
Let us consider the voltage accumulated in the liquid crystal display element 3 when line sequential scanning driving is performed at the timing of . Here, if the total number of scanning electrodes is n, the number of display data signals in the scanning direction is n/2, D1 to Dn/2. The load of the pixel 6 is basically a capacitive load, and is driven by an AC drive voltage whose polarity is inverted every frame. On the other hand, when driving an active matrix display panel, due to the parasitic capacitance 7 between the gate and drain of the thin film transistor 1, the liquid crystal display is displayed due to the penetration effect of the rapid voltage change when the gate voltage Vg supplied from the scanning electrode X at the time of selection is turned off. The potential of element 3 will change.

As mentioned above, FIG. 8 shows the state of the liquid crystal display element voltage when the two scanning electrodes X are simultaneously selected and line sequential scanning driving is performed, and A in FIG. The voltage waveform of the liquid crystal display element is shown, and B in FIG. 8 shows the voltage waveform of the lower liquid crystal display element. In FIG. 8, Vic is the liquid crystal display element voltage, Vs is the input signal voltage, Vc is the counter voltage applied to the counter electrode 5, 1H is one scanning period, and 1V is one frame. First, the upper stage liquid crystal display element voltage is the input signal voltage Vg applied to the liquid crystal display element 3 at the time of selection.
s is charged and receives a punch-through effect when the gate voltage Vg falls to become non-selected. This punch-through voltage ΔV
1 is expressed by the following formula.

[0006] ΔV1 = Vg·Cgd/(Cgd+Cic+Cs) where Cgd is a gate-drain parasitic capacitance, Cic is a liquid crystal capacitance, and Cs is an auxiliary capacitance.

Since this punch-through voltage ΔV1 occurs when the gate voltage Vg falls, its influence acts in the negative potential direction. Therefore, the effective signal voltage Vd1 is subtracted for the input signal voltage +Vs of positive polarity, and added for the input signal voltage -Vs of negative polarity, so the effective signal voltage Vd1 is
d1 = ((Vs-ΔV1)+(Vs+ΔV1))
/2=Vs, and the counter voltage Vc is shifted by -ΔV1 (
By shifting from the one-dot chain line to the actual battle), it is possible to substantially make it less susceptible to the impact of the piercing effect.

Next, as for the voltage of the lower liquid crystal display element, the selected gate voltage Vg is applied to the scanning electrodes Xi, Xi+1 (
Since i is applied from 1 to n-1), it receives a punch-through effect from both the gate-drain parasitic capacitance Cgd and the auxiliary capacitance Cs. Similarly, the punch-through voltage ΔV2 is determined by the following equation.

ΔV2 = Vg・(Cgd+Cs)/(Cgd+Cs
ic+Cs) ≒Vg・Cs/(Cgd
+Cic+Cs)≫ΔV1, and the opposing voltage Vc is -
By shifting ΔV2 (shifting from the one-dot chain line to the actual operation), the effective signal voltage Vd2 becomes the input signal voltage Vs, so that it can be made less susceptible to the punch-through effect. As is clear from the above equation, the punch-through voltage ΔV2 reaches a level that is Cs/Cgd times the punch-through voltage ΔV1.

[0010] Here, a case has been described in which line sequential scanning driving is performed by simultaneously scanning two scanning electrodes on an odd numbered line and an even numbered line, but it is possible to simultaneously select any n scanning electrodes (a≧2). Even in the case of
becomes.

[0011]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional configuration, the two scan electrodes of the odd and even lines are selected simultaneously to perform line sequential scanning drive, so the punch-through voltages ΔV1 and ΔV2 are generated at the same timing. Occur. Therefore, the shift voltage amount (ΔV1
or ΔV2 ) cannot be optimized, for example, (Δ
It is necessary to set the average shift voltage amount to V1 + ΔV2 )/2. In this case, the alternating current balance between each frame is disrupted, and a direct current component is generated in the liquid crystal display element 3, resulting in flicker, afterimage generation, and decreased reliability.

[0012] Furthermore, in the lower stage liquid crystal display element, the punch-through voltage ΔV2 is large (ΔV2 ≫ ΔV1);
The effective signal voltage level at the time of negative polarity becomes deeper and there is no margin with the gate voltage Vg, or becomes more negative than the gate voltage Vg, resulting in incomplete off-operation of the thin film transistor 1. On the other hand, in an active matrix display device with a rear-stage gate-connected auxiliary capacitor configuration, contrary to the above, the punch-through voltage of the upper stage liquid crystal display element is Δ
V2, and the punch-through voltage of the lower liquid crystal display element is ΔV.
1, and as a result, leakage of the signal voltage charged in the liquid crystal display element 3 and crosstalk between adjacent pixel signal voltages occur, resulting in a decrease or change in brightness and a difference between the upper liquid crystal display element and the upper liquid crystal display element. This results in an unbalance in the brightness of the image, which significantly reduces display quality.

Furthermore, as a method of eliminating the influence of the punch-through voltage ΔV2, the drive timing shown in FIG.
One scanning period is 1/2H between odd numbered scanning electrodes and even numbered scanning electrodes.
By performing double-speed scanning drive in which each line is selectively divided, it appears to be normal simple line sequential scanning, and by ensuring that the potential of the front-stage scanning electrode to which the auxiliary capacitor is connected is at the low level of the gate voltage, Since the punch-through voltage can be set to ΔV1 for all the liquid crystal display elements, the remarkable problem encountered during simultaneous selection scanning described above is eliminated. On the other hand, the actual charging time for the liquid crystal display element is halved (particularly in the case of high definition, one scanning period becomes extremely short), which can lead to uneven brightness due to insufficient charging time. I had a problem.

The present invention solves the above-mentioned conventional problems, and in an auxiliary capacitor-connected active matrix display device in which scan electrodes are shared, the display quality is not affected by the punch-through effect even if a plurality of scan electrodes are selected simultaneously. It is an object of the present invention to provide an active matrix display device that is not affected by this.

[0015]

[Means for Solving the Problems] In order to solve the above problems, an active matrix display device of the present invention includes a plurality of signal electrodes and scanning electrodes arranged in a matrix,
Within a region encompassed by each of the signal electrodes and scanning electrodes, a switch element controlled by a signal from the scan electrode, a display element driven by the switch element, an intersection between the switch element and the display element, and When simultaneously selecting and scanning driving multiple scanning electrodes of an active matrix display panel having auxiliary capacitors connected between adjacent scanning electrodes,
The OFF timing of the selection scan signal applied to each of the switch elements via the plurality of scan electrodes selected during the selection scan period is driven by sequentially giving a time difference of Δt between each of the selection scan electrodes. It is equipped with a control means for controlling.

[0016]

[Operation] According to the above structure, the control pulse voltages applied simultaneously to the switch elements are sequentially given a time difference of Δt between each scanning electrode, so that the off-times of the plurality of switch elements after simultaneous selection are shifted by Δt. Therefore, during the ON period of the switch element, the control voltage of the scan electrode to which the auxiliary capacitor is connected is turned off first, so when this switch element is turned off, the potential of the scan electrode to which the auxiliary capacitor is connected is Stable at low level constant potential. As a result, for example, when selecting two scan electrodes simultaneously and sequentially selecting them, the component of the punch-through voltage ΔV2 generated in the lower liquid crystal display element due to the auxiliary capacitance is eliminated, and as a result, For all liquid crystal display elements, the punch-through voltage due to the punch-through effect is a low level shift amount of the punch-through voltage ΔV1 due to the gate-drain regulation capacitance, so it is possible to balance the drive voltage with the counter voltage.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the same reference numerals are given to those having the same functions and effects as those of the conventional example, and the explanation thereof will be omitted.

FIG. 1 is a configuration diagram of a front-stage gate-connected auxiliary capacitance type liquid crystal display panel of an active matrix display device according to a first embodiment of the present invention.
This shows the case where the scanning electrodes of the book are selected simultaneously and the selection is performed sequentially. In FIG. 1, a plurality of scan electrodes of an active matrix display panel has a thin film transistor 1, a liquid crystal display element 3, and an auxiliary capacitor 4 in each region encompassed by a plurality of signal electrodes Y and scan electrodes X arranged in a matrix. During simultaneous selection scan driving, the off timing of the selection scan signal of the odd line applied to each liquid crystal display element 3 via the two scan electrodes selected during the selection scan period is set to the timing of the selection scan signal of the even line. A control means is provided for controlling the selected scan electrodes to be driven sequentially by a period of Δt from the off-time timing, and this control means is provided corresponding to each of the scan electrodes on odd-numbered lines and even-numbered lines. It is composed of an odd-numbered electrode scanning side driver 11 and an even-numbered electrode scanning side driver 12.

FIG. 2 shows a drive timing diagram of the active matrix display device in FIG. In FIG. 2, simultaneous selection line sequential scanning by the odd-numbered electrode scanning side driver 11 and the even-numbered electrode scanning side driver 12 is performed by scanning electrodes X1
, X2 , scanning electrodes X3 , X4 , ... scanning electrodes X
Two scanning electrodes such as n-1 and Xn are selected at the same time. At this time, the off timing of the gate voltage Vg of the upper scan electrodes X1, X3, . . . It precedes the off timing by Δt. Such a time difference Δ
t, when the gate voltage Vg of the lower scanning electrodes X2, X4...Xn is turned off, the upper scanning electrodes X1, X3...
Since the gate voltage Vg is at a low level, the lower liquid crystal display element 3 can be substantially driven in the same manner as the upper liquid crystal display element 3, so the auxiliary capacitor 4 is
The penetration effect of the gate voltage Vg of the upper scanning electrode via the capacitance Cs no longer occurs. Therefore, the punch-through voltage of the lower liquid crystal display element 3 can be reduced from ΔV2 to ΔV1. Therefore, the punch-through voltage due to the punch-through effect for all liquid crystal display elements 3 becomes a low level shift amount of ΔV1 due to the capacitance Cgd of the gate-drain parasitic capacitance 7, so it is possible to balance the driving voltage with the opposing voltage. .

By the way, while the thin film transistor 1 of the lower liquid crystal display element 3 is turned on, the potential difference between the change level of the gate voltage Vg of the upper scan electrodes X1, X3, . . . If it is not charged or discharged, a part of the input signal voltage Vs charged in the liquid crystal display element 3 will flow to the auxiliary capacitor 4, which will cause the liquid crystal display element voltage to fluctuate and normal pixel display will not be possible. . Therefore, the value of the time difference Δt needs to be long enough to charge or discharge the potential difference of the auxiliary capacitor 4 described above. This time difference Δt is determined by the lower liquid crystal display element 3.
The potential difference ΔVgs between the voltage level of the pixel electrode (input signal voltage Vs) when the thin film transistor 1 is turned on and the gate voltage level of the upper scanning electrodes X1, X3, . . . It is defined by the supply capacity Id and the capacity Cs of the auxiliary capacitor 4. Let's make a rough estimate using the following conditions, which are relatively large estimates.

ΔVgs=20V, Id=10-4 to 10-5A, Cs
= 1 pF Furthermore, a potential difference ΔVg is applied to the capacitance Cs of the auxiliary capacitor 4.
The amount of charge Q for charging and discharging s is expressed by the following equation.

Q=Cs・ΔVgs Furthermore, since the relationship between the amount of charge Q and the current I is I=Q/T, Δt=T=Q/I=Cs・ΔVgs/Id=0.2 ~
2.10-6 sec, and it is sufficient to consider Δt to be several microseconds at most. This value is the normal one scanning period (1H)
This is a very small amount of time compared to , and can be effectively used over approximately one scanning period (1H) as the charging time for the liquid crystal display element 1 . In actual scan driving, the scanning driver is divided into odd-numbered blocks and even-numbered blocks, and the clock signal of the odd-numbered electrode scanning side driver 11 of the odd-numbered block is advanced by Δt from the clock signal of the even-numbered electrode scanning side driver 12 of the even-numbered block, so that the clock signal is simultaneous. Generally speaking, when a plurality (a) of simultaneously selected scanning electrodes are selected, the off timing of the gate electrode of the lower scanning electrode is set by Δ with respect to the upper scanning electrode.
The delay may be delayed by t, or control may be performed by setting Δt=(1/a)H. Note that with this driving method, the display data signal voltage of the previous scanning period is charged for a maximum period of Δt(a-1), but the remaining (1H)
Since the original display data signal voltage can be charged in the time period of -Δt(a-1))>Δt, there is no problem regarding the overlap of the display data signal voltages.

FIG. 3 is a configuration diagram of a rear-stage gate-connected auxiliary capacitance type liquid crystal display panel of an active matrix display device according to a second embodiment of the present invention, in which two scanning electrodes are simultaneously selected and selected sequentially. The case is shown below. In FIG. 3, a plurality of scan electrodes of an active matrix display panel has a thin film transistor 1, a liquid crystal display element 3, and an auxiliary capacitor 4 in each region encompassed by a plurality of signal electrodes Y and scan electrodes X arranged in a matrix. During simultaneous selection scan driving, the off timing of the selection scan signal of the odd line applied to each liquid crystal display element 3 via the two scan electrodes selected during the selection scan period is set to the timing of the selection scan signal of the even line. An odd-numbered electrode scanning side driver 21 and an even-numbered electrode scanning side driver 22 are provided as control means for controlling each selected scanning electrode to be driven with a time delay of Δt sequentially from the off-time timing.

FIG. 4 shows a driving timing diagram of the active matrix display device in FIG. 3. In FIG. In FIG. 4, the gate voltage Vg of the upper scanning electrodes X1, X3, . . .
The off timing of the gate voltages Vg of the lower scan electrodes X2, X4, . . . Such a time difference Δt
If given, upper scanning electrodes X1, X3...Xn-1
When the gate voltage Vg of the lower scanning electrodes X2, X4, . . . Since the same driving state as that of the lower liquid crystal display element 3 can be achieved, the penetration effect of the gate voltage Vg of the lower scan electrode via the capacitance Cs of the auxiliary capacitor 4 as in the conventional case does not occur. Therefore, the punch-through voltage of the upper liquid crystal display element 3 can be reduced from ΔV2 to ΔV1. Therefore, the punch-through voltage due to the punch-through effect for all liquid crystal display elements 3 becomes a low level shift amount of ΔV1 due to the capacitance Cgd of the gate-drain parasitic capacitance 7, so it is possible to balance the driving voltage with the opposing voltage. . Note that the conditions for Δt are the same as in the case of the pre-stage gate-connected auxiliary capacitor type described above.

Regarding the phase difference of Δt in actual scan driving, for example, divide blocks into odd-numbered blocks and even-numbered blocks, and use the scanning clock signal of the odd-numbered electrode scanning side driver 21 of the odd-numbered block to the even-numbered electrode scanning side driver 22 of the even-numbered block. The scan clock signal is delayed by Δt from the scan clock signal, or the scan clock signal with a duty ratio of Δt/1H is set to have a 180 degree phase difference between the odd electrode scan side driver 21 of the odd block and the even electrode scan side driver 22 of the even block. Generally, multiple (a) selections are scanned simultaneously.
For the number of simultaneously selected scanning electrodes, the off timing of the gate electrode of the upper scanning electrode should be delayed by Δt relative to the lower scanning electrode, or the control should be performed by setting Δt=(1/a)H. Bye.

In the first and second embodiments, a liquid crystal was used as an example of a display element, but a plasma (PD)
P), electroluminescence (EL), fluorescent display (VFD), etc., the same effects as in the first and second embodiments can be obtained if the active matrix display device is equipped with an auxiliary capacitor.

[0027]

As described above, according to the present invention, simultaneous selection line sequential scanning driving of a plurality of scanning electrodes of an active matrix display device in which the auxiliary capacitance of a pixel is connected to an adjacent scanning electrode at the front or rear stage can be performed. , it is possible to eliminate the punch-through effect of the gate voltage via the auxiliary capacitance and improve the display quality.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a front-stage gate-connected auxiliary capacitance type liquid crystal display panel of an active matrix display device according to a first embodiment of the present invention.

FIG. 2 shows a drive timing diagram of the active matrix display device in FIG. 1;

FIG. 3 is a configuration diagram of a rear-stage gate-connected auxiliary capacitance type liquid crystal display panel of an active matrix display device according to a second embodiment of the present invention.

FIG. 4 shows a drive timing diagram of the active matrix display device in FIG. 3;

FIG. 5 is a configuration diagram of a front-stage gate-connected auxiliary capacitance type liquid crystal display panel of a conventional active matrix display device.

FIG. 6 is a configuration diagram of a rear-stage gate-connected auxiliary capacitance type liquid crystal display panel of a conventional active matrix display device.

7 shows a drive timing diagram of the active matrix display device in FIG. 5. FIG.

FIG. 8 shows liquid crystal display element voltage waveforms during simultaneous selection line sequential scanning driving, where A is a voltage waveform diagram of an upper stage liquid crystal display element and B is a voltage waveform diagram of a lower stage liquid crystal display element.

9 shows a drive timing diagram of the active matrix display device in FIG. 6. FIG.

[Explanation of symbols]

1 Thin film transistor 3. Liquid crystal display element 4 Auxiliary capacity

Claims (1)

[Claims] 1. A plurality of signal electrodes and scanning electrodes arranged in a matrix are provided, and a switch element controlled by a signal from the scanning electrode is provided in a region encompassed by each of the signal electrodes and scanning electrodes; Simultaneous selection of multiple scan electrodes of an active matrix display panel having a display element driven by a switch element and an auxiliary capacitor connected between the intersection of the switch element and the display element and between adjacent scan electrodes. The off timing of the selection scan signal applied to each of the switch elements via the plurality of scan electrodes selected during the scan period is driven by sequentially giving a time difference of Δt between each of the selection scan electrodes. An active matrix display device comprising control means for controlling.