JPH08136618A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To highly accurately and highly efficiently inspect the phase variation of timing signals even under a high-speed condition by incorporating a phase shift detecting circuit in an LSI which generates and processes a plurality of timing signals. CONSTITUTION: An LSI 100 is a clock distributing LSI which generates and outputs a plurality of timing signals (clock signals) Al-An of the uniform phase. In the LSI 100, a signal processing circuit 101 which generates the timing signals A1-An and a phase shift detecting circuit 1 which detects whether or not the maximum phase difference among the signals A1-An exceeds a prescribed range and outputs detected results to the outside are integrally formed. Therefore, the phase fluctuation of the timing signals generated and processed by the LSI 100 can be inspected in the LSI 100 with high accuracy and high efficiency without receiving any influence from the characteristic of the transmission line between the LSI 100 and a tester.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device,
Furthermore, high-speed logic LSI (large-scale semiconductor integrated circuit device)
The present invention relates to a technology effective when applied to, for example, a technology effectively applied to a clock distribution LSI.

[0002]

2. Description of the Related Art In a logic system, in order to match the operation timing in the system, a plurality of timing signals (clock signals) in phase with each other are generated and distributed to each part in the system. In this case, the phase variation between the plurality of timing signals needs to be made as small as possible, and in particular, the higher the timing signal becomes, the stricter the condition for allowing the phase variation becomes.

Therefore, for example, an LS for clock distribution
For an LSI that generates a plurality of timing signals and outputs them to the outside, such as I, it is necessary to diagnose whether the phase variation between the timing signals is within a predetermined allowable range.

In the conventional LSI, the diagnosis of the phase variation is performed by a tester 200 connected to an external terminal of the LSI 100, as shown in FIG.
February 9, 7 issue No. 414 "265-268: See LSI Tester).

[0005]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, the timing signal becomes faster,
When the permissible range of the phase variation reaches several tens ps, for example, in the tester connected to the external terminal of the LSI, the influence of the transmission path characteristic between the LSI and the tester becomes large, and the phase variation becomes large. Will not be able to be inspected accurately. In other words, when the speed of the timing signal is increased, the inspection of the phase variation exceeds the measurement limit of the tester, which hinders the stabilization and efficiency of the inspection process, and further the stabilization of the LSI performance and the high speed. It became clear that this would cause a problem that it would also become a hindrance factor that hinders the realization.

An object of the present invention is to provide an LSI that handles a plurality of timing signals, such as an LSI for clock distribution, so that the phase variation of the timing signals can be inspected with high accuracy and efficiency even under a high speed condition. To provide the technology to do.

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, whether or not the maximum phase difference between the plurality of timing signals exceeds a predetermined permissible range is detected in the LSI for generating and processing a plurality of timing signals whose phases are aligned with each other, and then the LSI is output to the outside of the LSI. The phase shift detection circuit for outputting is built in.

[0011]

According to the above-mentioned means, the phase variation of a plurality of timing signals generated and processed in the LSI can be eliminated by the LSI.
Without being affected by the characteristics of the transmission line between the tester and the tester,
It is possible to perform inspection with high accuracy and high efficiency in the LSI.

Thus, for example, the clock distribution LS
In the LSI that handles a plurality of timing signals, such as I, it is possible to achieve an object of enabling the phase variation of the timing signals to be inspected with high accuracy and efficiency even under a high speed condition.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

FIG. 1 shows an embodiment of a high speed logic LSI to which the technique of the present invention is applied. The LSI 100 shown in FIG.
Clock distribution LS that generates and outputs a plurality of timing signals (clock signals) A1 to An whose phases are aligned with each other.
In the LSI 100, it is detected in the LSI 100, together with the signal processing circuit 101 that generates the timing signals A1 to An, whether the maximum phase difference between the plurality of timing signals A1 to An exceeds a predetermined allowable range. Then, the phase shift detection circuit 1 for outputting to the outside of the LSI 100 is integrally formed together.

FIG. 2 shows a specific embodiment of the phase shift detection circuit 1 and FIG. 3 shows its operation waveform chart. The phase shift detection circuit 1 shown in FIG. 2 is a logic circuit 1 that detects a logic mismatch section w between a plurality of timing signals A1 to An.
1 and an integrating circuit 1 for integrating the output D of the logic circuit 11
2 and a level detection circuit 1 for detecting whether the output level Vw of the integration circuit 12 exceeds a predetermined threshold value Vth.
3 and 3.

In this case, the logic circuit 11 for detecting the logic non-coincidence section w takes the negative logical product of the above timing signals A1 to An and the first logic gate G1 which takes the total logical sum of the plurality of timing signals A1 to An. A second logic gate G2,
It is composed of a third logic gate G3 which takes a logical product between the output B of the first logic gate G1 and the output C of the second logic gate G2, and the output D of the third logic gate G3 is in the logic mismatch section w. It is transmitted to the integration circuit 12 as a detection output.

At this time, as shown in FIG. 3, the logical mismatch section w indicated by H (high level) of the detection output D is
The maximum phase difference between the timing signals A1 to An is the so-called phase variation amount.

The integrating circuit 12 has a resistor R as a time constant element.
t and the capacitance element Ct, the capacitance element Ct is charged to the high-side power supply potential Vcc when the output D of the logic circuit 11 is H (high level), while the logic circuit 11 is
When the output D from is at L (low level), the capacitance element C
t is discharged to the low-side power supply potential Vee.

As a result, as shown in FIG. 3, when the logic disagreement section w in which the output D from the logic circuit 11 becomes H (high level) is short, that is, the timing signals A1 to A1.
When the maximum phase difference between An is small, the discharge of the capacitive element Ct becomes more dominant than the charge, and the output level Vw of the integrating circuit 12 decreases. On the other hand, when the logic disagreement section w in which the output D from the logic circuit 11 becomes H (high level) becomes long, that is, when the maximum phase difference between the timing signals A1 to An becomes large, the charging of the capacitive element Ct is more than the charging. Also becomes dominant, and the output level Vw of the integrating circuit 12 rises.

The level detection circuit 13 includes emitter-coupled differential bipolar transistors Q31 and Q32 and resistors R33 and R34 for dividing a predetermined detection threshold Vth.
And a bipolar transistor Q32 forming an emitter follower output circuit Q33.
As shown in FIG. 5, it is detected whether the output level Vw of the integrating circuit 12 becomes equal to or higher than a predetermined detection threshold value Vth, and the detection result is used as a diagnostic output for phase variation LS.
I Output to outside.

As described above, in the above-described clock distribution LSI 100, it is determined whether or not the maximum phase difference between the plurality of timing signals A1 to An internally generated, that is, the non-coincidence section w exceeds the predetermined allowable range. The detection is performed inside the LSI 100, and the detection result is output to the outside as a phase variation diagnostic output.

As a result, the phase variation among the plurality of timing signals A1 to An generated and processed in the LSI 100 does not depend on the external tester, and the LSI 1 does not depend on the external tester.
It is inspected in 00 with high accuracy and high efficiency. Therefore, the phase variation defect can be accurately diagnosed without being affected by the characteristics of the transmission line between the LSI and the tester.

FIG. 4 shows another embodiment of the phase shift detection circuit 1, and FIG. 5 shows its operation waveform chart. The phase shift detection circuit 1 shown in FIG. 4 has a plurality of timing signals A1 to A1.
A logic circuit 11 for detecting a logic mismatch section w between An;
A delay circuit 14 for delaying and transmitting the output D of this logic circuit;
A logic gate G4 which takes a logical product between the output E of the delay circuit 14 and the output D of the logic circuit, and the logic gate G4.
4 and the holding circuit 15 which is set by the output F of 4.

As shown in FIG. 5, the logic mismatch section w detected by the logic circuit 11 is the delay amount t of the delay circuit 14.
When it becomes larger than d, the output F of the logic gate G4 becomes H
(High level) comes to appear, and this H (high level)
The holding circuit 15 is set by the holding circuit 15
The set output Q of the LSI is used as a diagnostic output of phase variation.
Output to the outside.

In this case, the delay amount td of the delay circuit 14 is
It is set to a size corresponding to the above logical non-matching section w, that is, the allowable range of the maximum phase difference. When the logic non-coincidence section w is smaller than the delay amount td, the output E of the delay circuit 14 and the output D of the logic circuit 11 do not temporally overlap with each other, and therefore the output F of the logic gate G4 does not become H (high level).

However, when the logic non-coincidence section w becomes larger than the delay amount td, the output E of the delay circuit 14 and the output D of the logic circuit 11 temporally overlap with each other, as shown in FIG. Output F of logic gate G4 in the interval
Becomes H (high level), and the holding circuit 15 is set by this H (high level). The holding circuit 15 is assumed to be initialized to a reset state when the power is turned on (power-on reset).

As described above, it is detected inside the LSI 100 whether or not the maximum phase difference between the plurality of timing signals A1 to An generated inside the LSI 100, that is, the logic non-matching section w exceeds a predetermined allowable range. The detection result is output to the outside as a phase variation diagnostic output.

As a result, the phase variation among the plurality of timing signals A1 to An generated and processed in the LSI 100 does not depend on the external tester, and the LSI 1 does not depend on the external tester.
It is inspected in 00 with high accuracy and high efficiency.

Further, in this embodiment, the diagnostic output of the phase variation is set to H by the set output Q of the holding circuit 15.
Since it is given at a binary level of (high level) or L (low level), there is also an advantage that the determination of the phase variation defect can be performed very easily and clearly.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, by using the wired logic for the logic gates G1 to G4, the detection speed of the logic disagreement section w can be increased, thereby further improving the detection accuracy of the phase variation.

In the above description, the case where the invention made by the present inventor is mainly applied to the clock distribution LSI which is the background field of application has been described.
The present invention is not limited to this, and can be applied to, for example, a functional logic LSI that performs parallel processing of logic signals.

[0033]

The effects of the typical ones of the inventions disclosed in this application will be briefly described as follows.

That is, in an LSI that handles a plurality of timing signals, such as a clock distribution LSI, the phase variation of the timing signals can be inspected with high accuracy and efficiency even under high speed conditions. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the technique of the present invention is applied.

FIG. 2 is a diagram showing a specific circuit example of the phase shift detection circuit shown in FIG.

FIG. 3 is a waveform chart showing the operation of the phase shift detection circuit shown in FIG.

FIG. 4 is a diagram showing a specific circuit example of the phase shift detection circuit shown in FIG.

5 is a waveform chart showing the operation of the phase shift detection circuit shown in FIG.

FIG. 6 is a block diagram showing a conventional phase variation inspection method in a semiconductor integrated circuit device.

[Explanation of symbols]

 100 semiconductor integrated circuit device 101 signal processing circuit 1 phase shift detection circuit 11 logic circuit 12 integration circuit 13 level detection circuit 14 delay circuit 15 holding circuit

Claims (3)

[Claims] 1. A signal processing circuit for generating a plurality of timing signals in phase with each other and outputting the timing signals to the outside, and detecting whether or not the maximum phase difference between the plurality of timing signals exceeds a predetermined allowable range. And a phase shift detection circuit for outputting the semiconductor integrated circuit to the outside of the semiconductor integrated circuit. 2. A phase shift detection circuit, a logic circuit for detecting a logic mismatch section between a plurality of timing signals, an integration circuit for integrating the output of the logic circuit, and an output level of the integration circuit having a predetermined threshold. A semiconductor integrated circuit device, comprising: a level detection circuit for detecting whether or not a value is exceeded. 3. A phase shift detection circuit, a logic circuit for detecting a logic mismatch section between a plurality of timing signals, a delay circuit for delaying and transmitting the output of the logic circuit, an output of the delay circuit and the logic circuit. A semiconductor integrated circuit device, comprising: a holding circuit set by a logical product between the output and the output.