JPH0813140B2 - Motion compensation predictive coding device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation predictive coding device used for coding image signals in television, video conference, and the like.

2. Description of the Related Art Recently, a motion compensation predictive coding apparatus has been actively used in the field of high-efficiency coding of moving images, etc., and its practical use has been reported in part.

The principle of this motion compensation predictive coding utilizes the correlation between frames (or between fields) of a moving image, obtains the motion of the image between the current frame and the previous frame, and based on this motion, the image of the current frame is calculated. The prediction error is calculated between this and the current frame, and the prediction error information and the motion information are encoded.

Here, a method called a block matching method is well known as a method for obtaining a motion (called a motion vector) of an image between frames (for example, “motion correction in interframe coding”, Yuichi Ninomiya, Electronic). Technical Report of IEICE IE78-6).

This method will be described below with reference to FIG.

In this method, the motion of the image between the current frame 136 and the previous frame 137 is obtained in rectangular block units. As shown in FIG. 10, for each detection block 138 obtained by dividing the current frame 136 into a plurality of detection blocks. The best matching portion is found from the reference block 140 included in the reference area 139 of the previous frame 137, and the amount of motion during this time is calculated as the motion vector 141.
It is what you ask for.

At this time, the degree of block matching is determined by the magnitude of a predetermined evaluation function value (various things such as sum of absolute values of pixel differences between blocks have been devised), and motion vector detection is included in the reference area. This is done by finding the one that gives the minimum value of the evaluation function from a large number of reference blocks.

Problems to be Solved by the Invention However, in the configuration based on the above method, a large amount of calculation such as subtraction / comparison is performed by using a pixel value represented by multiple values (for example, 8 bits) in the calculation of the evaluation function value. Since the number of reference blocks that can be evaluated in real-time processing will be limited, the reference block that gives the correct motion vector may not be evaluated, resulting in low detection accuracy of the motion vector and representing prediction error information. There is a problem that the code amount increases.

In order to solve this problem, conventionally, an evaluation feeling value calculation for a plurality of reference blocks was performed in parallel, but the problem was that in this case, the device scale increased. Was there.

In view of the above conventional problems, it is an object of the present invention to provide a motion compensation predictive coding device capable of detecting a motion vector with high accuracy without increasing the device scale. .

Means for Solving the Problems In order to solve the above problems, the present invention provides a distribution measuring unit that measures a pixel value distribution of a current frame or field image signal by dividing it into pixel regions, a current frame or field image signal, and First and second binary values that divide the domain of the previous frame or field image signal into a plurality of sections based on the pixel value distribution and binarize each section into a value of 0 or 1 different from the adjacent section The conversion means and the binary calculation means for obtaining the evaluation function value for detecting the motion vector converted into the binarized image signal are provided.

With the above-described structure, the present invention is a binary image in which the first and second binarizing means divide the image signal into intervals based on the local pixel value distribution and binarize the image signal to reflect the characteristics of the original image. On the other hand, the calculation amount is reduced by obtaining an evaluation function value for motion vector detection based on the binary image by the binary calculation means, and a large number of reference blocks can be evaluated in a short time. This is so that the motion vector can be accurately detected without increasing the device scale.

Practical Example The concept of binarization of an image signal in the present invention will be described below with reference to FIG.

In FIG. 9A, the horizontal axis represents the pixel position and the vertical axis represents the pixel value. The range of pixel values is divided into n + 1 sections by _n thresholds t _{1 to} t _n (n = 5 in the figure), and a binary value of 0 or 1 so that the values are different in adjacent sections. A pixelized pixel value is assigned. Each pixel is binarized according to which section the pixel value belongs to. From the above, the image is
It is binarized as shown in FIG.

At this time, the threshold values t _{1 to} t _n are adaptively arranged based on the local distribution of pixel values in a pixel value section in which the distribution is concentrated.

This binarization method is an effect of using a plurality of threshold values when the pixel value distribution is spread over a wide range.
Conversely, when the distribution is concentrated near a certain value, the effect of adaptively changing the threshold interval based on the distribution,
Since the local change of the image can be represented, the binarized image reflects the characteristics of the original image even in a small area such as a block for motion vector detection. Therefore, if the patterns match in the binary image obtained by this method, it is highly possible that the original images also match.

On the other hand, in the present invention, since the binary image signal is used for calculating the evaluation function value, the amount of calculation for obtaining the evaluation function value for one reference block can be small, for example, the evaluation function is a block of binarized pixel values. If it is defined by the number of disagreements between values, the evaluation function value is calculated by calculating 64 times the exclusive OR with the block size of 8 pixels x 8 lines and counting the number of times the true / false value becomes "true". Can be asked.

Therefore, according to the present invention, a larger number of reference blocks can be evaluated as compared with the case of the conventional technique, so that a reference block that gives a correct motion vector is less likely to be evaluated and the motion vector detection accuracy is improved. In addition, the device scale when the evaluation function value is calculated in parallel is also
It is considerably smaller than that of the prior art.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the present invention, a configuration in which a plurality of reference blocks are evaluated in parallel and a configuration in which each block is evaluated one block at a time are conceivable, but the latter case will be described here.

FIG. 1 is a block diagram showing the configuration of a motion compensation predictive coding apparatus according to an embodiment of the present invention.

In FIG. 1, 1 is an input terminal to which a digital input image signal is supplied, 3 is a motion vector binary detection unit for calculating a motion vector, and 4 is a sequential supply of previous frame decoded image signals to the motion vector binary detection unit 3. The frame memory 8 is a prediction unit that performs motion compensation prediction to generate a prediction signal of the current frame. Reference numeral 10 is a prediction error signal generation unit that obtains a prediction error, and includes a delay circuit 11 and a subtractor 13. 15 24
Is an encoder that performs variable length coding, for example. A decoding unit 17 obtains a decoded image signal from the outputs of the prediction unit 8 and the encoder 15, and includes a decoder 18, a delay circuit 20, and an adder 22. 26 is a multiplexer, 28 is a transmission buffer memory, and 30 is a transmission line.

The operation of the above configuration will be described below.

First, the input image signal of the current frame which is A / D (analog / digital) converted is supplied from the input terminal 1,
It is sent to the motion vector binary detector 3 and the prediction error signal generator 10 via the signal line 2. The motion vector binary detector 3 obtains a motion vector based on the current frame input image signal and the previous frame decoded image signal supplied from the frame memory 4 via the signal line 5, and outputs the motion vector via the signal line 6 as a motion vector signal. It is supplied to the prediction unit 8 and the encoder 24. The prediction unit 8 that has been supplied with the motion vector signal performs motion compensation prediction based on this motion vector signal and the previous frame decoded image signal supplied from the frame memory 4 via the signal line 7, and outputs the prediction signal of the current frame. It is generated and supplied to the prediction error signal generation unit 10 and the decoding unit 17 via the signal line 9 in the same scanning sequence as the input image signal. Prediction error signal generator
In 10, the error between the input image signal supplied via the delay circuit 11 and the prediction signal supplied from the prediction unit 8 is obtained by the subtracter 13 and is used as a prediction error signal via the signal line 14 to the encoder.
Output to 15. The delay circuit 11 is used to match the timing of inputting the two signals to the subtractor 13. Next, in the encoders 15 and 24, the prediction error signal and the motion vector signal are subjected to variable length coding, for example, and sent to the multiplexer 26 as the prediction error code and the motion vector code. The prediction error code is also sent to the decoding unit 17. Then, the multiplexer 26 multiplexes the prediction error code which is the output of the encoder 15 and the motion vector code which is the output of the encoder 24, and supplies it as a picture information code to the transmission buffer memory 28 via the signal line 27. The transmission buffer memory 28 is used to match the transmission speed of the image information code with the transmission speed of the transmission line 30.

In the decoding unit 17, the prediction error code is decoded by the decoder 18, the sum of the prediction error code and the prediction signal is obtained by the adder 22, and the decoded image signal is sent to the frame memory 4 via the signal line 23. This decoded image signal is used by the motion vector binary detector 3 and the predictor 8. The delay circuit 20 includes an adder 22
It is used to match the timing of the input of the two signals to the.

FIG. 2 is a block diagram showing a configuration of a decoding device corresponding to the motion compensation predictive coding device in the embodiment of the present invention.

In FIG. 2, 30 is a transmission line, 32 is a reception buffer memory, 34 is a demultiplexer for separating the output of the reception buffer memory 32 into a motion vector code and a prediction error code, and 36 and 43 are the motion vector code and the prediction error code. , 38 is a decoder for decoding each of the above, 38 generates a prediction signal from the previous frame decoded image signal supplied from the frame memory 39 and the output of the decoder 36, 45 is an adder, and 47 is an output terminal.

 The operation of the above configuration will be described below.

First, the image information code sent via the transmission line 30 is once stored in the reception buffer memory 32, then read out in accordance with the decoding processing speed, and then demultiplexed via the signal line 33.
Sent to 34. The demultiplexer 34 separates this into a motion vector code and a prediction error code, and sends the former to the decoder 36 through the signal line 35 and the latter to the decoder 43 through the signal line 42. The decoders 36 and 43 decode these signals, and use the signal line 37 and the signal line as motion vector signals and prediction error signals, respectively.
Send to 44. The motion vector signal is supplied to the prediction unit 38 via the signal line 37, and the prediction unit 38 and the frame memory 39
A prediction signal is generated based on the previous frame decoded image signal supplied through the signal line 40. This prediction signal is supplied to the adder 45 via the signal line 41, and on the other hand, addition is performed with the prediction error signal stored in the chest cavity via the signal line 44 to obtain a decoded image signal. The decoded image signal is output from the output terminal 47 and stored in the frame memory 39 for use in the prediction unit 38.

Next, a more detailed structure of the block structure of FIG. 1 in one embodiment of the present invention will be described with reference to FIGS.

FIG. 3 is a block diagram showing a detailed configuration of the motion vector binary detector 3 shown in FIG. This figure shows a configuration in which the distribution measurement of the input image signal is performed in block line units, and the reference area for motion vector detection covers a total of 3 block lines including 1 block line above and below with reference to the same position as the detection block. ing. Here, the "block line" refers to the number of continuous scanning lines equal to the size of the detection block in the vertical direction.

In FIG. 3, reference numeral 48 is a distribution measuring unit for measuring the pixel value distribution of each block line of the current frame input image signal,
Reference numeral 50 is a threshold value determining unit that determines a threshold value for binarization based on the output of the distribution measuring unit 48, 52 is a delay circuit that delays the input image signal of the current frame by about one block line time, 54 and 63 , 67, 69 are binarization circuits that binarize based on the output of the threshold value determining unit 50. 56 is a detection block configuration unit that divides the input image signal of the current frame into blocks.
57 and an address mapping unit 58. 61,
Reference numeral 65 denotes a delay circuit which delays the decoded image signal of the previous frame by about 2 block line times and about 1 block line time. Reference numeral 71 is a reference block configuration unit that divides the decoded image signal of the previous frame into blocks, and includes a memory 72 and an address mapping unit 73. Reference numeral 76 is a binary operation unit that obtains an evaluation function value from each output of the detection and reference block configuration units 56 and 71, 78 is a comparison detector that calculates a motion vector based on the output of the binary operation unit 76, and 79 is a control circuit. Is.

 The operation of the above configuration will be described below.

The signals supplied to the motion vector binary detector 3 are the current frame input image signal and the previous frame decoded image signal, which are supplied via the signal lines 2 and 5, respectively. The current frame input image signal supplied via the signal line 2 is sent to the distribution measuring unit 48, and the appearance frequency of each pixel value is obtained for each block line. The appearance frequency value obtained here is sent to the threshold value determining unit 50 via the signal line 49, and is used to determine the threshold value for binarization. In the threshold value determining unit 50, the signal line 49
Based on the appearance frequency value of each pixel value supplied via, for example, the average value a of the distribution and the difference average b of the pixel value and the average value are obtained, and a ± b, a ± 0.5b, a, etc. are obtained. The signal is sent from the signal line 51 to the binarization circuits 54, 63, 67 and 69 as a threshold value for dividing the interval. In the binarization circuit 54, a plurality of threshold values supplied from the signal line 51 and a delay circuit
The current block input image signal delayed by one block line time is compared by 52, and the current frame input image signal is binarized based on the result, and the detection block configuration unit 56
Send to. On the other hand, in the binarization circuits 63, 67, and 69, similarly, the delay circuit 61 delays the previous frame decoded image signal by about two block lie times, and the delay circuit 65 delays about 1
Previous frame decoded image signal delayed by block line time,
The preceding frame decoded image signal directly supplied from the signal line 5 is binarized and sent to the reference block configuration unit 71 as a binary image signal of 3 block lines covering the reference area.

Next, in the detection block configuration unit 56, the binary image signal supplied via the signal line 55 is temporarily stored in the memory 57. Assuming that the size of the detection block in the vertical direction is 8 pixels and the input image signal is line-sequential scanning, the memory 57 needs a capacity of at least 8 scanning lines (1 bit / pixel). Memory 57
The binary data is read from the address mapping section 58 by the memory address signal sent via the signal line 59, and sent out in block units via the signal line 60. The signal line 60 in this case consists of eight signal lines, each of which is used to send data for one scanning line of the detection block. That is, the data of each scanning line of the detection block is sent in parallel. The address mapping unit 58 is configured by using, for example, a memory table, and outputs the memory address signal based on the detection block number and the in-block relative address signal sent from the control circuit 79 via the signal lines 81 and 82. is there. On the other hand, also in the reference block configuration unit 71, the binary data of the reference block is similarly sent out from the signal line 75. However, unlike the detection block configuration unit, in the address mapping unit 73, the memory address signal is generated also by using the shift control signal supplied from the control circuit 79 via the signal line 80. In addition, the timing of data transmission and the memory size are also different (the memory size is at least 24 scanning lines (1 bit / bit since the vertical size of the reference area is 3 block lines).
Pixel) is required). The binary data of the detection block and the reference block thus obtained are sent to the binary operation unit 76, the evaluation function value indicating the degree of match / mismatch of the block is obtained, and the comparison detection unit 78 is sent via the signal line 77. Is supplied to. In the comparison / detection unit 78, the optimum one of the shift control signals sent from the control circuit 79 via the signal line 80 is determined based on the evaluation function value, and sent out from the signal line 6 as a motion vector signal.

FIG. 4 is a block diagram showing a more detailed structure of the binarization circuits 54, 63, 67, 69 in the motion vector binary detection section of FIG. The figure shows a case where the domain of the image signal is divided into 6 sections by 5 threshold values and binarized.

In FIG. 4, 85 _{1 to} 85 ₅ are registers for holding a threshold value, 87 _{1 to} 87 ₅ are comparators for comparing the current frame input image signal or the previous frame decoded image signal with the threshold value, and 89 ₁ 89 ₂ aND circuit, 90 an inverter, 93 is an OR circuit.

In the above configuration, the operation of the binarization circuit will be described below.
The case of 54 will be described as an example.

The threshold t ₁ ~t ₅ via a signal line 51 ₁ to 51 ₅ is supplied to the register _{85 1 ~85 5 (t 1 <} t 2 <... t 5) register 85 _{1-85 5}
Then this is retained. This threshold value t _{1 to} t ₅ and the signal line 53
The magnitude relationship with the image signal supplied from the comparators 87 _{1 to} 87 ₅
And the value 1 is output to the signal lines 88 _{1 to} 88 ₅ when the image signal is less than or equal to the threshold value, and otherwise the value 0 is output. The output values are combined by the logical operation in the logical product circuits 89 _{1 to} 89 ₂ , the inverter 90, and the logical sum circuit 93, and the result is directly output from the signal line 55 as a binarized pixel value. In the binarized pixel value at this time, the original pixel value l is t ₁ <lt ₂ , t ₃ <l
It is 1 when either t ₄ or t ₅ <l is satisfied, and 0 otherwise.

FIG. 5 is a block diagram showing a more detailed configuration of the binary operation unit 76 in the motion vector binary detection unit of FIG. The figure shows the case where the detection block size is 4 × 4 pixels.

In FIG. 5, reference numerals 94 _{1 to} 94 ₄ denote binary line matching units, which are shift registers 95 and 96 and an exclusive OR circuit, respectively.
It is composed of 99 _{1 to} 99 ₄ and a bit addition circuit 101. 103
Is a multiplexer that sequentially switches and outputs the outputs of the binary line matching units 94 _{1 to} 94 ₅ , 105 is an adder, and 107 and 110 are registers.

 The operation of the above configuration will be described below.

The data of the detection block and the reference block supplied via the signal lines 60 and 75 are sent to the binary line matching units 94 _{1 to} 94 ₄ in scanning line units. Each binary line matching unit 94 ₁
In ~ 94 _{4 the} binary data for each pixel is taken out using the shift registers 95, 96, and the pixels at the same position in the block are evaluated for match / mismatch by the exclusive OR circuits 99 ₁ ~ 99 _4. The value 1 is supplied to the bit addition circuit 101 when they do not match, and the value 0 is supplied to them when they match. The bit addition circuit 101 obtains the sum of these, which indicates the number of mismatched pixels for each scanning line. This sum is output from the binary block matching units 94 _{1 to} 94 ₄ via the signal lines 102 _{1 to} 102 ₄ and the multiplexer 10
Supplied to 3. The multiplexer 103 sequentially selects the input signal line by the selection control signal sent from the signal line 83 _1, and supplies the input value to the adder 105 via the signal line 104. The adder 105 and the register 107 determine the sum of the input values, and determine the number of mismatched pixels between blocks as the evaluation function value. Register 110 is for output control,
The evaluation function value is output from the signal line 77. The signal line 83
₂ is for supplying clear input to register 107,
Signal line 83 ₃ is for supplying an output control signal to the register 110.

FIG. 6 is a block diagram showing a more detailed configuration of the comparison detection unit 78 in the motion vector binary detection unit of FIG.

In FIG. 6, 111 is the binary operation unit 76 shown in FIG.
Comparator that compares the output of the
3, 117 are multiplexers, and 115, 119, 122 are registers.

 The operation of the above configuration will be described below.

The register 115 holds the minimum value of the evaluation function at each time point, while the register 119 holds the corresponding shift amount. The comparator 111 compares the evaluation function value supplied via the signal line 77 with the contents of the register 115 and outputs the result to the signal line 1
It is sent as a selection control signal to the multiplexers 113 and 117 via 12. When the comparison result indicates that the input from the signal line 77 is small, the multiplexers 113 and 117 update the contents of the registers 115 and 119 through the input evaluation function value from the signal line 77 and the input shift amount from the signal line 80. Finally register 119
The shift amount obtained in is the motion vector. Register 122
Is for output control. The signal line 84 ₁ is for a preset input to the register 115, and the signal line 84 ₂ is for an output control input to the register 122. The register 115 is preset to the maximum value that the evaluation function can take each time the motion vector detection of each detection block is started.

FIG. 7 is a block diagram showing a more detailed structure of the prediction unit 8 shown in FIG.

In FIG. 7, reference numeral 123 is a prediction block configuration unit that makes the output of the frame memory 4 shown in FIG. 1 in block units, and includes a memory 124 and an address mapping unit 125. Reference numeral 128 is a scan conversion buffer memory for converting an operation sequence.

In the above configuration, the operation in the prediction block construction unit 123 is almost the same as the operation described in the reference block construction unit 71 in FIG.
It is output from 127. This is the difference conversion buffer memory 128
, And is output from the signal line 9 in which the scanning sequence is converted.

The above is the detailed configuration and operation of the motion compensation predictive coding apparatus according to the embodiment of the present invention.

As described above, according to the present embodiment, the current frame input image signal and the previous frame image signal are binarized to obtain the evaluation function value, and the motion vector is obtained. Can be made smaller. Further, since the calculation time of the evaluation function value per time is short, a large number of reference blocks can be evaluated, and the binary image binarized based on the pixel value distribution of each block line is the original image. Since the local feature of can be reflected, the accuracy of the motion vector can be improved as a result. Therefore, since the generation of prediction error information can be suppressed, it is possible to reduce the amount of code relating to the prediction error to be transmitted.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 is a block diagram showing a motion vector binary detector of the motion compensation predictive coding apparatus according to the second embodiment of the present invention.

8 is different from FIG. 3 in that instead of the reference block configuration unit 71 of FIG. 3, a reference block line configuration unit 129 including a memory 72 and an address mapping unit 130, and a control circuit 133 based on the reference block line configuration unit 129. That is the point. Here, the “reference block line” refers to a part included in the reference area in the block line.

In the above configuration, the address mapping unit 130 is based on the shift control signal sent from the signal line 80, the detection block number sent from the signal line 81, and the reference block line relative address signal sent from the signal line 134. A memory 72 is generated via the signal line 131 by generating a memory address signal.
Supply to. A binary image signal is sent from the memory 72 through the signal line 132 in block line units. Binary calculator 76
Then, every time one bit is shifted by the shift register 96 in FIG. 5, binary data of the reference block is taken out. On the other hand, in the case of the first embodiment, in order to fetch the data of the reference block, it is necessary to shift the block by the horizontal size. The other operations are the same as those in the first embodiment.

As described above, according to the present embodiment, when all the reference blocks in the reference area are evaluated, the data of the reference blocks can be easily fetched, so that the calculation time per evaluation can be shortened. .

In the above two embodiments, the case where the motion vectors are detected between the frames by using the frame memories 4 and 39 has been described, but the motion vector may be detected between the fields by using the field memory.

As described above, according to the present invention, when detecting a motion vector,
The current frame image signal and the previous frame image signal are binarized by reflecting the characteristics of local changes in the original image,
By using this to evaluate a large number of reference blocks, it is possible to detect a motion vector with high accuracy without increasing the device scale, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a motion compensation predictive coding device according to an embodiment of the present invention, FIG. 2 is a block connection diagram of a decoding device corresponding to the same device, and FIGS. Partial block connection diagram, FIG. 9 is a conceptual diagram for explaining the basic binarization of the present invention, and FIG. 10 is a conceptual diagram for explaining the principle of conventional motion vector detection. 3 ... Motion vector binary detector, 4 ... Frame memory,
8 ... Prediction unit, 10 ... Prediction error signal generation unit, 15, 24 ...
Encoder, 48 ... Distribution measuring unit, 50 ... Threshold value determining unit,
54, 63, 67, 69 ... Binarization circuit, 56 ... Detection block configuration unit, 71 ... Reference block configuration unit, 76 ... Binary operation unit,
78 …… Comparison detection unit, 129 …… Reference block line configuration unit.

Claims (1)

[Claims] 1. A distribution measuring means for measuring a pixel value distribution of a current frame or field image signal by dividing it into pixel areas, and the current frame or field image signal based on the pixel value distribution obtained by the distribution measuring means. First binarizing means for binarizing, and detection block configuring means for constituting a detection block obtained by dividing the frame or field surface converted into the binary image signal by the first binarizing means into a plurality of parts. Second, binarizing the previous frame or field image signal based on the pixel value distribution obtained by the distribution measuring means
And a reference block at a position two-dimensionally shifted with reference to the same position as the detection clock on the frame or field surface converted into the binary image signal by the second binarizing device. Reference block constructing means, binary computing means for obtaining an evaluation function value based on the two binary image signal blocks obtained by the detecting block constructing means and the reference block constructing means, and the evaluation obtained by the binary computing means. Motion vector calculation means for obtaining a motion vector based on a function value, wherein the first and second binarization means are:
Based on the pixel value distribution obtained by the distribution measuring means, the domain of the image signal value is divided into a plurality of areas, and the value of 0 or 1 is set so that the value of each area is different from that of the adjacent area. A motion compensation predictive coding device for outputting as a signal.