JPH07121122B2 - Motion compensation predictive coding device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation predictive coding device used for coding image signals in television, video conference, and the like.

2. Description of the Related Art Recently, a motion compensation predictive coding device has been actively used in the field of high efficiency coding of moving images,
Practical application has also been reported in some areas.

The principle of this motion compensation predictive coding utilizes the correlation between frames (or between fields) of a moving image, obtains the motion of the image between the current frame and the previous frame, and based on this motion, the image of the current frame is calculated. The prediction error is calculated between this and the current frame, and the prediction error information and the motion information are encoded.

Here, a method called a block matching method is well known as a method for obtaining a motion (called a motion vector) of an image between frames (for example, "motion correction in interframe coding" Yuichi Ninomiya, Electronic Communication IEICE Technical Report IE-78-6).

This method will be described below with reference to FIG.

This method obtains the motion of the image between the current frame 122 and the previous frame 123 in rectangular block units. As shown in FIG. 10, for each detection block 124 obtained by dividing the current frame 122 into a plurality of detection blocks. The best matching portion is the reference block included in the reference area 125 of the previous frame 123.
It is found from 126 and the amount of motion during this is obtained as a motion vector 127.

At this time, the degree of block matching is determined by the magnitude of a predetermined evaluation function value (various things such as sum of absolute values of pixel differences between blocks have been devised), and motion vector detection is included in the reference area. This is done by finding the one that gives the minimum value of the evaluation function from a large number of reference blocks.

Problems to be Solved by the Invention However, in the configuration based on the above method, a large amount of calculation such as subtraction / comparison is performed by using a pixel value represented by multiple values (for example, 8 bits) in the calculation of the evaluation function value. Since it will be done, the number of reference blocks that can be evaluated in real-time processing will be limited,
In some cases, a reference block that gives a correct motion vector is not evaluated, resulting in a low motion vector detection accuracy and a large amount of code representing prediction error information.

In order to solve this problem, conventionally, the evaluation function values for a plurality of reference blocks are calculated in parallel, but the problem has been solved in this case. Was there.

In view of the above conventional problems, it is an object of the present invention to provide a motion compensation predictive coding device capable of detecting a motion vector with high accuracy without increasing the device scale. .

Means for Solving the Problems In order to achieve the above object, the present invention has a first binarizing means for binarizing a current frame or field image signal, and a binarizing means obtained by the first binarizing means. Detection block forming means for forming a detection block in which a frame or field surface is divided into a plurality of portions based on the value image signal, and second binarizing means for binarizing the previous frame or field image signal,
Reference block forming means for forming a reference block at a position shifted by at least one pixel with reference to the same position as the detection block on the frame or field plane based on the binary image signal obtained by the second binarizing means. A binary operation means for obtaining an evaluation function value based on the two binary image signal blocks obtained by the detection block configuration means and the reference block configuration means; and an evaluation function value obtained by the binary operation means And a motion vector calculating means for calculating a motion vector.

Effect of the Invention The present invention has the above-described configuration, and a value of 0/1 set so that the value is set to be different from that of the adjacent section for each section obtained by dividing the domain of the image signal into a plurality of sections by the first and second binarizing means. Is output as a binary image signal, and the evaluation function value for detecting the motion vector is obtained based on the binarized image signal by the binary operation means, so that the device scale is accurately increased without increasing the device scale. Vectors can be detected.

Practical Example The concept of binarization of an image signal in the present invention will be described below with reference to FIG.

In FIG. 9A, the horizontal axis represents the pixel position and the vertical axis represents the pixel value. The range of pixel values is divided into n + 1 sections by n threshold values t _{1 to} t _n (n = 5 in the figure),
Binary pixel values of 0 or 1 are assigned so that the values are different in the adjacent sections. Each pixel is binarized according to which section the pixel value belongs to. As a result, the image is binarized as shown in FIG. 9 (b).

Since this binarization method can represent a local change in an image without being affected by the bias in the distribution of pixel values,
The binarized image reflects the characteristics of the original image even in a small area such as a motion vector detection block. Therefore, if the patterns match in the binary image obtained by this method, it is highly possible that the original images also match.

On the other hand, in the present invention, since the binary image signal is used for calculating the evaluation function value, the amount of calculation for obtaining the evaluation function value for one reference block can be small. For example, if the evaluation function is defined by the number of disagreement between blocks of binarized pixel values, 64 times of exclusive OR calculation and its true / false value are “true” when the block size is 8 pixels × 8 lines. The evaluation function value can be obtained by counting the number of "."

Therefore, according to the present invention, a larger number of reference blocks can be evaluated as compared with the case of the conventional technique, so that a reference block that gives a correct motion vector is less likely to be evaluated and the motion vector detection accuracy is improved. In addition, the scale of the apparatus when the evaluation function value is calculated in parallel can be considerably smaller than that of the conventional technology.

An embodiment of the present invention will be described below with reference to the drawings. In the present invention, a configuration in which a plurality of reference blocks are evaluated in parallel and a configuration in which each block is evaluated one block at a time are conceivable, but the latter case will be described here.

FIG. 1 is a block diagram showing the configuration of a motion compensation predictive coding apparatus according to an embodiment of the present invention.

In FIG. 1, 1 is an input terminal to which a digital input image signal is supplied, 3 is a motion vector binary detection unit for calculating a motion vector, and 4 is a preceding frame decoded image signal sequentially supplied to the motion vector binary detection unit 3. A frame memory 8 to be supplied is a prediction unit that performs motion compensation prediction to generate a prediction signal of the current frame. Reference numeral 10 is a prediction error signal generation unit that obtains a prediction error, and includes a delay circuit 11 and a subtractor 13. 15,24
Is an encoder that performs variable length coding, for example. A decoding unit 17 obtains a decoded image signal from the outputs of the prediction unit 8 and the encoder 15, and includes a decoding unit 18, a delay circuit 20, and an adder 22. 26 is a multiplexer, 28 is a transmission buffer memory, and 30 is a transmission line.

The operation of the above configuration will be described below.

First, the input image signal of the current frame which is A / D (analog / digital) converted is supplied from the input terminal 1,
It is sent to the motion vector binary detector 3 and the prediction error signal generator 10 via the signal line 2. The motion vector binary detector 3 obtains a motion vector based on the current frame input image signal and the previous frame decoded image signal supplied from the frame memory 4 via the signal line 5, and outputs the motion vector via the signal line 6 as a motion vector signal. It is supplied to the prediction unit 8 and the encoder 24. The prediction unit 8 that has been supplied with the motion vector signal performs motion compensation prediction based on this motion vector signal and the previous frame decoded image signal supplied from the frame memory 4 via the signal line 7, and outputs the prediction signal of the current frame. It is generated and supplied to the prediction error signal generation unit 10 and the decoding unit 17 via the signal line 9 in the same scanning sequence as the input image signal. Prediction error signal generator
In 10, the error between the input image signal supplied via the delay circuit 11 and the prediction signal supplied from the prediction unit 8 is obtained by the subtracter 13 and is used as a prediction error signal via the signal line 14 to the encoder.
Output to 15. The delay circuit 11 is used to match the timing of inputting the two signals to the subtractor 13. Next, in the encoders 15 and 24, the prediction error signal and the motion vector signal are, for example, variable-length coded, and are sent to the multiplexer 26 as the prediction error code and the motion vector code. The prediction error code is also sent to the decoding unit 17. Then, the multiplexer 26 multiplexes the prediction error code which is the output of the encoder 15 and the motion vector code which is the output of the encoder 24, and supplies it as a picture information code to the transmission buffer memory 28 via the signal line 27. The transmission buffer memory 28 is used to match the transmission speed of the image information code with the transmission speed of the transmission line 30.

In the decoding unit 17, the prediction error code is decoded by the decoder 18, the sum of the prediction error code and the prediction signal is obtained by the adder 22, and the decoded image signal is sent to the frame memory 4 via the signal line 23. This decoded image signal is transmitted to the motion vector binary detector 3
And used by the prediction unit 8. The delay circuit 20 is used to match the timing of inputting two signals to the adder 22.

FIG. 2 is a block diagram showing a configuration of a decoding device corresponding to the motion compensation predictive coding device in the embodiment of the present invention.

In FIG. 2, 30 is a transmission line, 32 is a receiving buffer memory, 34 is a demultiplexer for separating the output of the receiving buffer memory 32 into a motion vector code and a prediction error code, and 36 and 43 are the motion vector code and the prediction error code. Is a predictor for generating a prediction signal from the previous frame decoded image signal supplied from the frame memory 39 and the output of the decoder 36, 45 is an adder, and 47 is an output terminal.

The operation of the above configuration will be described below.

First, the image information code sent via the transmission line 30 is once stored in the reception buffer memory 32, then read out in accordance with the decoding processing speed, and sent to the demultiplexer 34 via the signal line 33. The demultiplexer 34 separates this into a motion vector code and a prediction error code, and sends the former to the decoder 36 through the signal line 35 and the latter to the decoder 43 through the signal line 42. The decoders 36 and 43 decode these and send them to the signal line 37 and the signal line 44 as a motion vector signal and a prediction error signal, respectively. The motion vector signal is supplied to the prediction unit 38 via the signal line 37, and the prediction unit 38 generates a prediction signal based on this and the previous frame decoded image signal supplied from the frame memory 39 via the signal line 40. . This prediction signal is signal line 41
And the prediction error signal supplied via the signal line 44 are added to the adder 45 to obtain a decoded image signal.

The decoded image signal is output from the output terminal 47 and stored in the frame memory 39 for use in the prediction unit 38.

Next, a more detailed structure of the block structure of FIG. 1 in one embodiment of the present invention will be described with reference to FIGS.

FIG. 3 is a block diagram showing a detailed configuration of the motion vector binary detector 3 shown in FIG.

In FIG. 3, reference numerals 48 and 55 are binarization circuits. Reference numeral 50 is a detection block configuration unit that divides the input image signal of the current frame into blocks, and includes a memory 51 and an address mapping unit 52. Reference numeral 57 is a reference block configuration unit that divides the decoded image signal of the previous frame into blocks.
It consists of 59. Reference numeral 62 is a binary operation unit that obtains an evaluation function value from each output of the detection / reference block configuration units 50 and 57, 64 is a comparison detection unit, and 65 is a control circuit.

The operation of the above configuration will be described below.

The signals supplied to the motion vector binary detection unit 3 are the current frame input image signal and the previous frame decoded image signal, which are supplied via the signal lines 2 and 5, respectively, and binarized by the binarization circuits 48 and 55. It is sent to the detection block construction unit 50 and the reference block construction unit 57. In the detection block configuration unit 50, the signal line
The binary image signal supplied via 49 is temporarily stored in the memory 51. Assuming that the size of the detection block in the vertical direction is 8 pixels and the input image signal is line-sequential scanning, the memory 51 requires a capacity of at least 8 scanning lines (1 bit / pixel). Reading of binary data from the memory 51 is performed by a memory address signal sent from the address mapping unit 52 via the signal line 53, and sent out in block units via the signal line 54. The signal line 54 in this case consists of eight signal lines, each of which is used to send data for one scan line of the detection block. That is, the data of each scanning line of the detection block is sent in parallel. The address mapping unit 52 is configured by using, for example, a memory table, and outputs the memory address signal based on the detection block number and the in-block relative address signal sent from the control circuit 65 via the signal lines 67 and 68. is there. on the other hand,
Also in the reference block configuration unit 57, the binary data of the reference block is similarly sent out from the signal line 61. However,
Unlike the detection block configuration unit, the address mapping unit
In 59, the memory address signal is generated also by using the shift control signal supplied from the control circuit 65 via the signal line 66. Also, the timing of data transmission and the memory size are different (the memory size is the vertical size 4 of the reference area).
At least 24 scanning lines (1 bit / pixel)
is necessary). The binary data of the detection block and the reference block thus obtained are sent to the binary operation unit 62, the evaluation function value indicating the degree of match / mismatch of the block is obtained, and the comparison detection unit 64 via the signal line 63. Is supplied to. In the comparison / detection unit 64, the shift control signal sent from the control circuit 65 via the signal line 66, which gives the minimum evaluation function value, is sent out from the signal line 6 as a motion vector signal.

FIG. 4 is a block diagram showing a more detailed configuration of the binarization circuitization 48, 55 in the motion vector binary detection unit of FIG. The figure shows a case where the domain of the image signal is divided into 6 sections by 5 threshold values and binarized.

In Figure 4, 71 ₁ to 71 ₅ is the threshold input terminal, 73 _1-7
3-5 comparator for comparing the current frame input image signal or the preceding frame decoded image signal and the threshold, 75 _{1-75 2} AND circuit, 76 an inverter, 79 is an OR circuit.

The operation of the above configuration will be described below.

The threshold input terminal 71 ₁ to 71 _5, the threshold t ₁ ~t ₅ is supplied _{(t 1 <t 2 <...} <t 5). The magnitude relationship between this threshold value and the image signal supplied from the signal line 2 is determined by the comparators 73 _{1 to} 7 3.
3 and ₅ are compared. When the image signal is below the threshold value, the value 1 is
The value 0 otherwise is output to the signal line _72d. The output values are combined by the logical operation in the logical product circuits 75 ₁ to 75 ₂ , the inverter 76, and the logical sum circuit 79, and the result is directly output from the signal line 49 as a binarized pixel value. The binarized pixel value at this time is such that the original pixel value l is t ₁ <lt ₂ , t ₃ <
It is 1 when either lt ₄ or t ₅ <l is satisfied, and is 0 otherwise.

FIG. 5 is a block diagram showing a more detailed configuration of the binary operation unit 62 in the motion vector binary detection unit of FIG.
The figure shows the case where the detection block size is 4 × 4 pixels.

In FIG. 5, reference numerals 80 ₁ to 80 ₄ denote binary line matching units, which are shift registers 81 and 82 and an exclusive OR circuit 8 respectively.
5 _{1 to} 85 ₄ and a bit addition circuit 87. 89 is a multiplexer that sequentially switches and outputs the outputs of the binary line matching units 80 ₁ to 80 ₄ , 91 is an adder, and 93 and 96 are registers.

The operation of the above configuration will be described below.

The data of the detection block and the reference block supplied via the signal lines 54 and 61 are binary line matching units for each scanning line.
Sent to 80 ₁ to 80 ₄ . Each binary line matching unit 80 ₁ to 8
In 0 _4, binary data is taken out for each pixel using the shift register 81 and 82, in between pixels of the same position in the block,
The exclusive OR circuits 85 _{1 to} 85 ₄ evaluate the match / mismatch, and the value 1 is supplied to the bit adder circuit 87 when they do not match, and the value 0 is supplied to the bit adder circuit 87 when they match. The bit addition circuit 87 calculates the sum of these, which indicates the number of mismatched pixels for each scanning line.
The sum is over the signal line 88 ₁ to 88 ₄ is output from the binary block matching unit 80 ₁ to 80 _4, is supplied to the multiplexer 89. The multiplexer 89 sequentially selects the input signal line according to the selection control signal sent from the signal line 69 _1, and supplies the input value to the adder 91 via the signal line 90. Adder 91,
The sum of the input values is obtained by the register 93, and the number of mismatched pixels between blocks is obtained as the evaluation function value. The register 96 is for output control, and the evaluation function value is the signal line.
Output from 63.

The signal line 69 ₂ is for supplying a clear input to the register 93, and the signal line 69 ₃ is for supplying an output control signal to the register 96.

FIG. 6 is a block diagram showing a more detailed structure of the comparison / detection unit 64 in the motion vector binary detection unit of FIG.

In FIG. 6, reference numeral 97 is a comparator for comparing the output of the binary operation unit 62 shown in FIG.
Is a multiplexer, and 101, 105, and 108 are registers.

The operation of the above configuration will be described below.

The register 101 holds the minimum value of the evaluation function at each time point, while the register 105 holds the shift amount corresponding thereto. The comparator 97 compares the evaluation function value supplied via the signal line 63 with the contents of the register 101, and sends the result as a selection control signal to the multiplexers 99 and 103 via the signal line 98. When the comparison result indicates that the input from the signal line 63 is small, the multiplexers 99 and 103 pass through the input evaluation function value from the signal line 63 and the input shift amount from the signal line 66 to the registers 101 and 105.
The content of is updated. The shift amount finally obtained in the register 105 is a motion vector. The register 108 is for output control. The signal line 70 ₁ is for a preset input to the register 101, and the signal line 70 ₂ is for an output control input to the register 108. The register 101 is preset to the maximum value that the evaluation function can take each time the detection of the motion vector of each detection block is started.

FIG. 7 is a block diagram showing a more detailed structure of the prediction unit 8 shown in FIG.

In FIG. 7, reference numeral 109 is a prediction block configuration unit that makes the output of the frame memory 4 shown in FIG.
It is composed of a memory 110 and an address mapping unit 111.
Reference numeral 114 is a scan conversion buffer memory for converting the scan casing.

In the above configuration, the operation in the prediction block construction unit 109 is almost the same as the operation described in the reference block construction unit 57 in FIG.
It is output from 3. This is once stored in the scan conversion buffer memory 114, and the scan sequence is converted and output from the signal line 9.

The above is the detailed configuration and operation of the motion compensation predictive coding apparatus according to the embodiment of the present invention.

As described above, according to the present embodiment, the current frame input image signal and the previous frame image signal are binarized to obtain the evaluation function value, and the motion vector is obtained. Can be made smaller. In addition, since the calculation time of the evaluation function value per time is short, it is possible to evaluate a large number of reference blocks, and since the binary image reflects the characteristics of the original image, the accuracy of the motion vector is consequently increased. Can be improved. Therefore, since the generation of prediction error information can be suppressed, it is possible to reduce the amount of code relating to the prediction error to be transmitted.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 is a block diagram showing a motion vector binary detector of the motion compensation predictive coding apparatus according to the second embodiment of the present invention.

8 is different from FIG. 3 in that instead of the reference block configuration unit 57 of FIG. 3, a reference block line configuration unit 115 including a memory 58 and an address mapping unit 116, and a control circuit 119 based on the reference block line configuration unit 115. That is the point.
Here, the "block line" refers to 8 scanning lines that are continuous when the size of the detection block in the vertical direction is 8 pixels,
The “reference block line” refers to a part included in the reference area in the block line.

In the above configuration, the address mapping unit 116
A memory address signal is generated based on the shift control signal sent from the signal line 66, the detection block number sent from the signal line 67, and the reference block line relative address signal sent from the signal line 120, and the signal line 117 is generated. To the memory 58 via. A binary image signal is sent from the memory 58 through the signal line 118 in block line units. In the binary operation unit 62, the binary data of the reference block is taken out every time the shift register 82 in FIG. 5 shifts by 1 bit. On the other hand, in the case of the first embodiment, in order to fetch the data of the reference block, it is necessary to shift the block by the horizontal size. The other operations are the same as those in the first embodiment.

As described above, according to the present embodiment, when all the reference blocks in the reference area are evaluated, the data of the reference blocks can be easily fetched, so that the calculation time per evaluation can be shortened. .

In the above two embodiments, the binarization circuits 48, 55
Although a configuration using a comparator is used, a configuration using a memory table may be used. In addition, from the pixel value of multiple bits, 1
The bit may be taken out, which has the advantage that no special device is required.

Further, although the case where the motion vector is detected between frames using the frame memories 4 and 39 has been described, the motion vector may be detected between fields using the field memory.

As described above, according to the present invention, when detecting a motion vector, the current frame image signal and the previous frame image signal are binarized by reflecting the feature of the local change of the original image, and By using a configuration in which a large number of reference blocks are evaluated, it is possible to detect a motion vector with high accuracy without increasing the device scale, and the effect is large.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a motion compensation predictive coding device according to an embodiment of the present invention, FIG. 2 is a block connection diagram of a decoding device corresponding to the same device, and FIGS. Partial block connection diagram, FIG. 9 is a conceptual diagram for explaining the basic binarization of the present invention, and FIG. 10 is a conceptual diagram for explaining the principle of conventional motion vector detection. 3 ... Motion vector binary detector, 48, 55 ... Binarization circuit, 5
0 ... Detection block configuration unit, 57 ... Reference block configuration unit, 62 ... Binary operation unit, 64 ... Comparison detection unit, 115 ... Reference block line configuration unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Uno 3-10-1 Higashisanda, Tama-ku, Kawasaki City, Kanagawa Matsushita Giken Co., Ltd. (56) References JP-B 59-33858 (JP, B2) Electronic IEICE Transactions, J68-B1 [1] (1985-1-25) P. 77-84

Claims (1)

[Claims] 1. A first binarizing unit for binarizing a current frame or field image signal, and a plurality of frame or field planes based on the binary image signal obtained by the first binarizing unit. Detection block forming means for forming a detection block divided into two, second binarizing means for binarizing the previous frame or field image signal, and a binary image signal obtained by the second binarizing means. Based on the same position as the detection block on the frame or field plane, the reference block forming means forms a reference block at a position shifted by at least one pixel unit, and 2 obtained by the detection block forming means and the reference block forming means. Binary operation means for obtaining an evaluation function value based on one binary image signal block, and a motion vector based on the evaluation function value obtained by the binary operation means A vector calculating means, wherein the first and second binarizing means compare the image signal with a plurality of threshold values by a combination of a plurality of comparators to determine a plurality of variable regions of the image signal. A motion-compensated predictive coding device that outputs a value of 0/1 set as a value different from that of an adjacent section for each section divided into pieces as a binary image signal.