KR100255633B1 - A high-speed moving picture motion estimation device - Google Patents

Abstract

PURPOSE: A method for estimating a motion of a high-speed dynamic image is provided to simplify a circuit, and to improve a processing speed by using a motion estimation mode according to a binarization. CONSTITUTION: The first frame memory(1) stores an image of a present frame. A frame delay unit(2) delays dynamic image data as much as 1 frame. The second frame memory(3) stores an image outputted from the frame delay unit(2). The first block memory(4) reads and stores image data of a macro block. The second block memory(5) reads and stores data relevant to a search region. A coincidence bit detection unit(15) detects whether a designated bit inputted is corresponded to a designated bit outputted from the first and the second block memory(4,5). A motion vector estimation unit(6) calculates a sum of bits outputted from the coincidence bit detection unit(15). An error signal detection unit(7) outputs a motion vector.

Description

High speed moving picture motion estimation device

1 is a block diagram according to a first embodiment of a conventional moving picture motion estimation apparatus.

FIG. 2 is a detailed block diagram of a motion vector estimating unit in FIG.

3 is a block diagram according to a second embodiment of the conventional moving picture motion estimation apparatus.

4 is a block diagram according to an embodiment of a fast moving picture motion estimation apparatus according to the present invention.

FIG. 5 is a detailed block diagram of a motion vector estimating unit in FIG.

The present invention relates to a fast moving picture motion estimation apparatus, and more particularly, to a fast moving picture motion estimation device that simplifies a circuit and improves processing speed by using a motion estimation method using binarization.

In a digital image processing system, a moving picture composed of consecutive frames has redundancy even in an intra frame, but has a higher temporal redundancy in an inter frame. The frame can be used to express the current frame with a small amount of information.

A conventional motion estimating apparatus for estimating the motion of an object present in a specific block in each frame of successive moving images stores a current frame for an input moving image as in the first embodiment shown in FIG. 1 frame memory (1) and a second frame memory (3) for storing an image delayed by one frame in the frame delay unit (2), and M × N serving as a basic unit of motion detection from the first frame memory (1). The image data of the block is read out and stored in the first block memory 4. On the other hand, as much data as the area to be searched to find a motion in the data stored in the second frame memories 1 and 3 is stored in the second block memory 5.

The motion vector estimator 6 obtains the difference component in pixel units between the current block and the specific block immediately before, selects a block whose minimum sum is absolute, and moves the distance difference between the block and the current block. Determines the distance, that is, the value of the motion vector, compensates for that distance, obtains the error component from the minimum error block memory (not shown), and multiplexes the value and the motion vector value stored in the motion vector memory (not shown). I'm taking a way.

2 is a detailed block diagram of the motion vector estimator 6, and its operation is as follows.

The subtractor 8 obtains the difference component in pixel units between the current block read out from the first and second block memories 4 and 5 and the specific block immediately before it, and then obtains the absolute value from the absolute stroke (9). In (10), the sum of the difference components in the block is obtained and stored in the error memory 11. In the minimum error block searcher 12, the minimum value among the values stored in the error memory 11 is found and applied to the motion vector calculator 13, and in the motion vector calculator 13, the difference between the current position and the position having the minimum value is used as the motion amount. Obtain and print

Related to the above-described motion estimation methods include motion estimation techniques (MPEG-video Working draft, 1992, 11 and MPEG-video Test Model 5) adopted by the Moving Picture Experts Group (MPEG), an international standard that is being promoted by ISO / IEC. , 1993, 4) and US patents (US 5,151,784, US 5,060,064, US 4,864,394).

The motion estimation method has the advantage of accurately estimating the motion, but the logic circuit required for the calculation is complicated, the memory, the adder and the subtractor are required, and as the search area increases, the calculation amount increases proportionally, making it difficult to implement. There is a problem following this.

A second embodiment of a conventional moving picture motion estimation apparatus using binarization to solve this problem is shown in FIG. In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals.

However, in the motion estimation apparatus using such binarization, a binarization unit 14-2 for binarization, a threshold calculator 14-1 for obtaining a threshold value, and a binary block for storing binarized image data There is a problem that the memory 14-3 must be provided.

In addition, US patents already submitted in relation to binarization include US 4,663,662, US 4,876,610, US 4,998,122, US 4,999,629, US 5,166,808. have.

Accordingly, an object of the present invention is to provide a fast moving picture motion estimation apparatus for simplifying a circuit and improving a processing speed by using a motion estimation method using binarization to solve the above problems.

In order to achieve the above object, a fast moving picture motion estimation apparatus according to the present invention comprises: a first frame memory for storing an image of a current frame with respect to inputted moving picture data; A second frame memory for storing an image of a frame delayed by one frame with respect to the moving image data; A first block memory for reading out and storing image data of a macroblock which is a basic unit of motion detection from the first frame memory; A second block memory for reading and storing data corresponding to a search area to detect movement from the second frame memory; A coincidence bit detector for detecting whether a predetermined bit output from the first and second block memories is matched by inputting predetermined bits among the pixel units constituting the first and second block memories; A motion vector estimator configured to calculate a sum of bits output from the coincidence bit detector, compare the result with a previous value, and update the current value to output a maximum value when the current value is large; And an error signal detector for outputting a motion vector by obtaining a distance difference from the current macroblock with respect to the macroblock having the maximum value output from the motion vector estimator.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

4 is a block diagram according to an embodiment of a fast moving picture motion estimation apparatus according to the present invention.

The block diagram shown in FIG. 4 includes a first frame memory 1 for storing an image of a current frame with respect to inputted moving image data, and a frame delay unit 2 for delaying one frame with respect to moving image data. And reading and storing the image data of the macroblock, which is a basic unit of motion detection, from the second frame memory 3, which stores the image of the frame output from the frame delay unit 2, and the first frame memory 1; A first block memory 4 for reading, a second block memory 5 for reading and storing data corresponding to a search area for detecting movement from the second frame memory 3, and first and second blocks Coincides with the coincidence bit detection unit 15 for detecting whether coincidence of the predetermined bits output from the first and second block memories 4 and 5 by inputting predetermined bits among the pixel units constituting the memories 4 and 5; Sum of bits output from the bit detector 15 After comparing the previous value with the previous value, if the current value is large, the motion vector estimator 6 for outputting the maximum value and output the maximum value, and has a maximum value output from the motion vector estimator 6 An error signal detection section 7 is provided for obtaining the motion vector from the distance difference from the current position macroblock with respect to the macroblock.

In addition, the coincidence bit detector 15 includes first and second exclusive logic logic gates 15-1 and 15-2 that input predetermined bits output from the first and second block memories 4 and 5, and the first and second exclusive logic gates 15-1 and 15-2. And an AND gate 15-3 for performing a logical product on the signals output from the double exclusive negative logic gates 15-1 and 15-2 and applying the result to the motion vector estimating unit 6.

FIG. 5 is a detailed block diagram of the motion vector estimating unit 6 in FIG.

The block diagram shown in FIG. 5 includes an adder 16 for calculating the sum of coincidence bits output from the AND gate 15-3, and the output of the macroblock from the adder 16 as input. A maximum value detector 17 for detecting the maximum value in comparison with the value, and a latch 18 for temporarily storing the maximum value output from the maximum value detector 17.

The operation of the present invention will now be described with reference to FIG. 4 and FIG.

First, referring to FIG. 4, the input image data is stored in the first frame memory 1 for storing the current frame, and the second frame memory (1) is image data delayed by one frame through the frame delay unit 2. 3) are stored.

In the first frame memory 1, as much as M × N macroblocks are stored in the first block memory 4, and in the second frame memory 3, as much data as the search area is stored in the first frame memory 1. 2 blocks are stored in the memory 5.

The first and second block memories 4 and 5 are each composed of 8 bits per pixel, but only upper 2 bits or upper 3 bits are used as input signals of the first and second exclusive logic gates 15-1 and 15-2. The output of the AND gate 15-3 when the values of the 2 bits or the upper 3 bits match, that is, when the outputs of the first and second exclusive logic gates 15-1 and 15-2 are 'high' logic levels. The signal also becomes a 'high' logic level and is input to the motion vector estimator 6.

A detailed block diagram of the motion vector estimating unit 6 is shown in FIG. 5 and its operation is as follows.

The motion vector estimator 6 calculates the sum using an adder 16 composed of a counter. The maximum value detector 17 uses the output of the adder 16 in units of macroblocks as a comparator as a previous value. If the current value is large compared to the above, the maximum value is detected by storing the value in the latch 18.

The error signal detection unit 7 calculates the distance difference between the macroblock having the maximum value and the current position macroblock and outputs a motion vector. The difference between the macroblock of the current position and the macroblock having the maximum value is output. Obtain and output to encode only the difference component.

The reason for using only the upper 2 bits or the upper 3 bits in the present invention is that the hardware-to-performance ratio is most efficient when the upper 2 bits or the upper 3 bits are used.

As described above, the fast moving picture motion estimation apparatus according to the present invention has the advantage that not only the hardware can be simplified but also the processing speed can be improved by processing the upper two bits or the upper three bits with the exclusive negative logic gate.

In addition, although the PSNR is slightly lower than the motion estimation by the entire search, there is an advantage that the size of the search area is not limited.

Claims (3)

A first frame memory for storing an image of a current frame with respect to inputted moving image data; A second frame memory for storing an image of a frame delayed by one frame with respect to the moving image data; A first block memory for reading out and storing image data of a macroblock which is a basic unit of motion detection from the first frame memory; A second block memory for reading and storing data corresponding to a search area to detect movement from the second frame memory; A coincidence bit detection unit for detecting whether an upper 2 bit or an upper 3 bit of 8 bits which are output pixel units of the first and second block memories match; A motion vector estimator configured to calculate a sum of bits output from the coincidence bit detector, compare the result with a previous value, and update the current value to output a maximum value when the current value is large; And an error signal detector for obtaining a distance difference from the current position macroblock with respect to the macroblock having the maximum value output from the motion vector estimator and outputting a motion vector. 2. The logic circuit of claim 1, wherein the coincidence bit detection unit comprises: first and second exclusive logic logic gates configured to input bits output from the first and second block memories; And an AND gate for performing an AND operation on the signals output from the first and second exclusive sub logic gates and applying the result to the motion vector estimator. 3. The apparatus of claim 2, wherein the motion vector estimator comprises: an adder for calculating a sum of coincidence bits output from the AND gate; A maximum detector for detecting a maximum value by comparing the previous value with an output of the macroblock from the adder; And a latch for temporarily storing the maximum value output from the maximum value detector.