JPH08130566A - High frequency digital signal reception device - Google Patents

Abstract

PURPOSE: To prevent the interference of a digital clock from outside by storing an input filter, an oscillator, a mixer, an intermediate frequency tuning filter and an I/Q detector in the same shielding case. CONSTITUTION: An input terminal 1 provided for a vertical side board 43, a fixed input filter 2 and a gain control amplifier 4 are provided for the division room 49 of the shielding case 40. A division room 50 is provided with a mixer 5 and a division room 51 is provided with the oscillator 6 inputting a signal to the mixer 5. A division room 53 is provided with a gain control amplifier 10 and the intermediate frequency tuning filter 11, a division room 54 is provided with the I/Q detector 19 and output terminals 17 and 18 are installed on a vertical side board 44. An unnecessary signal among high frequency digital signals inputted to the input terminal 1 is removed and amplified by the input filter 2, and the frequency given from the oscillator 6 is mixed by the mixer 5 so as to obtain the intermediate frequency. The intermediate frequency is amplified and is detected and outputed by the I/Q detector 19 through the intermediate frequency tuning filter 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency digital signal receiving apparatus for receiving a digital signal using a cable such as CATV.

[0002]

2. Description of the Related Art A conventional high frequency digital signal receiving apparatus will be described below.

FIG. 2 shows a conventional high frequency digital signal receiving device.
Shown in In FIG. 2, reference numeral 23 denotes an input terminal, a variable input filter 24 connected to the input terminal 23, a first gain control amplifier 25 connected to an output side of the variable input filter 24, and a first gain control amplifier 25. A gain control terminal 26 connected to a gain control input of a gain control amplifier 25;
Of the gain control amplifier 25 is connected to the variable stage interstage filter 27, the output of the variable stage interstage filter 27 is connected to one input of the mixer 28, and the other input of the mixer 28 is The oscillator 29 to which the output is connected and the PLL control unit 30 to which the other output of the oscillator 29 is connected
A low-pass filter 31 connected between the output of the PLL control unit 30 and the input of the oscillator 29;
A control terminal 32 connected to the frequency data input terminal of the control unit 30. The output of the low-pass filter 31 is connected to the variable input filter 24 and the inter-variable-stage filter 27 so that a single shield case 38 is formed. It was stored in. A second gain control amplifier 33 having the output of the mixer 28 connected to the outside of the shield case 38.
The gain control input of the second gain control amplifier 33 is connected to the gain control terminal 26, and the output of the second gain control amplifier 33 is connected to the intermediate frequency tuning filter 34 and the intermediate frequency tuning filter 34. An I / Q detector 35 to which the output of the tuning filter 34 is connected, and a first output terminal 36 to which the I signal output of this I / Q detector 35 is connected,
The second output terminal 37, to which the Q signal output of the I / Q detector 35 is connected, is mounted on the printed circuit board on which the shield case 38 is mounted to constitute the high frequency digital signal receiving device.

That is, the second gain control amplifier 33
, Intermediate frequency tuning filter 34, and I / Q detector 35
Was a high-frequency digital signal receiving device, but was not housed in the same shield case 38.

[0005]

As described above, in the conventional configuration, the second gain control amplifier 33, the intermediate frequency tuning filter 34, and the I / Q detector 35 have relatively low frequencies (conventional). In the example, since this intermediate frequency is a 44 MHz band) and is a digital signal, it was not housed in the same shield case 38, but was mounted on the same printed circuit board as other digital components. Therefore, there is a problem that the digital clock interference from the printed circuit board is inevitable.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a high-frequency digital signal receiving apparatus which prevents digital clock interference from the outside.

[0007]

In order to achieve this object, a high frequency digital signal receiving apparatus of the present invention has an input terminal to which a high frequency digital signal is input, an input filter connected to this input terminal, and this input. A mixer in which the output of the filter is supplied to one input and the output of the oscillator is connected to the other input, an intermediate frequency tuning filter to which the output of this mixer is supplied, and an output of this intermediate frequency tuning filter Is provided, and an output terminal to which the output of this I / Q detector is connected is provided, and these components are housed in the same shield case.

[0008]

With this configuration, the second gain control amplifier, the intermediate frequency tuning filter, and the I / Q detector are also mounted in the same shield case, so that the digital clock interference from the outside is shielded by the shield case. It will be.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a layout of each block of a high frequency digital signal receiving apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an input terminal, a fixed input filter 2 connected to the input terminal 1, a first gain control amplifier 4 connected to the output side of the fixed input filter 2, and A gain control terminal 3 connected to a gain control input of a first gain control amplifier 4, and a mixer 5 having one input connected to the output of the first gain control amplifier 4.
A first oscillator 6 having one output connected to the other input of the mixer 5, a PLL control unit 8 connected to the other output of the first oscillator 6, and an output of the PLL control unit 8. Is connected to the input of the first oscillator 6, a control terminal 7 connected to the frequency data input terminal of the PLL controller 8, and the output of the mixer 5 are connected. The second gain control amplifier 10 and the gain control input of the second gain control amplifier 10 are connected to the gain control terminal 3, and the intermediate frequency to which the output of the second gain control amplifier 10 is connected. The tuning filter 11 and an I / Q to which the output of the intermediate frequency tuning filter 11 is connected
The detector 19, the first output terminal 17 to which the Q signal output of the I / Q detector 19 is connected, and the I / Q detector 19
I signal output is connected to the second output terminal 18.

The configuration of the I / Q detector 19 is as follows. That is, the two divider 12 to which the output of the intermediate frequency tuning filter 11 is connected, the first detector 13 to which one output of the two divider 12 is connected to one input, and the first detector 90-degree phase shifter 14 connected to the other input of the divider 13, a second oscillator 15 connected to the input of the 90-degree phase shifter 14, and the second divider 1
A second detector 16 whose other output is connected to one input, and the second oscillator 15 is connected to the other input of this second detector 16 and its output is the second Is connected to the output terminal 18. The output of the first detector 13 is connected to the first output terminal 17. These parts are housed in the same shield case 40.

The arrangement of each component housed in the metallic shield case 40 will be described below.

The shield case 40 includes a first lateral side plate 41.
And a second horizontal side plate 42 provided in parallel with the first horizontal side plate 41, a first vertical side plate 43 and a second vertical side plate 44 provided perpendicularly to the horizontal side plates 41, 42. It has a parallelogram shape. The partition plates made of metal are arranged in parallel to the vertical side plates 43, 44 in order from the first vertical side plate 43 side to the first partition plate 4
5, a second partition plate 46, and a third partition plate 47 are provided.

Also, from the first vertical side plate 43 to the first partition plate 4
A fourth partition plate 48 is provided in parallel with the first lateral side plate 41 through the first partition plate 41 to the second partition plate 46 to form each compartment.

In the compartment 49 partitioned by the partition plate 45, the partition plate 48 and the horizontal side plate 42, the input terminal 1 provided on the vertical side plate 43, the fixed input filter 2 and the first gain control amplifier 4 are provided. ing. The mixer 5 is mounted in a compartment 50 partitioned by the partition plate 45, the partition plate 46, the partition plate 48, and the lateral side plate 42. The oscillator 6 is mounted in a compartment 51 partitioned by the partition plate 45, the partition plate 46, and the lateral side plate 41. A PLL controller 8 and a low-pass filter 9 are mounted in a compartment 52 partitioned by the partition plate 48, the partition plate 45, and the lateral side plate 41, and the lateral side plate 41 has a gain control terminal 3 and a control terminal 7. It is installed. Partition plate 46 and partition plate 4
In the compartment 53 partitioned by 7, the second gain control amplifier 10 is mounted on the lateral side plate 42 side, and the lateral side plate 41 is provided.
The intermediate frequency tuning filter 11 is mounted on the side.

Further, the partition plate 47, the lateral side plates 41 and 4
2. The I / Q detector 19 is mounted in the compartment 54 partitioned by the vertical side plate 44, and the first output terminal 17 and the second output terminal 18 are mounted on the vertical side plate 44.
This is because the length from the first detector 13 to the first output terminal 17 and the wiring length from the second detector 16 to the second output terminal 18 are made equal, and the symmetry of the I / Q detection output is obtained. Is to keep.

The first output terminal 17 and the second output terminal 18 are connected to the lateral side plate 4 while maintaining the symmetry of the I / Q detection output.
1 may be provided. In this case, when the shield case 40 is planted on the printed board with the side plate 41 side down, the signals line up on the printed board side, which is convenient for wiring. Also,
Gain control terminal 3 connected to the second gain control amplifier 10
May be provided on the lateral side plate 41 side of the compartment 53. In this case, the number of gain control terminals 3 increases, but the compartments 49 and 5
There is no noise in 0. Further, when the shield case 40 is embedded in the printed circuit board in a face-down type, it becomes stable against vibration. Therefore, when the high-frequency digital signal receiving apparatus of the present invention needs to be stable against vibration, the face-up type print is performed. It is also possible to implant it on the substrate. In addition, since the height dimension can be reduced by using the face-down type, it is particularly effective when a plurality of printed circuit boards are stacked and housed.

In any case, the frequencies handled in this way,
It is important to divide into compartments according to the function and store them as in this embodiment. In particular, it is preferable that the partition plate 46 and the partition plate 47 be doubled in some cases to complete the partition.

Here, the function and frequency of each compartment will be described. The compartment 49 is the filter 2 for the input signal of 50 MHz to 550 MHz and the first gain control amplifier 4, and it is important not to receive an interference signal from the outside. The compartment 50 is a mixer that converts the input frequency to an intermediate frequency in the 612 MHz band, and it is important to prevent this signal from leaking to the outside. The reason why the intermediate frequency is set to the 612 MHz band is described in detail in Japanese Patent Application No. 6-232873. Compartment 51 has approximately 662 MHz to 1162 M
It is a variable frequency of Hz and it is important to prevent the signal from leaking to the outside. The compartment 52 is a digital signal for channel selection, and this digital signal is transmitted to the outside, especially the compartment 49.
It is important to take care not to leak into Compartment 5
3 is a place for accurately amplifying the 612 MHz band which is an intermediate frequency, and it is necessary to minimize the intrusion of an interfering signal from the outside. That is, the partition plates 46 and 47 need to be mounted more completely. The compartment 54 is an I / Q detector and handles the detection output signal frequency band from the 612 MHz band. Here, it is necessary to prevent intrusion of signals from the outside and perform detection with few errors. By arranging the compartments in this manner, the first oscillator 6 and the second oscillator 15 are separated by the partition plate 46 and the partition plate 47, and are arranged diagonally.

The operation of the high-frequency digital signal receiving device configured as described above will be described below.

50 MHz to 550 input to the input terminal 1
The fixed frequency of the high frequency digital signal of MHz is 50 by the fixed input filter 2.
Remove unnecessary signals other than MHz to 550 MHz. Then, after being amplified by the first gain control amplifier 4, the frequency given from the oscillator 6 is mixed by the mixer 5 to obtain an intermediate frequency in the 612 MHz band. This intermediate frequency is amplified by the second gain control amplifier 10, and then the intermediate frequency tuning filter 1
At 1, only the 612 MHz band, which is the intermediate frequency, is obtained. After that, the signal is detected by the I / Q detector 19, the I signal output is output from the second output terminal 18, and the Q signal output is output from the first output terminal 17. The I signal output and the Q signal output are then processed by a digital signal demodulator having a digital clock.

As described above, according to the present embodiment, the high-frequency digital signal receiving device of the present embodiment is housed in the same shield case 40, so that the shield case 40
Due to the shielding effect provided by, it is possible to prevent digital clock interference with the high frequency digital signal receiving apparatus.

As another effect, the first oscillator 6
In order to reduce the spurious interference due to the mutual interference of the second oscillator 15, the partition plate 46 and the partition plate 47 separate the first oscillator 6 and the second oscillator 15 from each other and on the diagonal line. This arrangement also has the effect of reducing spurious interference due to mutual interference between the first oscillator 6 and the second oscillator 15.

Another effect is that by separating the compartment 52, the digital signal for channel selection does not interfere with the other compartments.

As another effect, by providing the compartment 53, the first oscillator 6 and the second oscillator 15 can be separated from each other, so that the first oscillator 6 and the second oscillator 15 can be separated from each other.
There is also an effect that spurious interference due to mutual interference between the oscillators 15 can be reduced.

As another effect, by providing the first output terminal 17 and the second output terminal 18 on the lateral side plate 41 while maintaining the symmetry of the I / Q detection output, the lateral side plate 41 side is turned down. When the shield case 40 is implanted on the printed circuit board, signals are lined up in the same direction on the printed circuit board side, which is advantageous in terms of wiring.

[0028]

As described above, according to the high frequency digital signal receiving apparatus of the present invention, the input terminal to which the high frequency digital signal is input, the input filter connected to this input terminal, and the output of this input filter are A mixer to which the output of the oscillator is connected, the intermediate frequency tuning filter to which the output of this mixer is supplied, and the output of this intermediate frequency tuning filter I A / Q detector and an output terminal to which the output of this I / Q detector is connected are provided, and these components are housed in the same shield case, so that digital clock interference is shielded by the shield case. As a result, there is an effect that a stable high-frequency digital signal receiving device that does not enter the shield case can be realized without interference.

[Brief description of drawings]

FIG. 1 is a block diagram showing a layout of each block of a high frequency digital signal receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional high-frequency digital signal receiving device.

[Explanation of symbols]

 1 Input Terminal 2 Fixed Input Filter 5 Mixer 6 First Oscillator 11 Intermediate Frequency Tuning Filter 17 First Output Terminal 18 Second Output Terminal 19 I / Q Detector 40 Shield Case

Claims (6)

[Claims] 1. An input terminal to which a high-frequency digital signal is input, an input filter connected to this input terminal, an output of this input filter is supplied to one input, and an output of an oscillator is supplied to the other input. The connected mixer, the intermediate frequency tuning filter to which the output of this mixer is supplied, and the output of this intermediate frequency tuning filter are connected to I
A high-frequency digital signal receiving device having an A / Q detector and an output terminal to which the output of the I / Q detector is connected, and these parts are housed in the same shield case. 2. The high frequency digital signal receiving apparatus according to claim 1, wherein at least one shield plate is arranged between the oscillator and the oscillator used for the I / Q detector. 3. The high frequency digital signal receiving apparatus according to claim 2, wherein the oscillator and the oscillator used for the I / Q detector are arranged on a diagonal line in the same shield case. 4. An input terminal is provided on one vertical side surface of a shield case having a substantially rectangular shape, an input filter and a mixer are arranged following the input terminal, and the input filter, the mixer and a partition plate are provided. An oscillator for supplying an oscillating frequency to the mixer and a PLL control section for controlling the oscillating frequency of the oscillator are arranged substantially parallel to each other with the oscillator interposed therebetween.
The high-frequency digital signal receiver described. 5. The high frequency digital signal receiving apparatus according to claim 2, wherein a compartment for mounting an intermediate frequency tuning filter is provided between an oscillator for supplying an oscillation frequency to the mixer and the I / Q detector. 6. The shield plate is provided with P in the vicinity of the first lateral side plate.
The high frequency digital signal receiving apparatus according to claim 4, wherein a control terminal of the LL control unit and an output terminal of the I / Q detector are provided.