JP3055399B2 - High frequency signal processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency signal processing unit used in a video tape recorder (hereinafter, referred to as VTR) or the like.

[0002]

2. Description of the Related Art A conventional high-frequency signal processing unit will be described below.

A tuning circuit of a conventional high-frequency signal processing unit includes an input terminal 1 for inputting an RF signal and a filter circuit connected to the input terminal 1 in a housing 80 shown in FIG. 2, an RF amplifier 3 connected to the output of the filter circuit 2, an inter-stage circuit 4 connected to the output of the RF amplifier 3, an output of the inter-stage circuit 4, and a local oscillation circuit 5
, An IF amplifier 7 to which the output of the mixer 6 is connected, and an IF output terminal 8 to which the output of the IF amplifier 7 is connected. Also, an oscillation element 9 for generating a reference frequency, a reference oscillation circuit 10, a frequency divider 11 connected to the reference oscillation circuit 10, and an output of the frequency divider 11 and the other output of the local oscillation circuit 5 Also provided is a phase comparator 13 to which the connected frequency dividers 12 are respectively input, and a loop filter 14 connected to the output of the phase comparator 13, and the output of the loop filter 14 is the input of the local oscillation circuit 5. Connected to
The local oscillation circuit 5 constitutes a first PLL circuit.
Control of the oscillation frequency.

On the other hand, an RF modulation circuit section has an input terminal 15 for inputting a video signal in a housing 81 shown in FIG.
And a waveform shaping circuit 16 connected to the input terminal 15.
And an input terminal 17 to which an audio signal is input separately from the input terminal 15, and an F to which an output of the input terminal 17 is connected.
An M modulation circuit 18, a mixer circuit 20 to which an output of the FM modulation circuit 18, an output of the waveform shaping circuit 16, and one output of the carrier oscillation circuit 19 are respectively input, and an output of the mixer circuit 20 are connected. And an RF output terminal 21. Further, the oscillation element 22 for generating the reference frequency
And a reference oscillation circuit 23 connected to the oscillation element 22.
A frequency divider 24 connected to the reference oscillation circuit 23,
A phase comparator 26 to which the output of the frequency divider 24 and a frequency divider 25 connected to the other output of the carrier oscillation circuit 19 are input, and a loop filter connected to the output of the phase comparator 26 The output of the loop filter circuit 27 is connected to the carrier oscillation circuit 19 to form a second PLL circuit, and the output signal frequency of the RF output terminal 21 is controlled by the PLL circuit. Was.

[0005]

However, in recent years, with the need to combine high-frequency signal processing units, and to meet the demand for downsizing and cost reduction of high-frequency units, a tuning circuit is conventionally provided in a housing 80 as in the prior art. However, there is a problem in that the cost and the shape are limited, and the demand for cost reduction and size reduction cannot be satisfied.

An object of the present invention is to solve such problems and to provide a small and low-cost high-frequency signal processing unit without deteriorating the conventional functions and characteristics. .

[0007]

In order to achieve this object, a high-frequency signal processing unit according to the present invention comprises an oscillation element in which a reference frequency signal of a first PLL circuit and a reference frequency signal of a second PLL circuit are one. It is constituted so that it may be supplied from.

[0008]

With this configuration, one expensive oscillation element can be used as the first
And the second PLL circuit can be controlled, so that cost reduction can be realized. In addition, the number of parts is reduced, so that downsizing can be realized.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

The high-frequency signal processing unit according to the present invention is shown in FIG.
As shown in (1), it is composed of a tuning circuit section and an RF modulation circuit section. The tuning circuit section includes an input terminal 31 to which an RF signal is input, a filter circuit 32 connected to the input terminal 31, an RF amplifier 33 connected to an output of the filter circuit 32, and an RF amplifier 33 , A mixer 36 to which the output of the inter-stage circuit 34 and one output of the local oscillation circuit 35 are input, and an IF to which the output of the mixer 36 is connected. It has an amplifier 37 and an IF output terminal 38 to which the output of the IF amplifier 37 is connected. A frequency divider 41 for dividing the frequency of the reference frequency signal, and a frequency divider 42 to which the output of the frequency divider 41 and the other output of the local oscillation circuit 35 are connected are respectively inputted. And a loop filter 44 connected to the output of the phase comparator 43. The output of the loop filter 44 is connected to the input of the local oscillation circuit 35 to form a first PLL circuit 82. The oscillation frequency of the local oscillation circuit 35 is controlled.

On the other hand, the RF modulation circuit section has an input terminal 45 to which a video signal is input, a waveform shaping circuit 46 connected to the input terminal 45, and an input to which an audio signal is input separately from the input terminal 45. A terminal 47, an FM modulation circuit 48 to which the output of the input terminal 47 is connected, and an output of the FM modulation circuit 48, an output of the waveform shaping circuit 46, and one output of the carrier oscillation circuit 49 are input. The mixer circuit 50 includes an RF output terminal 51 to which an output of the mixer circuit 50 is connected. A frequency divider 54 for dividing the frequency of the reference frequency signal, and a frequency divider 55 connected to the output of the frequency divider 54 and the other output of the carrier oscillation circuit 49
And a loop filter circuit 57 connected to the output of the phase comparator 56. The output of the loop filter circuit 57 is connected to the carrier oscillation circuit 49, and the second A PLL circuit 83 is configured, and the output signal frequency of the RF output terminal 51 is controlled by the second PLL circuit 83. The output of the oscillation element 61 for generating the reference frequency signal of the first PLL circuit 82 and the second PLL circuit 83 and the output of the reference oscillation circuit 60 to which the oscillation element 61 is connected are the first
Of the frequency divider 41 forming the PLL circuit 82 and the input of the frequency divider 54 forming the second PLL circuit 83.

The operation of the high-frequency signal processing unit configured as described above will be described below.

In FIG. 1, a desired channel frequency set from an RF signal (television broadcast wave) input from an input terminal 31 is changed by a filter circuit 32 (the pass frequency of the filter circuit 32 is variable by the channel setting of a set microcomputer. ), The RF signal is amplified by an RF amplifier 33, unnecessary signal components are removed by an interstage circuit 34, and the signal is input to a mixer 36. Here, the local oscillation circuit 35
Generates a frequency higher by the intermediate frequency (IF) than the desired channel frequency set by the first PLL circuit 82, the mixer 36 converts the RF signal into an IF frequency, and the IF amplifier 37 Amplify with IF
Output from the output terminal 38.

On the other hand, in the RF modulation circuit section, the waveform of the video signal input from the input terminal 45 is shaped by the waveform shaping circuit 46 and is input to the mixer circuit 50. Here, the video wave of the carrier oscillation circuit 49 is oscillated by the second PLL circuit 83 at the set channel frequency, and
Is subjected to AM modulation of the waveform-shaped video signal to become a video carrier. The audio signal input from the input terminal 47 is FM-modulated by the FM modulation circuit 48 and output as an audio carrier, becomes a sub-carrier of the AM-modulated video carrier by the mixer circuit 50, and is output from the RF output terminal 51. Is done.

At this time, the reference signal frequency of the first PLL circuit 82 and the second PLL circuit 83 is generated by the oscillation element 61 and the reference oscillation circuit 60, and the frequency divider of the first PLL circuit 82 41 and the frequency divider 54 of the second PLL circuit 83.

More specifically, as shown in FIG. 2, a tuning circuit section 84 and an RF modulation circuit section 85 are mounted in a single housing 86 by being separated by a metal partition plate 87. . The oscillation element 61 and the reference oscillation circuit 60 are configured in a tuning circuit section 84, an output terminal 62 for outputting a reference signal of the reference oscillation circuit 60 is provided, and a reference signal is input to an RF modulation circuit section 85. If the input terminal 63 is provided and the reference signal is connected outside the housing 86, various disturbances to the high-frequency signal processing circuit due to the reference signal can be reduced.

The oscillation element 61 and the reference oscillation circuit 60 may be mounted in the RF modulation circuit section 85. In this case, the reference signal output is provided in the RF modulation circuit unit 85 and the reference signal input is provided in the channel selection circuit unit 84.

Note that, as shown in FIG.
And the RF modulation circuit unit 85 may be mounted in independent housings.

[0019]

As described above, according to the high-frequency signal processing unit of the present invention, the reference frequency of the first PLL circuit and the reference frequency of the second PLL circuit are supplied from one oscillation element. Therefore, miniaturization can be realized.

Further, since the oscillation element is expensive, it contributes to cost reduction. Furthermore, by configuring a reference oscillation circuit in one of the channel selection circuit section and the RF modulation circuit section, providing an output terminal for the reference signal, and providing an input terminal for this reference signal in the other circuit section, Since it is not necessary to route the reference signal in the same housing as the high-frequency signal processing circuit, various disturbances to the high-frequency signal processing circuit due to the reference signal can be reduced. Further, by providing the output terminal for the reference signal, the reference signal can be used as a control reference signal for the set-side circuit, which contributes to cost reduction of the entire set.

[Brief description of the drawings]

FIG. 1 is a block diagram of a high-frequency signal processing unit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a high-frequency signal processing unit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a high-frequency signal processing unit according to another embodiment of the present invention.

FIG. 4A is a block diagram of a channel selection circuit of the conventional high-frequency signal processing unit. FIG. 4B is a block diagram of an RF modulation circuit of the conventional high-frequency signal processing unit.

[Explanation of symbols]

 Reference Signs List 60 Reference oscillation circuit 61 Oscillator 62 Reference signal output terminal 63 Reference signal input terminal 82 First PLL circuit 83 Second PLL circuit 84 Tuning circuit section 85 RF modulation circuit section

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-300717 (JP, A) JP-A-1-236736 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 H03J 1/00 H03L 7/22 H04B 1/16 H04N 5/44-5/46

Claims (3)

(57) [Claims] A tuning circuit controlled by a first PLL circuit; and an RF modulation circuit controlled by a second PLL circuit, wherein the first PLL circuit and the second PLL circuit are provided. A high-frequency signal processing unit provided with an oscillation element for supplying a reference frequency signal to a circuit. 2. The tuning circuit unit and the RF modulation circuit unit are mounted in independent casings, respectively, and each casing has a reference signal output terminal for outputting a reference signal or a reference signal input terminal. 2. The high-frequency signal processing unit according to claim 1, further comprising a reference signal input terminal. 3. The tuning circuit section and the RF modulation circuit section are housed in a single metal-shielded housing, and the tuning circuit section has a reference signal output terminal for outputting a reference signal, or
A reference signal input terminal for inputting a reference signal;
2. The high-frequency signal processing unit according to claim 1, wherein the modulation circuit section is provided with a reference signal input terminal for inputting a reference signal or a reference signal output terminal for outputting a reference signal so as to complement the tuning circuit section.