JPH1155117A - Pll composite device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL composite device which is practicable in use by applying an external reference frequency signal oscillated from an external crystal vibrator to plural PLL circuits via a low-pass filter that eliminates harmonic components, so as to use a single crystal vibrator in common. SOLUTION: A modulator 10, a tuner 20, and an IF block 30 are respectively configured with a PLL circuit and provided with input terminals 11, 21, 31 that receive an external reference frequency signal respectively. The external reference frequency signal from an external oscillation circuit 40 with a crystal vibrator 41 and an amplifier 42 is given to the input terminals 11, 21, 31 respectively, and low-pass filters 51, 52, 53 are interposed respectively between the external oscillation circuit 40 and the input terminals 11, 21, 31. Thus, the reference frequency signal oscillated from the external crystal vibrator 41 is distributed to plural PLL circuits 10, 20, 30 respectively, and then the PLL composite device is realized in a constitution which is practicable in use, while using the a crystal vibrator 41 in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL composite device in which a plurality of PLL circuits are combined, and more particularly to a PLL composite device suitable for use in combining a plurality of PLL circuits in a VCR or the like. .

[0002]

2. Description of the Related Art In recent years, in a VCR, a tuner, a modulator, and an IF circuit have been reduced in size and integrated. Have been done.

It is not rational to provide a quartz oscillator individually for a plurality of modules employing such a PLL system, and it is desired to share them. Therefore, Japanese Unexamined Utility Model Publication No. Hei. The technique disclosed in Japanese Patent No. 174736 is known.

[0004]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
In a multi-function device, each of them simply connects the crystal unit to each module, but when attempting to distribute from the outside, a considerable level of harmonic components other than the fundamental wave are included in the semiconductor amplifier circuit. Further, there is a problem that the distortion is further increased via the active element and the active element, and cannot be adopted at a practical level.

[0005] The present invention has been made in view of the above problems, and has as its object to provide a practically usable PLL composite device.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a plurality of reference frequency signals using an external quartz oscillator are passed through a low-pass filter for removing harmonic components. And a common crystal resonator. According to the first aspect of the present invention, a reference frequency signal using an external quartz oscillator is distributed and supplied to a plurality of PLL circuits through a low-pass filter, but passes through the low-pass filter. As a result, the harmonic components are removed, and no malfunction is caused by distortion due to the harmonic components. Further, since the reference frequency signal can be distributed and supplied without worrying about harmonic components, the quartz oscillator is used substantially in common.

In this case, the low-pass filter only needs to remove harmonic components, and various configurations are possible. As an example, the invention according to claim 2 is the PLL composite device according to claim 1, wherein the low-pass filter is constituted by a band-pass filter. In the invention according to claim 2 configured as described above, the reference frequency signal using the external quartz oscillator passes through the band-pass filter, and thus, together with the harmonic component,
Low frequency components and DC components are also removed. Of course, the original reference frequency is set at the center of the pass band.

On the other hand, in a plurality of modules adopting the PLL system, it is useful not only to share the crystal oscillator but also to share the circuit more. As an example, the invention according to claim 3 uses a plurality of modules each including a local oscillator, a programmable frequency divider that performs a desired frequency division on the oscillation output of each local oscillator, and an external crystal resonator. An internal oscillating circuit that receives the reference frequency signal that has been input and oscillates and outputs the same at a corresponding frequency, a phase comparison circuit that compares the frequency of the programmable frequency divider with the oscillation output of the internal oscillating circuit, A PLL control device including a feedback control circuit for performing feedback control of the oscillation frequency of each local oscillator based on a comparison result of the circuits, wherein the programmable frequency divider is shared by a plurality of modules. The above-mentioned programmable frequency divider holds various frequency division commands and issues frequency division commands according to the module used. And Division command holding means for outputting, there corresponds to a module for use in selecting the output of said local oscillator as a constituent comprising an input selecting means for the input of the programmable frequency divider.

According to the third aspect of the present invention, each of the plurality of modules includes a local oscillator, and the oscillation output of the local oscillator is input to a programmable frequency divider to obtain a desired frequency division. Done. In addition, a reference frequency signal using an external crystal oscillator is input to an internal oscillation circuit to obtain an oscillation output of a corresponding frequency. The frequency division result of the programmable frequency divider and the oscillation of the internal oscillation circuit are obtained. The output and the phase are compared by a phase comparison circuit. Then, the feedback result of the phase comparison circuit is used to feedback-control the oscillation frequency of each local oscillator by a feedback control circuit, thereby forming a so-called PLL circuit.

Incidentally, the programmable frequency divider is not provided individually for each of a plurality of modules.
Dividing command holding means holds a dividing command necessary for each module, and outputs a dividing command corresponding to the module to be used to the programmable frequency divider. The input selection means selects the output of the local oscillator corresponding to the module to be used and sets the output as the input of the programmable frequency divider. Then, only the oscillation output of the local oscillator of the module to be used is input to the programmable frequency divider, and the programmable frequency divider is frequency-divided by the corresponding frequency division command, and the oscillation output of the internal oscillation circuit and the frequency division result are phase-shifted. The phase is compared by the comparison circuit, and the phase comparison result feeds back the oscillation frequency of the local oscillator via the feedback control circuit.

In this case, it is not necessary to form a feedback loop except for the module to be used. Therefore, the frequency division result of the programmable frequency divider only needs to be supplied to at least the phase comparison circuit to be used. An extra phase comparison circuit may not be provided, and the invention according to claim 4 is the PLL composite device according to claim 3, wherein the frequency division result of the programmable frequency divider is determined in correspondence with a module to be used. It has a configuration having output switching means for switching to and outputting the corresponding phase comparison circuit.

According to a fourth aspect of the present invention, an output switching means is provided, and the phase comparison circuit corresponds to a frequency division result of the programmable frequency divider corresponding to a module to be used. The output is switched to.

[0013]

As described above, according to the present invention, a PLL capable of sharing a crystal oscillator by substantially distributing and supplying a reference frequency signal using an external crystal oscillator to a plurality of PLL circuits. A composite device can be provided.

Further, according to the second aspect of the present invention, it is possible to eliminate the influence of not only harmonic components but also low frequency and DC components. Furthermore, according to the third aspect of the invention, it is possible to share not only the crystal oscillator but also the programmable frequency divider. Furthermore, according to the invention of claim 4, the frequency division result of the programmable frequency divider can be supplied only to the necessary phase comparison circuit.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a VCR realized by a PLL multifunction peripheral according to an embodiment of the present invention.

In FIG. 1, a modulator 10, a tuner 20, and an IF block 30 are each constituted by a PLL circuit, and are provided with input terminals 11, 21, 31 for inputting an external reference frequency signal. A quartz oscillator 41 and an amplifier 42 are connected to these input terminals 11, 21, 31.
A reference frequency signal is input from the external oscillation circuit 40 having the following. Low pass filters 51, 52, 53 are interposed between the external oscillation circuit 40 and the input terminals 11, 21, 31 respectively. ing.

When the external oscillation circuit 40 amplifies the oscillation output of the crystal oscillator 41 with the amplifier 42 and distributes and supplies the output to each PLL circuit, the external oscillation circuit 40 includes not only the fundamental wave which is the oscillation signal of the original frequency but also from the crystal oscillator 41. Significant levels of harmonics have been generated, increasing the distortion in the distributed reference frequency signal. Therefore, the input terminals 11 and 12 of each PLL circuit are
When the supply is distributed to 1, 31, an increased unnecessary harmonic other than the fundamental wave is also inputted, and a malfunction in operation or an unexpected decrease may occur due to a difference in permissible standard of each PLL circuit. Absent.

However, in the present embodiment configured as described above, the external oscillation circuit 40 and the input terminal 11,
Low-pass filters 51, 52, 53
, And higher harmonics higher than the fundamental wave cannot pass through, and only the fundamental wave is input via the input terminals 11, 21, 31. This reference frequency signal is supplied to low-pass filters 51, 52, 5 provided for each PLL circuit.
3, the modulator 10, the tuner 20, and the PLL circuit of the IF block 30 are input. Of course, each of the low-pass filters 51, 52 and 53 corresponds to the input characteristic of each PLL circuit, and the reference frequency signal is distributed and supplied with the optimal input characteristic.

In the present embodiment, a so-called low-pass filter is used to prohibit the passage of a signal having a frequency higher than the fundamental wave, but a band-pass filter for prohibiting the passage of a signal having a frequency lower than the fundamental wave. May be used. In this case, low-frequency noise and DC components can be removed, and harmonics can also be removed. As described above, a reference frequency signal using a quartz oscillator is distributed and supplied from the outside to a plurality of PLL circuits, thereby realizing a configuration that can be used substantially while sharing the quartz oscillator. On the other hand, FIGS. 2 to 4 further show an embodiment in which a PLL module in the PLL circuit is shared.

This embodiment is a tuner + modulator unit in which a tuner and a modulator are miniaturized and integrated in the same VCR, and is applicable to a 3IN1 unit and the like in which an IF unit is further added. As an example, the tuner module block 60 is configured by a lower heterodyne receiving system that receives a terrestrial wave or a CATV broadcast and outputs an IF signal by using a general US model as a model. The RF signal received from the external antenna is input to an RF amplifier 62 via an antenna filter 61, amplified, and input to a mixer 64 via a bandpass filter 63. The mixer 64 has a varicap 65 a
Also, the oscillation output of the local oscillator 65 whose tuning frequency can be changed is input, and the IF signal is output by the above-described lower heterodyne reception method.

On the other hand, the modulator module block 7
Reference numeral 0 denotes a local oscillator that modulates and mixes a video signal and an audio signal and outputs the signal as an RF signal of 3CH or 4CH on a carrier while changing the frequency of the carrier. 71 is used. Here, the video signal is input to the video modulator 74 via the clamp circuit 72 and the white clip circuit 73, and is subjected to so-called AM modulation. On the other hand, the audio signal
Is FM-modulated by the audio modulator 76 through the
/ A mixed. Further, the oscillation output of the local oscillator 71 described above is also input to the mixer 77, and the above-described RF
It is output as a signal. The oscillation frequency of the local oscillator 71 can be changed by the same varicap 71a as that of the local oscillator 65, and the oscillation frequency of the local oscillators 65 and 71 is controlled by the PLL module block 80. Supplying voltage.

The PLL module block 80 has a prescaler 81 whose input can be switched by a changeover switch SW1, and the local oscillator 65,
71, and 1 / N is set in advance so that the frequency can be divided by the programmable frequency divider 82.
Divided by Generally, tuner module block 6
The frequency of 0 is divided by 1/8, and the frequency of the modulator module block 70 is divided by 1/4. However, since it is shared here, the frequency is divided by 1/8 of the least common multiple.
The changeover switch SW1 selects the input of the programmable frequency divider 82, and constitutes an input selecting means.

The programmable frequency divider 82 has a latch circuit 8
It is composed of a down counter that can be preset by frequency division commands from 3a and 83b. Then, when a frequency division command of any one of the latch circuits 83a and 83b is input by the changeover switch SW2 synchronized with the changeover switch SW1, the frequency division command held by the latch circuits 83a and 83b is preset, and is preset. The oscillation output of the local oscillators 65 and 71 is further divided by performing down-counting according to the value.

The latch circuits 83a and 83b latch the frequency division command value obtained by serial-parallel conversion of the control data input by the shift register 84 via the bus controller 85. The latch circuit 83a is provided for the tuner module block 60. The frequency division command value is latched based on the reception frequency control data, and the latch circuit 83b latches the frequency division command value based on the oscillation frequency control data of the modulator module block 70. The bus controller 85 absorbs the format difference between the reception frequency control data and the oscillation frequency control data, and converts the data so that the shift register 84 can output an appropriate frequency division command value.
That is, the bus controller 85, the shift register 84, the latch circuits 83a and 83b, and the switch S
With W2, a frequency division command of the programmable frequency divider 82 is appropriately output, and these constitute frequency division command holding means.

The frequency division result of the programmable frequency divider 82 is input to the phase comparison circuits 86a and 86b via the changeover switch SW3 synchronized with the changeover switches SW1 and SW2. The divided output of the reference divider 88 for dividing the oscillation output of the oscillation circuit 87 by 512 or 1024 is also input. Each of the phase comparison circuits 86a and 86b detects a phase difference and a frequency difference between two inputs, and outputs a difference signal to the next-stage charge pumps 89a and 89b. This difference signal is output as a pulse signal, each of the charge pumps 89a, 89b is converted into a direct current according to the duty ratio, and is supplied as a voltage signal to the varicap 65a of the tuner module block 60, respectively.
Is applied to the varicap 71a of the modulator module block 70. In this case, the voltage signal performs feedback control of the oscillation frequency of each of the local oscillators 65 and 71 using the above-described frequency division result.
9a, 89b, the varicap 65a of the tuner module block 60 and the modulator module block 70
A feedback control circuit is constituted by the varicap 71a and the like. In this case, the changeover switch SW3 selects one of the frequency division results of the programmable frequency divider 82 and outputs the selected result to the phase comparison circuits 86a and 86b, thus constituting an output switching means.

An external reference frequency signal oscillated from the outside using a crystal oscillator is supplied to the internal oscillation circuit 87 via a low-pass filter 90, and the external reference frequency signal is similarly supplied to the low-pass filter. It is also supplied to the IF circuit through the respective circuits (not shown). Next, the operation of the present embodiment having the above configuration will be described. When tuning to a desired frequency by the tuner module block 60, the changeover switches SW1 to SW3 are connected to terminals a
Is switched to the side of. That is, the changeover switch SW1
Is switched to the output side of the local oscillator 65, the switch SW2 is switched to the latch circuit 83a, and the switch SW3 is switched to the phase comparison circuit 86a.

When the changeover switch SW2 is switched to the side of the latch circuit 83a, a frequency division command based on the reception frequency control data supplied via the IIC bus or the three wire bus is preset in the programmable frequency divider 82. . The received frequency control data is output by a system controller (not shown) via the IIC bus corresponding to the channel based on a channel switching operation by the user. On the other hand, since the changeover switch SW1 is switched to the output side of the local oscillator 65, the oscillation signal is input to the programmable frequency divider 82 via the prescaler 81, and the programmable frequency divider 82 The data is down-counted based on the data, and the frequency division result is supplied to the phase comparison circuit 86a via the changeover switch SW3.

On the other hand, the external reference frequency signal supplied from the outside is input to the internal oscillation circuit 87 after unnecessary harmonic components are removed through the low-pass filter 90, without causing the internal oscillation circuit 87 to malfunction. Oscillation is performed, and the oscillation signal is frequency-divided by 512 or 1024 by the reference frequency divider 88 and input to the phase comparison circuit 86a. Accordingly, the phase comparison circuit 86a compares the frequency-divided result of the stable frequency signal based on the oscillation of the crystal oscillator with the frequency-divided result based on the oscillation signal of the local oscillator 65, and obtains a difference signal representing the phase difference and the frequency difference. The charge pump 89
a. And the charge pump 89
a is a DC voltage signal based on the difference signal
a of the local oscillator 65 so as to eliminate the difference signal.
Feedback control of the oscillation frequency. As a result, a PLL is formed, and the oscillation frequency of the local oscillator 65 becomes a desired frequency and becomes extremely stable.

On the other hand, the RF output is set to 1CH by the setting operation.
Or 2CH, the oscillation frequency of the local oscillator 71 in the modulator module block 70 is determined,
A PLL is formed to keep this oscillation frequency constant. In this case, each of the changeover switches SW1 to SW3 is switched to the terminal b side. That is, the changeover switch SW1 is switched to the output side of the local oscillator 71,
The switch SW2 is switched to the latch circuit 83b, and the switch SW3 is switched to the phase comparison circuit 86b.

When the changeover switch SW2 is switched to the side of the latch circuit 83b, a frequency division command based on the oscillation frequency control data supplied via the IIC bus or the three wire bus is preset in the programmable frequency divider 82. . On the other hand, since the changeover switch SW1 has been switched to the output side of the local oscillator 71, its oscillation signal is supplied to the programmable frequency divider 8 via the prescaler 81.
2, the programmable frequency divider 82 counts down based on the above-mentioned oscillation frequency control data, and the frequency division result is output to the phase comparison circuit 86 via the changeover switch SW3.
b.

On the other hand, also in this case, the internal oscillation circuit 87 outputs an oscillation signal having a stable frequency based on the external reference frequency signal, and the oscillation signal is frequency-divided by the reference frequency divider 88 to generate a phase comparison circuit 86b. Has been entered. Therefore, the phase comparison circuit 86b also compares the frequency-divided result of the stable frequency signal based on the oscillation of the crystal oscillator with the frequency-divided result based on the oscillation signal of the local oscillator 71, and obtains a difference signal representing the phase difference and the frequency difference. Is output to the charge pump 89b. Then, the charge pump 89b supplies a DC voltage signal for feedback control to eliminate the same difference signal to the varicap 71a, and the oscillation frequency of the local oscillator 71 becomes the frequency of the above-described RF output channel, which is extremely stable.

That is, since a desired frequency dividing command can be preset to the programmable frequency divider 82,
Feedback control is possible so that the tuning frequency of the tuner module block 60 and the oscillation frequency of the modulator module block 70 are kept constant while being appropriately switched. Thus, the modulator 10 can be used like a VCR.
When a plurality of PLL circuits such as the tuner 20 and the IF block 30 are provided, by inputting a reference frequency signal supplied from outside through a low-pass filter, operation instability due to unnecessary harmonic components and the like can be prevented. A quartz oscillator or the like can be substantially shared, and the outputs of the local oscillators 65 and 71 to be input to the programmable frequency divider 82 are switched by the changeover switch SW1, and the bus controller 85, the shift register 84, the latch circuits 83a, Since the frequency division command is output to the programmable frequency divider 82 as appropriate by the switch 83b and the changeover switch SW2, the programmable frequency divider 82 can be shared by the PLL module blocks corresponding to a plurality of modules.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a VCR implemented by a PLL multifunction peripheral according to a first embodiment of the present invention.

FIG. 2 shows a tuner + which is another application example of the PLL composite device.
It is a block diagram of a tuner module block in a modulator unit.

FIG. 3 is a block diagram of a modulator module block in the tuner + modulator unit.

FIG. 4 shows P in the tuner + modulator unit.
It is a block diagram of LL module block.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Modulator 20 ... Tuner 30 ... IF block 40 ... External oscillation circuit 41 ... Crystal oscillator 42 ... Amplifier 51, 52, 53 ... Low-pass filter 60 ... Tuner module block 65 ... Local oscillator 65a ... Varicap 70 ... Modulator module block 71 ... Local oscillator 71a ... Varicap 80 ... PLL module block 81 ... Prescaler 82 ... Programmable frequency divider 83a, 83b ... Latch circuit 84 ... Shift register 85 ... Bus controller 86a, 86b ... Phase comparison circuit 87 ... Internal oscillation circuit 88 ... Reference Frequency divider 89a, 89b Charge pump 90 Low-pass filter SW1, SW2, SW3 Changeover switch

Claims (4)

[Claims] The present invention is characterized in that a reference frequency signal using an external quartz oscillator is supplied to a plurality of PLL circuits via a low-pass filter for removing harmonic components, and one quartz oscillator is shared. PLL composite device. 2. The PLL composite device according to claim 1, wherein said low-pass filter is constituted by a band-pass filter. 3. A plurality of modules each including a local oscillator, a programmable frequency divider for performing a desired frequency division on an oscillation output of each local oscillator, and a reference frequency signal using a crystal oscillator from the outside. An internal oscillation circuit that oscillates and outputs at a corresponding frequency; a phase comparison circuit that compares the phase of the frequency division result of the programmable frequency divider with the oscillation output of the internal oscillation circuit; and a comparison result of the phase comparison circuit. A PLL composite device comprising a feedback control circuit for performing feedback control of the oscillation frequency of each local oscillator, wherein the programmable frequency divider is shared by a plurality of modules. Frequency division command holding means for outputting a frequency division command to the programmable frequency divider corresponding to the module to be used , PLL composite device, characterized in that selects the output of the local oscillator in response to a module that uses comprising an input selecting means for the input of the programmable frequency divider. 4. The PLL composite device according to claim 3, further comprising output switching means for switching the frequency division result of said programmable frequency divider to said phase comparison circuit corresponding to a module to be used and outputting the result. A PLL composite device characterized by the above-mentioned.