JPH0685700A - Pll frequency synthesizer tuner - Google Patents

Pll frequency synthesizer tuner

Info

Publication number
JPH0685700A
JPH0685700A JP4234393A JP23439392A JPH0685700A JP H0685700 A JPH0685700 A JP H0685700A JP 4234393 A JP4234393 A JP 4234393A JP 23439392 A JP23439392 A JP 23439392A JP H0685700 A JPH0685700 A JP H0685700A
Authority
JP
Japan
Prior art keywords
circuit
pll
connected
mini
local oscillation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4234393A
Other languages
Japanese (ja)
Inventor
Masaki Bessho
Hitoshi Hirano
正樹 別所
人司 平野
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP4234393A priority Critical patent/JPH0685700A/en
Publication of JPH0685700A publication Critical patent/JPH0685700A/en
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a PLL frequency synthesizer tuner in which a problem to fluctuate an oscillation frequency due to the capacity change of a capacitor which comprises a loop filter on a PLL circuit by a piezoelectric effect in oscillation can be solved and turbulence can be prevented from occurring in the oscillation. CONSTITUTION:This tuner is comprised in such a way that the PLL circuit 11 is comprised on a minimodule substrate 20, and also, it is studded with a master substrate 19. Therefore, oscillation in the excitation applied to the tuner can be absorbed by the master substrate first. Thence, it is transmitted to the minimodule substrate 20 which comprises the PLL circuit 11. The transmission of the oscillation can be suppressed by employing such transmission route of two steps. In other words, the oscillation applied to the capacitor which comprises the loop filter of the PLL circuit can be suppressed, which prevents the capacity change due to the piezoelectric effect from occurring and ripple from occurring on a VT voltage. Therefore, no fluctuation of the oscillation frequency occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer tuner used for selecting a reception frequency.

[0002]

2. Description of the Related Art A conventional PLL frequency synthesizer tuner will be described below.

As a conventional PLL frequency synthesizer tuner, for example, the one disclosed in Japanese Patent Laid-Open No. 3-82937 has been known. Conventional PL according to the following drawings
The L frequency synthesizer tuner will be described.

FIG. 5 is a block diagram of a conventional PLL frequency synthesizer tuner. In FIG.
Reference numeral 1a is an input terminal, and the high frequency amplifier circuit 2a is connected to the input terminal 1a. This high frequency amplifier circuit 2a
The mixer circuit 3a, to which one input is connected, is connected to the output of, and the local oscillation circuit 10a is connected to the other input of this mixing circuit 3a. A PLL circuit 11a is connected to the local oscillator circuit 10a.
A data input terminal 12a is connected to.

A bandpass filter 4a is connected to the output of the mixing circuit 3a, and a first intermediate frequency amplifier circuit 5a is connected to the output of the bandpass filter 4a.
A mixing circuit 6a having one input connected to the output of the first intermediate frequency amplifier circuit 5a is connected to the mixing circuit 6a.
A local oscillation circuit 17a is connected to the other input of the. A second intermediate frequency amplifier circuit 7a is connected to the other output of the mixing circuit 6a, and the second intermediate frequency amplifier circuit 7a is connected to the second intermediate frequency amplifier circuit 7a.
A bandpass filter 8a is connected to the output of the.
An output terminal 9a is connected to the output of the bandpass filter 8a.

Here, the PLL circuit 11a will be described in detail. That is, 13a is a PLL synthesizer IC, which is connected to the crystal oscillator 16a, the data input terminal 12a and the local oscillation circuit 10a, and its output is connected to the local oscillation circuit 10a via the loop filter 14a.

Further, the high frequency circuit section 18a and the PLL circuit 1
1a and 1a are arranged apart from each other on the same substrate plane (not shown) and are connected by a wiring pattern formed on the substrate.

The operation will be described below. The high-frequency signal applied to the input terminal 1a shown in FIG. 5 is amplified by the high-frequency amplifier circuit 2a and then mixed by the mixing circuit 3a.
It is mixed with the oscillation frequency signal of a to become the first intermediate frequency of 612.75 MHz. After that, it passes through the band pass filter 4a and is amplified by the first intermediate frequency amplifying circuit 5a, and the mixing circuit 6a further receives 554 MHz from the fixed local oscillation circuit 17a.
Is mixed with the oscillating frequency signal of and converted to a second intermediate frequency of 58.75 MHz. After this, the second intermediate frequency amplifier circuit 7
It is amplified by a and is output to the output terminal 9a through the bandpass filter 8a.

The oscillation frequency signal of the local oscillator circuit 10a is
The desired channel can be received by being controlled by a tuning voltage (hereinafter referred to as VT voltage) output from the PLL circuit 11a based on the tuning data input to the data input terminal 12a.

[0010]

However, in the above-mentioned conventional configuration, the high frequency circuit section 18a and the PLL circuit 11a are provided.
Since they are arranged on the same substrate, the multilayer chip capacitor 15a used for the loop filter 14a forming the PLL circuit 11a causes a capacitance variation of the capacitor 15a due to the piezoelectric effect when the tuner is vibrated. As a result, the loop filter 14a becomes the PLL synthesizer IC.
The pulse output from 13a is integrated to generate the VT voltage. The VT voltage is added to the capacitor 15
A ripple is generated due to the capacitance change of a, and the local oscillation circuit 10
Since the oscillation frequency of a fluctuates under the influence of this ripple,
As a result, for example, there is a problem in that a white line-like disorder is generated on the TV screen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL frequency synthesizer tuner which does not disturb the screen during vibration.

[0012]

To achieve this object, a PLL frequency synthesizer tuner of the present invention is a PL frequency synthesizer.
The L circuit is configured on the mini-module board, and the mini-module is implanted on the parent board.

[0013]

With this configuration, the PLL circuit that is most susceptible to the adverse effects of vibration is independently formed on the mini-module board, and the mini-module board is implanted on the parent board. Therefore, the vibration when the tuner is excited is first absorbed by the parent board. Then, the data is transmitted to the mini module board that constitutes the PLL circuit. Vibration transmission is suppressed by this two-stage transmission path. That is, since the vibration to the capacitor that constitutes the loop filter of the PLL circuit is suppressed, no ripple occurs in the VT voltage. Therefore, the oscillation frequency of the local oscillation circuit does not fluctuate, and as a conclusion, the white line-shaped disturbance does not occur on the screen.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an electric circuit of a PLL frequency synthesizer tuner according to an embodiment of the present invention, and FIG. 2 is a mounting plan view thereof. 3 and 4 are a front view and a back view of a mini-module board constituting a PLL circuit of a PLL frequency synthesizer tuner according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is an input terminal, and a high frequency amplifier circuit 2 is connected to the input terminal 1. The mixing circuit 3 having one input connected to the output of the high frequency amplifier circuit 2 is connected to the other input of the local oscillation circuit 10. A PLL circuit 11 is connected to the local oscillator circuit 10,
A data input terminal 12 is connected to the LL circuit 11. A bandpass filter 4 is connected to the output of the mixing circuit 3, and a first intermediate frequency amplifier circuit 5 is connected to the output of the bandpass filter 4. The output of the first intermediate frequency amplifier circuit 5 is connected to the mixing circuit 6 having one input connected thereto, and the other input of the mixing circuit 6 is connected to the local oscillation circuit 17. A second intermediate frequency amplifier circuit 7 is connected to the output of the mixing circuit 6, and a bandpass filter 8 is connected to the output of the second intermediate frequency amplifier circuit 7. An output terminal 9 is connected to the output of the bandpass filter 8.

Reference numeral 13 denotes a PLL synthesizer IC, which is connected to the crystal oscillator 16, the data input terminal 12 and the local oscillation circuit 10, and the output thereof is connected to the local oscillation circuit 10 through the loop filter 14. .

Here, the entire PLL circuit 11 is constructed in the mini-module board 20 as shown in FIGS. 3 and 4, and the PLL circuit 11 is planted at a substantially right angle in the main board 19 as shown in FIG. There is. Further, the capacitor 15 that constitutes the loop filter 14 of the PLL circuit 11 is mounted on the opposite side of the mini module substrate 20 that faces the planting side 20a, as shown in FIG. Reference numeral 20b denotes a terminal laid on the planting side 20a, and the parent board 19 is provided via this terminal 20b.
And is electrically connected by soldering. In addition, the mini-module board 20 includes a local oscillator circuit 10 as shown in FIG.
And the data input terminal 12 are arranged and planted at the shortest distance, and the local oscillator circuit 10 is connected to the metal shield plate 22.
Via the above, it is planted in an independent metal compartment 23. Furthermore, the mini-module board 20 is composed of a double-sided through-hole board 21.

The operation of the PLL frequency synthesizer tuner configured as described above will be described below.

The high frequency signal applied to the input terminal 1 shown in FIG. 1 is amplified by the high frequency amplifier circuit 2 and mixed by the mixing circuit 3 with the oscillation frequency signal of the local oscillation circuit 10.
This is the first intermediate frequency of 2.75 MHz. After that, the signal is amplified by the first intermediate frequency amplifier circuit 5 through the band pass filter 4, and the mixing circuit 6 is mixed with the 554 MHz oscillation frequency signal from the fixed local oscillation circuit 17 to obtain 58.75 M.
Converted to the second intermediate frequency in Hz. After that, the signal is amplified by the second intermediate frequency amplifier circuit 7 and output to the output terminal 9 through the bandpass filter 8.

On the other hand, the oscillation frequency signal of the local oscillator circuit 10 is based on the tuning data input to the data input terminal 12, the PLL circuit 1 formed in the mini module board 20.
It is controlled by the VT voltage output from 1 so that the desired channel can be received.

As described above, according to this embodiment, the PLL circuit 11 is formed on the mini module board 20, and
By implanting in the parent board 19, it is possible to suppress the vibration transmission to the capacitor 15 used in the loop filter 14 when the tuner is vibrated, and to prevent the capacitance variation of the capacitor 15 due to the piezoelectric effect. . Therefore, the ripple is not generated in the VT voltage and the oscillation frequency signal is not changed, so that it is possible to prevent the screen from being disturbed.

Further, since the capacitor 15 is mounted on the opposite side of the mini-module board 20 facing the planting side 20a, the vibration transmission path is further sufficiently secured, so that the vibration transmission to the capacitor 15 is small. Ripple is not further generated in the VT voltage, and the oscillation frequency signal does not change.

Further, since the mini module board 20 is implanted in the parent board 19 at the shortest distance between the local oscillation circuit 10 and the data input terminal 12, the oscillation frequency signal of the local oscillation circuit 10 is sufficiently supplied to the PLL synthesizer IC 13. Since the injection can be performed stably and there is no transmission loss of the VT voltage, the oscillation frequency signal of the local oscillation circuit 10 can be controlled extremely stably. Moreover, since the local oscillation circuit 10, the PLL circuit 11 and the data input terminal 12 can be coupled with the shortest wiring pattern, the digital pulse of the tuning data inputted from the data input terminal 12 is superposedly coupled with the wiring pattern which supplies the VT voltage. There is nothing. Therefore, the ripple is not generated in the VT voltage and the oscillation frequency signal is not changed, so that it is possible to prevent the screen from being disturbed.

Furthermore, since the mini-module board 20 constituting the PLL circuit 11 is embedded in the independent compartment 23 made of metal via the local oscillation circuit 10 and the shield plate 22 made of metal. , The reference frequency generated by the PLL synthesizer IC 13 and the fundamental wave of the clock frequency of the crystal oscillator 16 forming the PLL circuit 11 can be prevented from wrapping around and overlapping with the oscillation frequency signal of the local oscillation circuit 10. Therefore, spurious interference can be prevented and the C / N characteristic of the local oscillation circuit 10 can be improved.

Further, since the PLL circuit 11 formed in the mini module board 20 uses the double-sided through-hole board 21, it is possible to realize miniaturization and a miniaturization of the PLL frequency synthesizer tuner.

[0026]

As described above, according to the present invention, the PLL circuit which is most susceptible to the adverse effects of vibration is independently formed on the mini-module board, and the mini-module board is implanted in the parent board. ing. Therefore, the vibration when the tuner is excited is first absorbed by the parent board. Then, the data is transmitted to the mini module board that constitutes the PLL circuit. Vibration transmission is suppressed by this two-stage transmission path. That is, since the vibration to the capacitor that constitutes the loop filter of the PLL circuit is suppressed, no ripple occurs in the VT voltage. Therefore, the oscillation frequency of the local oscillator does not change, and in conclusion,
There is an effect that no white line-like disturbance is generated on the screen.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL frequency synthesizer tuner according to an embodiment of the present invention.

[Fig. 2] The same mounting plan view

FIG. 3 is a front view of a PLL circuit mini-module board according to an embodiment of the present invention.

[Figure 4] Rear view of the same

FIG. 5 is a block diagram of a conventional PLL frequency synthesizer tuner.

[Explanation of symbols]

 1 Input Terminal 2 High Frequency Amplifier Circuit 3 Mixing Circuit 5 First Intermediate Frequency Amplifier Circuit 7 Second Intermediate Frequency Amplifier Circuit 9 Output Terminal 10 Local Oscillation Circuit 11 PLL Circuit 12 Data Input Terminal 19 Parent Board 20 Mini Module Board

Claims (5)

[Claims]
1. An input terminal, a high frequency amplifier circuit connected to the input terminal, a mixing circuit having one input connected to the output of the high frequency amplifier circuit, and an intermediate frequency connected to the output of the mixing circuit. An amplifier circuit, an output terminal connected to the output of the intermediate frequency amplifier circuit, a local oscillator circuit connected to the other input of the mixing circuit and supplying a local oscillation signal to the mixing circuit, and the local oscillation circuit A PLL circuit that is connected and controls the oscillation frequency of this local oscillation circuit, and this P
A data input terminal for inputting tuning data to the PLL circuit is connected to the LL circuit, the PLL circuit is configured on a mini module board, and the mini module is connected to the high frequency amplifier circuit, the mixing circuit, and the intermediate circuit. A PLL frequency synthesizer tuner embedded in a main board on which at least one of a frequency amplification circuit and a local oscillation circuit is mounted.
2. The PLL frequency synthesizer tuner according to claim 1, wherein the capacitor forming the loop filter of the PLL circuit is mounted on the side of the mini module substrate opposite to the planted side.
3. The PLL frequency synthesizer tuner according to claim 1 or 2, wherein the mini-module board is installed on a main board between the data input terminal and the local oscillation circuit.
4. The mini-module board constituting the PLL circuit is planted in a compartment independent from the compartment in which the local oscillation circuit is constituted via a shield plate.
Alternatively, the PLL frequency synthesizer tuner according to claim 3.
5. The PLL frequency synthesizer tuner according to claim 1, wherein the mini-module board is a double-sided through-hole board.
JP4234393A 1992-09-02 1992-09-02 Pll frequency synthesizer tuner Granted JPH0685700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4234393A JPH0685700A (en) 1992-09-02 1992-09-02 Pll frequency synthesizer tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4234393A JPH0685700A (en) 1992-09-02 1992-09-02 Pll frequency synthesizer tuner

Publications (1)

Publication Number Publication Date
JPH0685700A true JPH0685700A (en) 1994-03-25

Family

ID=16970298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4234393A Granted JPH0685700A (en) 1992-09-02 1992-09-02 Pll frequency synthesizer tuner

Country Status (1)

Country Link
JP (1) JPH0685700A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400419B1 (en) 1997-10-13 2002-06-04 Alps Electric Co., Ltd. Television tuner system
US6859502B1 (en) 1999-01-19 2005-02-22 Matsushita Electric Industrial Co., Ltd. Transmitting and receiving apparatus capable of the suppression of the microphonic noise in digital transmission system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61150410A (en) * 1984-12-24 1986-07-09 Sony Corp Tuner device
JPS62131633A (en) * 1985-12-04 1987-06-13 Hitachi Ltd Reception equipment
JPH02159127A (en) * 1988-12-12 1990-06-19 Matsushita Electric Ind Co Ltd High frequency circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61150410A (en) * 1984-12-24 1986-07-09 Sony Corp Tuner device
JPS62131633A (en) * 1985-12-04 1987-06-13 Hitachi Ltd Reception equipment
JPH02159127A (en) * 1988-12-12 1990-06-19 Matsushita Electric Ind Co Ltd High frequency circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400419B1 (en) 1997-10-13 2002-06-04 Alps Electric Co., Ltd. Television tuner system
US6859502B1 (en) 1999-01-19 2005-02-22 Matsushita Electric Industrial Co., Ltd. Transmitting and receiving apparatus capable of the suppression of the microphonic noise in digital transmission system
US7206371B2 (en) 1999-01-19 2007-04-17 Matsushita Electric Industrial Co., Ltd. Transmitting and receiving apparatus capable of the suppression of the microphonic noise in digital transmission system

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