JPH08130448A - Variable delay circuit - Google Patents

Abstract

PURPOSE: To relieve a defective product by speedily adjusting delay time after the completion of a wafer by adjusting the delay time by switching a control signal to be supplied from a permanent memory means and changing the number of stages of an inverter for delay. CONSTITUTION: A control signal ϕC is switched by cutting off a fuse inside a permanent memory means 6 by irradiating it with a laser. When the control signal ϕC from the means 6 is 'L', a switch means 2 is turned on, delay elements 1 and 3 are serially connected, an input signal ϕin is delayed by the elements 1 and 3, and the long delay time is provided from an AND gate 5. On the other hand, when the control signal ϕC is 'H', the switch means 2 is turned off, the elements 1 and 3 are disconnected and a switch means 4 is turned on, so that the input to the element 3 can be fixed at a power supply potential VCC and the output of the element 3 can become 'H'. Therefore, since the input signal ϕin is delayed by only the element 1 and outputted from the AND gate 5, the short delay time is provided. Thus, the yield of an integrated circuit is improved by speedily adjusting the delay time after the completion of the wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit incorporated in a semiconductor integrated circuit such as a DRAM, and more particularly to a variable delay circuit capable of adjusting a delay time after completion of a wafer.

[0002]

2. Description of the Related Art A delay circuit is a circuit that delays a signal for a fixed time and is widely used in semiconductor integrated circuits such as DRAM. For example, when reading data from a DRAM, a row address strobe signal * RA
The selected word line rises due to the fall of S, and the data stored from the selected memory cell is output to the pair of bit lines as a minute difference voltage. Then, the difference voltage is amplified by the sense amplifier and then transferred to the data line. However, if the sense amplifier operates before the above-mentioned difference voltage is sufficiently generated, indeterminate data is amplified, which causes erroneous reading. Therefore, a delay circuit is used to secure a constant delay time from the rise of the word line to the activation of the sense amplifier.

Conventionally, a general delay circuit used in a semiconductor integrated circuit has a plurality of inverters connected in series as shown in FIG. The delay time can be freely set depending on the number of inverter stages, but the design value and the actual delay time may deviate due to variations in device parameters generated in the semiconductor process. Therefore, as shown in the figure, the delay time is adjusted by changing the metal mask and switching the number of inverter stages.

[0004]

However, in the conventional delay circuit, in order to adjust the delay time, it is necessary to change the metal mask and go through the manufacturing process after the metal process again, which requires a quick adjustment. I couldn't do it. In addition, it is impossible to relieve a defective product that has been completed once and secure a yield.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a variable delay circuit capable of promptly adjusting a delay time after completion of a wafer and relieving a defective product.

[0006]

As shown in FIG. 1, a variable delay circuit according to the present invention comprises a first delay element (1) formed by connecting an even number of inverters in series, and the first delay element. An input of the second delay element (3), which is connected in series with the element (1) via the first switch means (2), and is formed by connecting even-numbered-stage inverters in series, and the second delay element. Controlling the first and second switch means, and an AND gate (5) to which outputs of the first and second delay elements are input. A permanent memory means (6) for supplying a signal φc for

Further, the permanent memory means (6) switches the control signal φc by cutting the fuse as shown in FIG. 3, for example.

[0008]

According to the variable delay circuit of the present invention, the first switch means (2) is turned on when the control signal φc supplied from the permanent memory means (6) is at low level (hereinafter referred to as L level). Then, the first delay element (1) and the second delay element (3) are connected in series. This allows
Since the input signal φin is delayed by the first delay element (1) and the second delay element (3) and output from the AND gate (6), a long delay time tDA is obtained as shown in FIG. .

On the other hand, the control signal φc has a high level (hereinafter,
It is called H level. ), The first switch means (2)
Is turned off, the first delay element (1) and the second delay element (3) are separated, and the second switch means (4) is turned on, so that the second delay element (3) is turned on. Is fixed to the power supply potential Vcc, and the output of the second delay element (3) becomes H level. As a result, the input signal φin is delayed only by the first delay element (1) and output from the AND gate (6), so that a short delay time tDB is obtained as shown in FIG. The control signal φc can be switched by, for example, cutting the fuse of the permanent memory means (6). Therefore, according to the present invention, it is possible to provide a variable delay circuit capable of quickly adjusting the delay time after completion of a wafer and relieving a defective product.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a variable delay circuit according to the present invention will be described below in detail with reference to FIGS. As shown in FIG. 1, the variable delay circuit of the present embodiment includes a first delay element (1) formed by connecting inverters in even stages in series,
The first delay element (1) and the first switch means (2)
A second delay element (3) connected in series via an even number of inverters in series, and a second switch means for fixing the input of the second delay element to the power supply potential Vcc ( 4), an AND gate (5) to which outputs of the first and second delay elements are input, and a permanent memory means (6) for supplying a signal φc for controlling the first and second switch means. It is equipped with.

The first switch means (2) is a CMOS controlled by the control signal φc and its inverted signal * φc.
Type transmission gate, and the second switch means (4) is a P-channel type MOS transistor controlled by an inverted signal * φc. The permanent memory means (6) is a programmable permanent memory that supplies the control signal φc, and can be configured by using, for example, a nonvolatile memory system or a fuse system used in a redundant address circuit of DRAM. An example of the circuit configuration of the permanent memory means (6) is as shown in FIG.
P through a fuse (10) made of a polysilicon layer or the like
A channel type MOS transistor (11) and an N channel type MOS transistor (12) are connected in series, and a P channel type MOS transistor (11) and a fuse (10) are connected.
The control signal φc is taken out from the connection point A with the inverters (13) and (14). In addition, the control signal φc
P-channel type MOS for level retention to stabilize the
A transistor (15) is provided at the connection point A. P
Control signals φA and φB are input to the gates of the channel type MOS transistor (11) and the N channel type MOS transistor (12), respectively. In the case of DRAM, the control signals φA and φB can be generated by delaying the row address strobe signal * RAS.

Next, the operation of the variable delay circuit will be described. Control signal φc supplied from the permanent memory means (6)
Is at the L level, the first switch means (2) is turned on, and the first delay element (1) and the second delay element (3) are connected in series. As a result, the input signal φ
in is the first delay element (1) and the second delay element (3)
Since it is delayed by and output from the AND gate (5),
As shown in FIG. 2, a long delay time tDA is obtained.

On the other hand, when the control signal φc is at the H level, the first switch means (2) is turned off and the first delay element (1) and the second delay element (3) are separated from each other, Moreover, since the second switch means (4) is turned on, the input of the second delay element (3) is fixed to the power supply potential Vcc, and the output of the second delay element (3) becomes H level. As a result, the input signal φin is delayed only by the first delay element (1) and output from the AND gate (5), so that a short delay time tDB is obtained as shown in FIG.

The switching of the control signal φc can be easily performed by cutting the fuse (10) of the permanent memory means (6) shown in FIG. 3 by laser irradiation or the like. The operation of the permanent memory means (6) will be described with reference to FIG. Low address strobe signal * RAS
Is at the H level, .phi.A and .phi.B are at the L level, and the connection point A is precharged to the potential Vcc. When the low address strobe signal * RAS becomes L level, φA and φB rise to H level based on this, the P channel type MOS transistor (11) is turned off and the N channel type MOS transistor (12) is turned on. Become. As a result, the control signal φc becomes L level when the fuse (10) is not blown, and the control signal φc maintains H level when the fuse (10) is blown. Therefore, in the variable delay circuit of this embodiment, the delay time is tDA in the initial state, but the delay time can be reduced to tDB by cutting the fuse (10). By inverting the control signal φc, the delay time in the initial state can be set to tDB, and the delay time after the fuse (10) is blown can be increased to tDA. Thus, according to the present invention, the delay time can be quickly adjusted after the completion of the wafer, and the defective product can be relieved.

Although the AND gate (5) is used as the logic gate in the above embodiment, the present invention is not limited to this, and it is also possible to use an OR gate or the like.

[0016]

As described above, according to the variable delay circuit of the present invention, the control signal φc supplied from the permanent memory means (6) is switched by cutting the fuse (10) to change the number of stages of the delay inverter. Since the delay time is adjusted by doing so, it is possible to quickly adjust the delay time after the completion of the wafer, which can contribute to the improvement of the yield of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a variable delay circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the variable delay circuit according to the exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating permanent memory means.

FIG. 4 is a timing diagram illustrating the operation of the permanent memory means.

FIG. 5 is a circuit diagram illustrating a variable delay circuit according to a conventional example.

[Explanation of symbols]

 (1) First delay element (2) First switch means (3) Second delay element (4) Second switch means (5) AND gate (6) Permanent memory means (10) Fuse (11) P-channel MOS transistor (12) N-channel MOS transistor (13) (14) Inverter (15) P-channel MOS transistor

Claims (2)

[Claims] 1. A first delay element formed by connecting a plurality of inverters in series, a second delay element connected in series via the first delay element and a first switch means, and Second switch means for fixing the input of the second delay element to a constant potential, a logic gate to which outputs of the first and second delay elements are input, and control of the first and second switch means And a permanent memory means for supplying a signal for controlling the variable delay circuit. 2. The variable delay circuit according to claim 1, wherein the permanent memory means switches the control signal by blowing a fuse.