JPH08130447A - Variable delay circuit - Google Patents

Abstract

PURPOSE: To provide a sufficient variable quantity by securing an amplitude and starting time required for the delay circuit by connecting an output buffer between a logic circuit and the first input terminal of a differential gate and connecting a capacitor through an external terminal to the output of this buffer. CONSTITUTION: The output of a logic circuit 10 is inputted to an output buffer 1, and that output is inputted to a non-inverted input terminal 3A of a differential gate 3. Besides, it is connected through an external terminal A to a capacitor 4, and the output of a D/A converter 2 is inputted to an inverted input terminal 3B. Since the amplitude of the signal of the logic circuit 10 inputted to the buffer 1 gets larger than that of an internal gate and the starting time of the buffer 1 is longer in comparison with that of the internal gate, the range of an output voltage by the control signal of the D/A converter 2 can sufficiently widely be secured even while considering a noise margin, and the delay time can be secured longer than the case of the internal gate. Further, the capacitor 4 is connected through the external terminal A, the starting time is made longer, and the delay amount can be further widened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit which obtains a sufficient delay amount when the variable delay circuit is constructed inside a gate array.

[0002]

2. Description of the Related Art Next, FIG. 2 shows the structure of a variable delay circuit according to the prior art. In FIG. 2, 2 is a D / A converter, 10 is a logic circuit, and 11 and 12 are differential gates. In FIG. 2, the logic circuit 10 outputs signals having "H" level and "L" level. The differential gate 11 inputs the output of the logic circuit 10 to the input terminal 11A and outputs the output of the D / A converter 2 to the input terminal 1A.
Enter in 1B. The differential gate 12 inputs the output of the differential gate 11 into the input terminal 12A and inputs the output of the D / A converter 2 into the input terminal 12B.

The differential gates 11 and 12 have an inverting input terminal and a non-inverting input terminal, and output a signal when the input level from each terminal is inverted. In FIG. 2, the output of the logic circuit 10 is connected to the non-inverting input terminal 11A of the differential gate 11.
Input to the inverting input terminal 11B of the output of the D / A converter 2.
Are typing in. By adjusting the level of the D / A converter 2 between the “H” level and the “L” level of the logic circuit 10 by the control signal, the delay time of the output of the differential gate 11 changes.

That is, in the case of the rising edge of the output of the logic circuit 10, the delay amount increases as it approaches the high level. Therefore, the delay amount can be changed programmable by the control signal at the input of the D / A converter 2. .

FIG. 2 shows an example in which two differential gates are connected in series to obtain a necessary delay time. In the configuration shown in FIG. 2, the delay amount of the signal is determined by the amplitude of the delayed signal and the rise time.

[0006]

Generally, when a variable delay circuit is constructed by a gate array, the internal gate has a small amplitude and a fast rise time because of low power consumption and high speed. The delay amount is very narrow, and the output voltage range of the DAC that controls the delay amount is extremely narrow, and it is very difficult to secure the delay amount. Therefore, several stages of differential gates are connected in series to obtain the required variable amount. However, the delay time of the internal gate of the gate array varies depending on the product, and even if the delay amount of the input signal can be secured, the delay amount of the delay circuit itself becomes large due to the large number of stages of operation gates, and the actual There is a problem that the amount of delay is reduced.

The present invention provides a variable delay circuit which secures a necessary amplitude and rise time for a delay circuit by using an output buffer and obtains a sufficient variable amount even if the skew adjusting circuit is composed of a gate array. To aim.

[0008]

To achieve this object, the present invention relates to a logic circuit 10 for generating a waveform, an output of the logic circuit 10 is connected to a first input terminal 3A, and an output voltage is controlled by a control signal. Is provided with a differential gate 3 for connecting the output of the D / A converter 2 to the second input terminal 3B. The differential gate 3 delays the waveform of the logic circuit 10 by the voltage of the D / A converter 2. In the variable delay circuit that outputs the output, the output buffer 1 is connected between the logic circuit 10 and the first input terminal 3A of the differential gate 3. Further, the capacitor 4 is connected to the output of the output buffer 1 via the external terminal A.

[0009]

The structure of the variable delay circuit according to the present invention is shown in FIG. In FIG. 1, 1 is an output buffer, 3 is a differential gate,
Reference numeral 4 is a capacitor, and the others are the same as those in FIG. That is, the output of the logic circuit 10 is first input to the output buffer 1. The output of the output buffer 1 is input to the non-inverting input terminal 3A of the differential gate 3 and connected to the capacitor 4 via the external terminal A, and the output of the D / A converter 2 is input to the inverting input terminal 3B. .

Next, the operation of the present invention will be described with reference to FIG. In FIG. 1, the signal of the logic circuit 10 input to the output buffer 1 has an amplitude larger than that of the internal gate. Further, since the rise time of the output buffer 1 is slower than that of the internal gate, the output voltage range of the control signal of the D / A converter 2 can be secured sufficiently large even if the noise margin is taken into consideration, and the delay time is reduced. More can be taken than with internal gates. Further, by using the output buffer 1, the capacitor 4 can be connected via the external terminal A. By delaying the rise time by the capacitor 4, the delay amount is further expanded.

Next, FIG. 3 shows a comparison diagram of the concrete waveforms of FIG. 1 and FIG. In FIG. 3, the vertical axis represents voltage and the horizontal axis represents time. 3A is the input waveform of the differential gate 11 of FIG. 2, and A is the output waveform of the output buffer 1 of FIG. In FIG. 3, the waveforms a and i both rise from the voltage V ₀ at time T ₀ , but the waveform a is shown in the output buffer 1 of FIG.
Therefore, as compared with the waveform a, the rising of the waveform is slow and the amplitude is large.

Considering the noise margin, the voltage range of the D / A converter 2 effective for the variable delay is the range of the voltages V _{1 to} V ₂ in the waveform of the output of FIG. The output waveform B is in the range of voltages V _{1 to} V ₃ . That is,
As shown in FIG. 3, the delay time of the output that varies according to the output voltage of the D / A converter 2 is the maximum delay amount per differential gate stage according to the configuration of FIG. 2 between time t _{0 and} time t ₁ . Yes,
The maximum delay amount according to the configuration of FIG. 1 is between time t _{0 and} t ₂ . Further, when the capacitor 4 is connected, the rising edge of the output waveform of the output buffer becomes slower and the maximum delay amount becomes larger.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS For example, when the circuit shown in FIG. 1 is composed of an ECL gate array having the following specifications, a rise time of 200 ps (20% to 80%) and an output amplitude of 0.
In contrast to 5V _pp , when output buffer 1 is used, the rise time is 650ps (20% to 80%) and the output amplitude is 1V.
It becomes _pp .

Here, assuming that the noise margin is 0.2 V above and below, the output range of the DAC 2 is 0.1 when the internal gate is used.
Output buffer 1 while the maximum delay amount at V is 66 ps
When is used, the output range of the DAC2 is 0.6 V and the maximum delay amount is 650 ps. Furthermore, when the capacitor 4 is connected and the capacitor 4 is set to 10 pF, the rise time becomes 650 ps → about 850 ps, and the maximum delay amount is 850 ps.

[0015]

According to the present invention, when the variable delay circuit is constructed in the gate array, the delayed signal is input to the differential gate through the output buffer, so that the amplitude and the rising edge required for the delay circuit are increased. Time can be secured, and a sufficient delay amount can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a variable delay circuit according to the present invention.

FIG. 2 is a configuration diagram of a variable delay circuit according to a conventional technique.

FIG. 3 is a comparison diagram of specific waveforms in FIGS. 1 and 2.

[Explanation of symbols]

 1 Output Buffer 2 D / A Converter 3 Differential Gate 10 Logic Circuit 11 · 12 Differential Gate

Claims (2)

[Claims] 1. A logic circuit (10) for generating a waveform, and a D / A converter for connecting the output of the logic circuit (10) to a first input terminal (3A) and controlling the output voltage by a control signal ( It has a differential gate (3) that connects the output of 2) to the second input terminal (3B), and the differential gate (3) is a logic circuit by the voltage of the D / A converter (2).
In the variable delay circuit that delays and outputs the waveform of (10), connect the output buffer (1) between the logic circuit (10) and the first input terminal (3A) of the differential gate (3). The characteristic variable delay circuit. 2. The variable delay circuit according to claim 1, wherein a capacitor (4) is connected to the output of the output buffer (1) via an external terminal A.