CN113986043B - Touch control and display driving integrated chip, driving method thereof and display device - Google Patents

Abstract

The invention relates to the technical field of display and provides a touch control and display driving integrated chip, a driving method thereof and a display device, wherein the integrated chip comprises a phase-change memory and a control circuit, the phase-change memory is connected with a flash memory, and can be started under the signal action of a first enabling signal end and cut into a reading mode under the signal action of a second enabling signal end; the control circuit includes: the input end of the first D trigger is connected with a first control signal end, and the clock control end is connected with a second control signal end; the first logic circuit is used for inputting a first enabling signal to a first enabling signal end of the phase-change memory according to signals of a positive output end and a second control signal end of the first D trigger; the second logic circuit is used for inputting a second enabling signal to a second enabling signal end of the phase-change memory according to the signal of the non-inverting output end of the first D trigger. The integrated chip has better stability.

Description

Touch control and display driving integrated chip, driving method thereof and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a touch control and display driving integrated chip, a driving method thereof and a display device.

Background

In the related art, TDDI IC (Touch AND DISPLAY DRIVER Integration IC, touch and display driver integrated chip) needs to plug in a Flash (Flash memory), and PRAM (phase change memory) in TDDI IC needs to read or write TDDI IC firmware information needed by the driver from the Flash. The start of the PRAM needs to be driven by a first enable signal, and the switching of the PRAM read mode or the write mode needs to be driven by a second enable signal, for example, the PRAM may enter the read mode when both the first enable signal and the second enable signal are low. However, since the generation circuits of the first enable signal and the second enable signal have delay, when the PRAM should be in the read mode, the first enable signal and the second enable signal received by the PRAM cannot drive the PRAM to read the firmware information on Flash.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

According to one aspect of the present disclosure, there is provided a touch and display driving integrated chip including: the phase-change memory comprises a first enabling signal end and a second enabling signal end, the phase-change memory can be started under the signal action of the first enabling signal end and can be switched into a reading mode under the signal action of the second enabling signal end, and in the reading mode, the phase-change memory can read firmware information in the flash memory. A control circuit, comprising: the input end of the first D trigger is connected with a first control signal end, and the clock control end is connected with a second control signal end; the first logic circuit is connected with the normal phase output end of the first D trigger, the second control signal end and the first enabling signal end of the phase change memory, and is used for inputting a first enabling signal to the first enabling signal end of the phase change memory according to signals of the normal phase output end of the first D trigger and the second control signal end; the second logic circuit is connected with the normal phase output end of the first D trigger and the second enabling signal end of the phase change memory, and is used for inputting a second enabling signal to the second enabling signal end of the phase change memory according to the signal of the normal phase output end of the first D trigger.

In one exemplary embodiment of the present disclosure, the first logic circuit includes: the input end of the second D trigger is connected with the positive output end of the first D trigger, and the clock control end is connected with the second control signal end; the input end of the inverter is connected with the non-inverting output end of the first D trigger; the first input end of the NAND gate is connected with the output end of the phase inverter, the second input end of the NAND gate is connected with the positive phase output end of the second D trigger, and the output end of the NAND gate is connected with the first enabling signal end of the phase change memory.

In an exemplary embodiment of the present disclosure, the first logic circuit further includes: the input end of the first connecting circuit is connected with the output end of the NAND gate; the first buffer is used for improving the driving current of the signals of the input end of the first buffer and outputting the improved driving current through the output end of the first buffer, the input end of the first buffer is connected with the output end of the first connection circuit, and the output end of the first buffer is connected with the first enabling signal end of the phase-change memory.

In an exemplary embodiment of the disclosure, the first connection circuit includes a data selector, an input terminal of the data selector is connected to an output terminal of the nand gate, and an output terminal of the data selector is connected to an input terminal of the first buffer.

In an exemplary embodiment of the disclosure, the phase-change memory may also be capable of switching into a write mode under the action of the second enable signal terminal signal, and in the write mode, the phase-change memory may be capable of writing firmware information into the flash memory. The control circuit further includes: the input end of the second connecting circuit is connected with the first control signal end, the output end of the second connecting circuit is connected with the input end of the first D trigger, and the second connecting circuit is used for adjusting signal parameters of signals at the input end of the second connecting circuit according to the read-write mode of the phase-change memory and outputting the adjusted signals through the output end of the second connecting circuit; the signal parameters include signal timing, and in the phase change, in the reading mode, the timing of the signal at the input end and the timing of the signal at the output end of the second connection circuit are the same.

In an exemplary embodiment of the present disclosure, the second logic circuit includes: the input end of the third connecting circuit is connected with the normal phase output end of the first D trigger, the output end of the third connecting circuit is connected with the second enabling signal end of the phase-change memory, and the third connecting circuit is used for adjusting signal parameters of signals of the input end of the third connecting circuit according to the read-write mode of the phase-change memory and outputting the adjusted signals through the output end of the third connecting circuit; the signal parameters include signal timing, and in the phase change, in the reading mode, the timing of the signal at the input end and the timing of the signal at the output end of the third connection circuit are the same.

In an exemplary embodiment of the present disclosure, the second logic circuit further includes: the signal of the input end of the fourth connecting circuit is the same as the signal time sequence of the output end of the fourth connecting circuit, and the input end of the fourth connecting circuit is connected with the output end of the third connecting circuit; the second buffer is used for improving the driving current of the signals of the input end of the second buffer and outputting the improved driving current through the output end of the second buffer, the input end of the second buffer is connected with the output end of the fourth connecting circuit, and the output end of the second buffer is connected with the second enabling signal end of the phase-change memory.

In an exemplary embodiment of the disclosure, the fourth connection circuit includes a data selector, an input terminal of the data selector is connected to an output terminal of the third connection circuit, and an output terminal of the data selector is connected to an input terminal of the second buffer.

In one exemplary embodiment of the present disclosure, the first D flip-flop is a metal stable type flip-flop; in one driving period, the metal stable trigger can acquire signals of the input end of the metal stable trigger respectively for multiple times, and the signals acquired multiple times are selected as input signals of the metal stable trigger.

In an exemplary embodiment of the present disclosure, the control circuit further includes: the third buffer is used for improving the driving current of the signals of the input end of the third buffer and outputting the improved driving current through the output end of the third buffer, the input end of the third buffer is connected with the second control signal end, and the output end of the third buffer is connected with the clock control end of the first D trigger.

In an exemplary embodiment of the present disclosure, the first control signal terminal and the second control signal terminal are connected to the flash memory, and the flash memory is capable of writing control signals to the first control signal terminal and the second control signal terminal, respectively.

In an exemplary embodiment of the disclosure, the phase change memory is capable of being turned on under the action of a low level signal of the first enable signal terminal and turned off under the action of a high level signal of the first enable signal terminal; the phase change memory can be switched into a read mode under the action of a low-level signal of the second enabling signal end and switched into a write mode under the action of a high-level signal of the second enabling signal end; in the writing mode, the phase change memory can write the firmware information into the flash memory.

According to an aspect of the present disclosure, a driving method of a touch and display driving integrated chip is provided, for driving the touch and display driving integrated chip, including:

writing a first control signal into a first control signal end, and writing a second control signal into a second control signal end;

the first control signal comprises a first low-level pulse, the second control signal comprises a plurality of second low-level pulses, the interval duration between two adjacent second low-level pulses is equal to the second low-level pulse duration, and the first low-level pulse duration is equal to four times of the second low-level pulse duration;

The falling edge of the first low level pulse is aligned with the rising edge of the second low level pulse, and the rising edge of the first low level pulse is aligned with the rising edge of the second low level pulse.

According to an aspect of the present disclosure, a display device is provided, which includes the above-mentioned integrated chip for touch control and display driving.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 is a functional block diagram of a display device according to the related art;

FIG. 2 is a schematic diagram of a portion of a touch and display driver integrated chip;

FIG. 3 is a timing diagram of a portion of the nodes in FIG. 2 in a read mode in which a phase transition exists;

FIG. 4 is a schematic diagram of an exemplary embodiment of a touch and display driver integrated chip of the present disclosure;

FIG. 5 is a timing diagram of a portion of the nodes of FIG. 4 in a read mode in the presence of a phase change in an exemplary embodiment;

FIG. 6 is a timing diagram of a portion of the nodes of FIG. 4 in a read mode in the presence of a phase change in another exemplary embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.

The terms "a," "an," "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.

As shown in fig. 1, a functional block diagram of a display device in the related art may include a touch and display driver integrated chip 1, a display panel 2, and a flash memory 3, wherein the touch and display driver integrated chip 1 may include a phase-change memory 11, a processor 12, and a data conversion circuit 13. The phase-change memory 11 may read firmware information in the flash memory 3 and transmit the firmware information to the processor 12, where the firmware information may include information such as an algorithm, a voltage, a frequency, and the like when the display driver integrated chip 1 is driven. The processor 12 may generate digital driving signals for driving the display panel according to the firmware information, and the digital driving signals may include touch driving signals, display driving signals, and the like. The digital driving signal may be converted by the data conversion circuit 13, thereby generating an analog signal that may directly drive the display panel 2. The data conversion circuit 13 may include a digital-to-analog converter, a rectifier, a data selector, and the like.

Fig. 2 shows a part of a circuit structure of the touch control and display driving integrated chip. The phase-change memory 11 includes a first enable signal terminal CEN, a second enable signal terminal WEN, and a clock signal terminal CLK. The phase change memory 11 can be turned on under the action of a low level signal of the first enable signal terminal CEN and turned off under the action of a high level signal of the first enable signal terminal CEN; the phase-change memory 11 can also switch into a read mode under the action of the low level signal of the second enable signal terminal WEN, and switch into a write mode under the action of the high level signal of the second enable signal terminal WEN. In the read mode, the phase-change memory 11 can read firmware information in the flash memory 3; in the write mode, the phase change memory 11 is capable of writing the firmware information to the flash memory 3. In addition, the rising edges of two adjacent high-level pulse signals on the clock signal terminal CLK may define a read or write cycle. As shown in fig. 2, the flash memory 3 may include a fourth D flip-flop DFF4, where an input terminal D of the fourth D flip-flop DFF4 is connected to a signal terminal cg located in the flash memory 3, and a clock control terminal CP is connected to a signal terminal spim located in the flash memory 3.

As shown in fig. 2, the touch and display driver integrated chip may further include a control circuit 14, where the control circuit 14 may be connected between the flash memory 3 and the phase-change memory 11, and the control circuit 14 may be configured to input an enable signal to the first enable signal terminal CEN and the second enable signal terminal WEN of the phase-change memory 11 according to a control signal of an output terminal of the flash memory 3, so as to control the phase-change memory 11 to read firmware information from the flash memory 3 or write firmware information to the flash memory 3.

As shown in fig. 2, the control circuit 14 may include: the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the first connection circuit GL1, the second connection circuit GL2, the third connection circuit GL3, the fourth connection circuit GL4, the inverter INT, the nand gate NG, the first buffer BF1, the second buffer BF2, and the third buffer BF3. The input end of the third buffer BF3 is connected with the second control signal end CN2; the input end of the second connecting circuit GL2 and the positive phase output end Q of the fourth D trigger DFF4 are connected with the first control signal end CN1; the input end D of the first D trigger DFF1 is connected with the output end of the second connecting circuit GL2, the normal phase output end Q is connected with the first node N1, and the clock control end CP is connected with the output end of the third buffer BF 3; the input end D of the second D trigger DFF2 is connected with the first node N1, the normal phase output end Q is connected with the second node N2, and the clock control end CP is connected with the output end of the third buffer BF 3; the input end of the inverter INT is connected with the first node N1, and the output end of the inverter INT is connected with the third node N3; two input ends of the NAND gate NG are respectively connected with a second node N2 and a third node N3; the input end of the first connecting circuit GL1 is connected with the output end of the NAND gate NG, the output end of the first connecting circuit GL1 is connected with the input end of the first buffer BF1, and the output end of the first buffer BF1 is connected with the first enabling signal end CEN of the phase-change memory 11; the input end of the third connecting circuit GL3 is connected with the first control signal end CN1, and the output end of the third connecting circuit GL3 is connected with the input end D of the third D trigger DFF 3; the clock control end CP of the third D flip-flop DFF3 is connected to the output end of the third buffer BF3, the normal phase output end Q is connected to the input end of the fourth connection circuit GL4, the input end of the second buffer BF2 is connected to the output end of the fourth connection circuit GL4, and the output end is connected to the second enable signal end WEN of the phase change memory 11. The signal of the clock signal terminal CLK in the phase change memory 11 can be provided through the first clock signal terminal CLK1 in the flash memory 3.

As shown in fig. 2, the first connection circuit GL1 is used for transmitting the signal of its input terminal to its output terminal, and the signal of the input terminal of the first connection circuit GL1 and the signal of its output terminal have the same timing. The first connection circuit GL1 may include a data selector, the first connection circuit GL1 may include a plurality of output terminals, wherein an input terminal of the first buffer BF1 is connected to one output terminal of the first connection circuit GL1, and the first connection circuit GL1 may be configured to selectively output a signal of the input terminal to one of the plurality of output terminals. The first connection circuit GL1 may further include a switching circuit, and the first connection circuit GL1 may turn off or on a signal transmission path between the output end of the nand gate NG and the first buffer BF 1. Similarly, the fourth connection circuit GL4 is used to transmit the signal at the input end to the output end, and the signal at the input end of the fourth connection circuit GL4 and the signal at the output end are the same in time sequence. The fourth connection circuit GL4 may include a data selector, and the fourth connection circuit GL4 may include a plurality of output terminals, wherein an input terminal of the second buffer BF2 is connected to one output terminal of the fourth connection circuit GL4, and the fourth connection circuit GL4 may be configured to selectively output a signal of the input terminal thereof to one of the plurality of output terminals. In addition, the fourth connection circuit GL4 may further include a switching circuit, and the fourth connection circuit GL4 may turn off or on a signal transmission path between the third D flip-flop non-inverting output terminal Q and the second buffer BF 2. The second connection circuit GL2 may be used to adjust signal parameters of the signal at the input end according to the read-write mode of the phase-change memory, and output the adjusted signal through the output end. For example, the signal parameter may include a signal timing, and correspondingly, the second connection circuit GL2 may include a signal delayer, and the second connection circuit GL2 may perform different timing adjustment on the signal at its input terminal in the read mode or the write mode. In the phase transition, in the reading mode, the input end signal and the output end signal of the second connection circuit GL2 have the same time sequence. Similarly, the third connection circuit GL3 may be configured to adjust a signal parameter of the signal at the input terminal according to the read/write mode of the phase-change memory, and output the adjusted signal through the output terminal. For example, the signal parameter may include a signal timing, and correspondingly, the third connection circuit GL3 may include a signal delayer, and the third connection circuit GL3 may perform different timing adjustment on the signal at its input terminal in the read mode or the write mode. In the phase transition, in the reading mode, the input end signal and the output end signal of the third connection circuit GL3 have the same time sequence.

As shown in fig. 2, the first D flip-flop DFF1 and the third D flip-flop DFF3 may be metal stable flip-flops. The signals passing through the first D flip-flop DFF1 and the third D flip-flop DFF3 have delays, respectively. When the touch control and display driving integrated chip adopts a smaller nanometer process, for example, a 40nm process, the resistance of each device on the touch control and display driving integrated chip is larger, so that the delay of a certain probability passing through the third D trigger DFF3 signal is larger than the delay of a certain probability passing through the first D trigger DFF1 signal, and the phase change memory 11 can be further caused to realize the normal reading function.

FIG. 3 is a timing diagram of a portion of the nodes of FIG. 2 in a read mode in which a phase change exists. The time sequence is set to have no time delay after the first D trigger DFF1 signal and have time delay after the third D trigger DFF3 signal, so that the situation that the time delay after the third D trigger DFF3 signal is longer than the time delay after the first D trigger DFF1 signal and the normal reading function cannot be realized by the memory 11 is changed. Wherein, spim is the timing of the signal terminal Spim, CN1 is the timing of the first control signal terminal CN1, CN2 is the timing of the second control signal terminal CN2, N1 is the timing of the first node N1, N2 is the timing of the second node N2, N3 is the timing of the third node N3, CLK1 is the timing of the first clock signal terminal CLK1, CEN is the timing of the first enable signal terminal CEN, WEN is the actual timing of the second enable signal terminal WEN, WEN0 is the theoretical timing of the second enable signal terminal WEN.

As shown in fig. 2 and 3, in the read mode of the phase-change memory 11, the first connection circuit GL1, the second connection circuit GL2, the third connection circuit GL3, the fourth connection circuit GL4, the first buffer BF1, the second buffer BF2, and the third buffer BF3 do not affect the timing of the signals passing through them. The signal of the first control signal terminal CN1 is unchanged in time sequence after passing through the second connection circuit GL2, and the signal of the second control signal terminal CN2 is unchanged in time sequence after passing through the third buffer BF 3. The timing of the NAND gate NG output signal is the same as the timing of the first enable signal terminal CEN. The timing of the Q signal at the positive output terminal of the third D flip-flop DFF3 is the same as the timing of the second enable signal terminal WEN. As shown in fig. 3, the theoretical timing of the positive output terminal of the third D flip-flop DFF3 is shown as WEN0 in fig. 3, however, the actual timing of the positive output terminal of the third D flip-flop DFF3 is shown as the second enable signal terminal WEN in fig. 3 due to the delay of the signal passing through the third D flip-flop DFF 3. In the period T1 in fig. 3, when the logic level of the first enable signal terminal CEN is low, the logic level of the second enable signal terminal WEN is high, so that the phase-change memory 11 cannot enter the read mode, i.e. the phase-change memory 11 cannot read the firmware information from the flash memory 3, and the display panel cannot display normally.

Based on this, the present exemplary embodiment provides a touch and display driving integrated chip, as shown in fig. 4, which is a schematic structural diagram of an exemplary embodiment of the touch and display driving integrated chip of the present disclosure. The touch control and display driving integrated chip may include: the phase-change memory 11 and the control circuit 14, the phase-change memory 11 is connected with the flash memory 3, the phase-change memory 11 comprises a first enabling signal end CEN and a second enabling signal end WEN, the phase-change memory 11 can be started under the signal action of the first enabling signal end CEN and can be switched into a reading mode under the signal action of the second enabling signal end WEN, and in the reading mode, the phase-change memory 11 can read firmware information in the flash memory 3. The control circuit includes: the first D trigger DFF1, the first logic circuit 141 and the second logic circuit 142, wherein the input end D of the first D trigger DFF1 is connected with the first control signal end CN1, and the clock control end CP is connected with the second control signal end CN2; the first logic circuit 141 is connected to the normal phase output terminal Q of the first D flip-flop DFF1, the second control signal terminal CN2, and the first enable signal terminal CEN of the phase-change memory 11, and is configured to input a first enable signal to the first enable signal terminal CEN of the phase-change memory 11 according to signals of the normal phase output terminal Q of the first D flip-flop DFF1 and the second control signal terminal CN2; the second logic circuit 142 is connected to the normal phase output terminal Q of the first D flip-flop DFF1 and the second enable signal terminal WEN of the phase change memory 11, and is configured to input a second enable signal to the second enable signal terminal WEN of the phase change memory 11 according to the signal of the normal phase output terminal Q of the first D flip-flop DFF 1.

As shown in fig. 2 and 4, compared to the touch and display driving integrated chip shown in fig. 2, the touch and display driving integrated chip provided in this exemplary embodiment of fig. 4 removes the third D flip-flop DFF3, and generates the second enable signal according to the signal of the positive output terminal Q of the first D flip-flop DFF1 by using the second logic circuit 142. Therefore, the technical problem that the phase change memory 11 cannot read the firmware information in the flash memory 3 due to the delay action of the third D flip-flop DFF3 in the related art is avoided.

In this exemplary embodiment, the phase-change memory 11 is further capable of switching into a write mode under the action of the second enable signal terminal WEN signal, and in the write mode, the phase-change memory 11 is capable of writing firmware information into the flash memory 3. For example, when the second enable signal terminal WEN signal is at a low level, the flash memory 3 is switched into the read mode; when the signal of the second enable signal terminal WEN is at a high level, the flash memory 3 is switched into the write mode. The flash memory 3 may also be turned off by the first enable signal terminal CEN signal, for example, when the first enable signal terminal CEN signal is at a low level, the flash memory 3 is turned on, and when the first enable signal terminal CEN signal is at a high level, the flash memory 3 is turned off.

In the present exemplary embodiment, as shown in fig. 4, the first logic circuit 141 may include: the input end D of the second D trigger DFF2 is connected with the normal phase output end Q of the first D trigger DFF1, and the clock control end CP is connected with the second control signal end CN2; the input end of the inverter INT is connected with the non-inverting output end Q of the first D trigger DFF 1; the first input end of the nand gate NG is connected to the output end of the inverter INT, the second input end is connected to the normal phase output end Q of the second D flip-flop DFF2, and the output end is connected to the first enable signal end CEN of the phase change memory 11.

In this exemplary embodiment, as shown in fig. 4, the first logic circuit may further include: the input end of the first connection circuit GL1 is connected with the output end of the NAND gate NG; the first buffer BF1 is configured to increase the driving current of the input signal and output the increased driving current through the output terminal, the input terminal of the first buffer BF1 is connected to the output terminal of the first connection circuit GL1, and the output terminal is connected to the first enable signal terminal of the phase-change memory 11.

In this exemplary embodiment, the first connection circuit GL1 may include a data selector, the first connection circuit GL1 may include a plurality of output terminals, wherein an input terminal of the first buffer BF1 is connected to one output terminal of the first connection circuit GL1, and the first connection circuit GL1 may be configured to selectively output a signal of the input terminal thereof to one of the plurality of output terminals thereof. The first connection circuit GL1 may further include a switching circuit, and the first connection circuit GL1 may turn off or on a signal transmission path between the output end of the nand gate NG and the first buffer BF 1.

In this exemplary embodiment, as shown in fig. 4, the control circuit 14 may further include: the input end of the second connection circuit GL2 is connected to the first control signal end CN1, the output end is connected to the input end D of the first D flip-flop DFF1, the second connection circuit GL2 is used to adjust the signal parameters of the input end signal according to the read-write mode of the phase-change memory 11, and output the adjusted signal through the output end. The signal parameters may include signal timing, signal amplitude, and the like, and the second connection circuit GL2 may include a signal delay, a voltage amplifier, and the like. The second connection circuit GL2 may perform different timing adjustment on the signal at its input terminal in the read mode or the write mode. In the present exemplary embodiment, in the read mode of the phase-change memory 11, the timings of the input signal and the output signal of the second connection circuit GL2 are the same.

In the present exemplary embodiment, the timing of the second enable signal output from the second logic circuit 142 may be the same as the timing of the positive output terminal Q of the first D flip-flop DFF 1. As shown in fig. 4, the second logic circuit 142 may include: the input end of the third connection circuit GL3 is connected to the normal phase output end Q of the first D flip-flop DFF1, the output end is connected to the second enable signal end WEN of the phase change memory 11, the third connection circuit GL3 is used for adjusting the signal parameters of the input end signal according to the read-write mode of the phase change memory 11, wherein the signal parameters may include signal timing, signal amplitude, etc., and correspondingly, the third connection circuit GL3 may include a signal delay device, a voltage amplifier, etc. The third connection circuit GL3 can perform different timing adjustment on the signal at its input terminal in the read mode or the write mode. In the present exemplary embodiment, in the read mode of the phase-change memory 11, the timings of the input signal and the output signal of the third connection circuit GL3 are the same.

In this exemplary embodiment, the second logic circuit 142 may further include: the signal of the input end of the fourth connecting circuit GL4 and the signal of the output end of the fourth connecting circuit GL4 have the same time sequence, and the input end of the fourth connecting circuit GL4 is connected with the output end of the third connecting circuit GL 3; the second buffer BF2 is configured to increase the driving current of the input signal and output the increased driving current through the output terminal, the input terminal of the second buffer BF2 is connected to the output terminal of the fourth connection circuit GL4, and the output terminal is connected to the second enable signal terminal WEN of the phase-change memory 11.

In this exemplary embodiment, the fourth connection circuit GL4 may include a data selector, the fourth connection circuit GL4 may include a plurality of output terminals, the input terminal of the fourth connection circuit GL4 is connected to the input terminal of the third connection circuit GL3, the input terminal of the second buffer BF2 is connected to one output terminal of the fourth connection circuit GL4, and the fourth connection circuit GL4 may be used to selectively output the signal of the input terminal thereof to one of the plurality of output terminals. The fourth connection circuit GL4 may further include a switching circuit, and the fourth connection circuit GL4 may turn off or on a signal transmission path between the third connection circuit GL3 and the second buffer BF 2.

In the present exemplary embodiment, the first D flip-flop DFF1 may be a metal stable flip-flop; the metal stable trigger can respectively acquire signals of the input ends of the metal stable trigger in one driving period, and the signals acquired in multiple times are selected as the input signals of the metal stable trigger. The metal stable trigger can take the more accurate signal of the signals acquired multiple times as the signal of the input end according to an internal algorithm, for example, the metal stable trigger can acquire the signal of the input end twice respectively. Thus, the metal stabilized flip-flop has higher stability. The second D flip-flop DFF2 may be a normal D flip-flop that only acquires the signal at its input once.

In this exemplary embodiment, as shown in fig. 4, the control circuit may further include: the third buffer BF3 is configured to increase the driving current of the signal at the input end thereof, and output the increased driving current through the output end thereof, the input end of the third buffer BF3 is connected to the second control signal end CN2, and the output end is connected to the clock control end CP of the first D flip-flop DFF1 and the clock control end CP of the second D flip-flop DFF 2.

In this exemplary embodiment, as shown in fig. 4, the flash memory 3 may include a fourth D flip-flop DFF4, where an input terminal D of the fourth D flip-flop DFF4 is connected to a signal terminal cg located in the flash memory 3, a CP terminal is connected to a signal terminal spim located in the flash memory 3, and a normal phase output terminal Q is connected to the first control signal terminal CN1. In addition, the second control signal terminal CN2 may be connected to the flash memory 3, and the flash memory 3 may write control signals into the first control signal terminal CN1 and the second control signal terminal CN2, respectively. It should be understood that in other embodiments, the control signals of the first control signal terminal CN1 and the second control signal terminal CN2 may also be provided by other circuits.

FIG. 5 is a timing diagram of a portion of the nodes of FIG. 4 in a read mode in which a phase change exists in an exemplary embodiment. The signal passing through the first D flip-flop DFF1 is set without delay. The first node N1 is an equipotential point of the positive output terminal Q of the first D flip-flop DFF1, the second node N2 is an equipotential point of the positive output terminal Q of the second D flip-flop DFF2, and the third node N3 is an equipotential point of the output terminal of the inverter INT. The Spim is the timing of the signal terminal Spim, CN1 is the timing of the first control signal terminal CN1, CN2 is the timing of the second control signal terminal CN2, N1 is the timing of the first node N1, N2 is the timing of the second node N2, N3 is the timing of the third node N3, CLK1 is the timing of the first clock signal terminal CLK1, CEN is the timing of the first enable signal terminal CEN, WEN is the timing of the second enable signal terminal WEN.

As shown in fig. 4 and 5, the first connection circuit GL1, the second connection circuit GL2, the third connection circuit GL3, the fourth connection circuit GL4, the first buffer BF1, the second buffer BF2, and the third buffer BF3 do not affect the timing of the signals passing through the phase-change memory 11 in the read mode. The signal of the first control signal terminal CN1 is unchanged in time sequence after passing through the second connection circuit GL2, and the signal of the second control signal terminal is unchanged in time sequence after passing through the third buffer BF 3. The timing of the NAND gate NG output signal is the same as the timing of the first enable signal terminal CEN. The timing of the first node N1 signal is the same as the timing of the second enable signal WEN. In the period T1 in fig. 5, when the logic level of the first enable signal terminal CEN is low, the logic level of the second enable signal terminal WEN is low, so that the phase-change memory 11 can read the firmware information in the flash memory in the read mode.

FIG. 6 is a timing diagram of a portion of the nodes of FIG. 4 in a read mode in the presence of a phase change in another exemplary embodiment. The delay of the signal passing through the first D flip-flop DFF1 is set. The Spim is the timing of the signal terminal Spim, CN1 is the timing of the first control signal terminal CN1, CN2 is the timing of the second control signal terminal CN2, N1 is the timing of the first node N1, N2 is the timing of the second node N2, N3 is the timing of the third node N3, CLK1 is the timing of the first clock signal terminal CLK1, CEN is the timing of the first enable signal terminal CEN, WEN is the timing of the second enable signal terminal WEN. The first node N1 is an equipotential point of the positive output terminal Q of the first D flip-flop DFF1, the second node N2 is an equipotential point of the positive output terminal Q of the second D flip-flop DFF2, and the third node N3 is an equipotential point of the output terminal of the inverter INT.

As shown in fig. 4, 5 and 6, due to the delay of the signal passing through the first D flip-flop DFF1, the timing of the first node N1 in fig. 6 moves rightward compared to the timing shown in fig. 5, and accordingly, the timing of the second node N2, the timing of the third node N3, the timing of the first enable signal terminal CEN and the second enable signal terminal WEN all move rightward. In the period T1 in fig. 6, when the logic level of the first enable signal terminal CEN is low, the logic level of the second enable signal terminal WEN is low, so that the phase-change memory 11 can read the firmware information in the flash memory in the read mode.

The present exemplary embodiment also provides a driving method of a touch and display driving integrated chip, for driving the touch and display driving integrated chip, where the method includes:

writing a first control signal into a first control signal end, and writing a second control signal into a second control signal end;

the first control signal comprises a first low-level pulse, the second control signal comprises a plurality of second low-level pulses, the interval duration between two adjacent second low-level pulses is equal to the second low-level pulse duration, and the first low-level pulse duration is equal to four times of the second low-level pulse duration;

The falling edge of the first low level pulse is aligned with the rising edge of the second low level pulse, and the rising edge of the first low level pulse is aligned with the rising edge of the second low level pulse.

The driving method of the touch and display driving integrated chip is described in detail in the above description, and will not be repeated here.

The present exemplary embodiment also provides a display device, which includes the above-mentioned integrated chip for touch control and display driving. The display device can be a display device such as a mobile phone, a tablet personal computer, a television and the like.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (14)

1. The utility model provides a touch and display drive integrated chip which characterized in that, touch and display drive integrated chip includes:

The phase-change memory is connected with a flash memory and comprises a first enabling signal end and a second enabling signal end, and can be started under the signal action of the first enabling signal end and cut into a reading mode under the signal action of the second enabling signal end;

In the reading mode, the phase-change memory can read firmware information in the flash memory;

a control circuit, comprising:

The input end of the first D trigger is connected with a first control signal end, and the clock control end is connected with a second control signal end;

the first logic circuit is connected with the normal phase output end of the first D trigger, the second control signal end and the first enabling signal end of the phase change memory and is used for inputting a first enabling signal to the first enabling signal end of the phase change memory according to signals of the normal phase output end of the first D trigger and the second control signal end;

And the second logic circuit is connected with the normal phase output end of the first D trigger and the second enabling signal end of the phase-change memory and is used for inputting a second enabling signal to the second enabling signal end of the phase-change memory according to the signal of the normal phase output end of the first D trigger.

2. The integrated touch and display driver chip of claim 1, wherein the first logic circuit comprises:

the input end of the second D trigger is connected with the positive phase output end of the first D trigger, and the clock control end is connected with the second control signal end;

The input end of the inverter is connected with the non-inverting output end of the first D trigger;

And the first input end of the NAND gate is connected with the output end of the phase inverter, the second input end of the NAND gate is connected with the positive phase output end of the second D trigger, and the output end of the NAND gate is connected with the first enabling signal end of the phase change memory.

3. The integrated touch and display driver chip of claim 2, wherein the first logic circuit further comprises:

The first connecting circuit is used for transmitting the signal of the input end of the first connecting circuit to the output end of the first connecting circuit, the signal of the input end of the first connecting circuit is the same as the signal time sequence of the output end of the first connecting circuit, and the input end of the first connecting circuit is connected with the output end of the NAND gate;

The first buffer is used for improving the driving current of the signals of the input end of the first buffer and outputting the improved driving current through the output end of the first buffer, the input end of the first buffer is connected with the output end of the first connecting circuit, and the output end of the first buffer is connected with the first enabling signal end of the phase-change memory.

4. The integrated touch and display driver chip of claim 3, wherein the first connection circuit comprises:

and the input end of the data selector is connected with the output end of the NAND gate, and one output end of the data selector is connected with the input end of the first buffer.

5. The integrated touch and display driver chip of claim 1, wherein the phase-change memory is further capable of switching into a write mode under the action of the second enable signal terminal signal, and wherein in the write mode, the phase-change memory is capable of writing firmware information into the flash memory;

The control circuit further includes:

The input end of the second connection circuit is connected with the first control signal end, the output end of the second connection circuit is connected with the input end of the first D trigger, and the second connection circuit is used for adjusting signal parameters of signals of the input end of the second connection circuit according to a read-write mode of the phase-change memory and outputting the adjusted signals through the output end of the second connection circuit;

The signal parameters include signal timing, and in the phase change, in the reading mode, the timing of the signal at the input end and the timing of the signal at the output end of the second connection circuit are the same.

6. The integrated touch and display driver chip of claim 2, wherein the second logic circuit comprises:

the input end of the third connecting circuit is connected with the normal phase output end of the first D trigger, the output end of the third connecting circuit is connected with the second enabling signal end of the phase-change memory, and the third connecting circuit is used for adjusting signal parameters of signals of the input end of the third connecting circuit according to the read-write mode of the phase-change memory and outputting the adjusted signals through the output end of the third connecting circuit;

The signal parameters include signal timing, and in the phase change, in the reading mode, the timing of the signal at the input end and the timing of the signal at the output end of the third connection circuit are the same.

7. The integrated touch and display driver chip of claim 6, wherein the second logic circuit further comprises:

The signal of the input end of the fourth connecting circuit is the same as the signal time sequence of the output end of the fourth connecting circuit, and the input end of the fourth connecting circuit is connected with the output end of the third connecting circuit;

The second buffer is used for improving the driving current of the signals of the input end of the second buffer and outputting the improved driving current through the output end of the second buffer, the input end of the second buffer is connected with the output end of the fourth connecting circuit, and the output end of the second buffer is connected with the second enabling signal end of the phase-change memory.

8. The integrated touch and display driver chip of claim 7, wherein the fourth connection circuit comprises:

And the input end of the data selector is connected with the output end of the third connecting circuit, and one output end of the data selector is connected with the input end of the second buffer.

9. The integrated touch and display driver chip of claim 1, wherein the first D flip-flop is a metal-stabilized flip-flop;

in one driving period, the metal stable trigger can acquire signals of the input end of the metal stable trigger respectively for multiple times, and the signals acquired multiple times are selected as input signals of the metal stable trigger.

10. The integrated touch and display driver chip of claim 1, wherein the control circuit further comprises:

And the input end of the third buffer is connected with the second control signal end, and the output end of the third buffer is connected with the clock control end of the first D trigger.

11. The integrated touch and display driver chip of claim 1, wherein the first control signal terminal and the second control signal terminal are connected to the flash memory, and the flash memory is capable of writing control signals into the first control signal terminal and the second control signal terminal, respectively.

12. The integrated touch and display driver chip of claim 1, wherein the phase change memory is capable of being turned on by a low level signal of the first enable signal terminal and turned off by a high level signal of the first enable signal terminal;

the phase change memory can be switched into a read mode under the action of a low-level signal of the second enabling signal end and switched into a write mode under the action of a high-level signal of the second enabling signal end;

In the writing mode, the phase change memory can write the firmware information into the flash memory.

13. A driving method of a touch and display driving integrated chip for driving the touch and display driving integrated chip according to any one of claims 1 to 12, comprising:

writing a first control signal into a first control signal end, and writing a second control signal into a second control signal end;

the first control signal comprises a first low-level pulse, the second control signal comprises a plurality of second low-level pulses, the interval duration between two adjacent second low-level pulses is equal to the second low-level pulse duration, and the first low-level pulse duration is equal to four times of the second low-level pulse duration;

The falling edge of the first low level pulse is aligned with the rising edge of the second low level pulse, and the rising edge of the first low level pulse is aligned with the rising edge of the second low level pulse.

14. A display device comprising the touch and display driver integrated chip of any one of claims 1-12.