JP2002009952A - Information multiplex transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information multiplex transmission circuit capable of storing pieces of transmission information in a single memory, sending the stored information and flexibly increasing/decreasing transmission information length and the number of the pieces of transmission information. SOLUTION: This information multiplex transmission circuit is provided with: a memory for string input data and repeated instruction data; and a FIFO for storing the addresses of the memory and the leading addresses of information stored in the memory; a NAND circuit for inverting the logical level of AND of an RE signal and a WE signal stored in the memory; an adder for adding the output from the NAND circuit and the output from the FIFO; a delay flip flop for storing the output of the adder; a selector for selecting one of the outputs of the adder and the delay flip flop; and an OR circuit for executing the OR operation of a recording start signal, a recording stop signal, a leasing address updating signal, and the repeated instruction data outputted from the memory and supplying the OR operation result to the selector as a selection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information multiplex transmission circuit for multiplexing a plurality of pieces of guidance information and transmitting the multiplexed information. In particular, the transmission information can be stored and transmitted in a single memory. The present invention relates to an information multiplex transmission circuit capable of flexibly increasing or decreasing the number of information.

When a telephone subscriber makes a telephone call, for example, when the line is congested and the telephone subscriber cannot connect to a partner who desires connection, there is a notice that the line is congested,
If you dialed the other party's phone number incorrectly or dialed without knowing that the other party's number has been changed, you will be notified that the other party's number does not exist, and it is registered that the dialed other party's number has been changed. If there is, the user notices that there are multiple guidance services, such as the guidance of a new number along with the guidance that the number has been changed.

An information multiplex transmission circuit for transmitting these pieces of guidance information is mounted on a service function unit connected to an exchange.

[0004] In recent years, the types of guidance information tend to increase due to the addition of various services, and the number of guidance information must naturally be increased. On the other hand, demands for downsizing of exchanges have become stronger.

[0005] In other words, there is a strong demand that the number of pieces of guidance information handled by the service function device increases and the size of the service function device conflicts with each other. this is,
The same applies to the information multiplex transmission circuit mounted on the service function device.

[0006] At the same time, there is a need for an information multiplex transmission circuit that can flexibly change the information length and the number of pieces of guide information with the addition of various services.

[0007]

2. Description of the Related Art FIG. 26 shows a conventional information multiplex transmission circuit. In FIG. 26, the input data and the output data of the information to be provided are assumed to be 8 bits, and the address of the memory for storing the input data can be expressed by 16 bits so that the following description will be more specific. It is assumed that the number of information is 4, and specific information is expressed as information # 1 to information # 4.

In FIG. 26, reference numerals 101 to 104 denote input data of information # 1 to information # 4 and information # 1 to # 4.
To send repeatedly (hereinafter,
Described as "repeated transmission instruction data". ), 105 is an adder for adding 1 to an address supplied to the memories 101 to 104, and 106 is a memory 1
The logical start of a recording start signal for instructing the start of storage of information in the memories 101 to 104, the recording stop signal for instructing the stop of storage of information in the memories 101 to 104, and the repetitive transmission instruction data read from the memories 101 to 104 NOR circuit for inverting and outputting the logical level of the operation result, 1
07 performs an AND operation of the 16-bit output of the adder 105 and the 1-bit output of the NOR circuit 106, that is, the logical level of the output of the NOR circuit 106 is “0”.
, An AND circuit that masks the output of the adder 105,
108 to 111 are delay flip-flops for delaying the 16-bit output of the AND circuit 107. The outputs of the delay flip-flop 111 are supplied to the memories 101 to 104 as addresses.

Actually, each of the delay flip-flops 108 to 111 is a set of 16 delay flip-flops receiving the same clock and receiving one bit of the 16-bit output of the AND circuit 107, respectively. However, there are 16 input lines to the data terminal (indicated as “D” in the figure) and 16 output lines from the output terminal (indicated as “Q” in the figure). It is shown by such a virtual delay flip-flop. Similar notation will be used hereinafter.

FIG. 27 is an example of a memory map in a conventional information multiplex transmission circuit.

In FIG. 27, reference numerals 101 to 104 correspond to those in FIG.
6 is the same as the memory shown in FIG.

In the conventional information multiplex transmission circuit, for example, information # 1 is stored in the memory 101 and information # 2 is stored in the memory 102.
Information # 3 is stored in the memory 103, and information # 4 is stored in the memory 10
4, specific information is stored in a specific memory.

Accordingly, FIG. 27A shows that the information # 1 is the address 0x0000 of the memory 101 (“0x” is hexadecimal notation. Each digit is 0, 1, 2, 3,.
4, 5, 6, 7, 8, 9, a (10), b (11), c
Any of (12), d (13), e (14) and f (15) weights can be taken. That is, since each digit can display 4 bits, 4 digits = 4 × 4 = 16 bits of address can be defined. ) To 0x0fff, indicating that addresses 0x1000 and beyond of the memory 101 are not used.

Further, it shows that "0" is stored at addresses 0x0000 to 0x0ffe in the area of the repeat instruction data of the memory 101, and "1" which is repeat instruction data is stored at the address 0x0fff.

Similarly, the address 0x00 of the memory 102
Information # 2 is stored from 00 to address 0x14ff, repeat instruction data "1" is stored at address 0x14ff of the repeat instruction data area, information # 3 is stored from address 0x0000 to address 0x22ff of memory 103, and repeat instruction is performed. The repeat instruction data “1” is stored at the address 0x22ff of the data area, indicating that no information is stored in the memory 104.

As described above, since information having different lengths is generally stored in each memory, in the configuration shown in FIG. 26, it is necessary to supply an independent address to each memory in accordance with the difference in information length. There is. To this end, four stages of 16 parallel delay flip-flops equal to the number of bits of the address are arranged so that the addresses to be supplied to each memory can be held and supplied in order.

That is, for example, the delay flip-flop 11
1 holds an address to be supplied to the memory 101,
When an address is supplied to the memory 101, the address to be supplied to the memory 102 is stored in the delay flip-flop 110, and the memory 1 is stored in the delay flip-flop 109.
03 is supplied to the delay flip-flop 1
08 holds an address to be supplied to the memory 104.

When the address held in the delay flip-flops 108 to 110 is shifted at the next timing, the adder 1 adds the address held in the delay flip-flop 111 to the address.
At 05, the address obtained by adding 1 to the result of the AND operation of the NOR circuit 106 is held in the delay flip-flop 108 as a new address of the memory 101.

At this time, if the logical levels of the recording start signal and the recording stop signal supplied to the NOR circuit 106 and the repetitive transmission instruction data read from the memory 101 are all "0", the data is held in the delay flip-flop 111. The address obtained by adding 1 to the address that was
Delay flip-flop 108 as the new address of 1
Is held.

If any of the logical levels of the recording start signal, the recording stop signal, and the repeat transmission instruction data supplied to the NOR circuit 106 is "1", the adder 10
5 is output from the logical product circuit 107 to the NOR circuit 1
At this time, the address held in the delay flip-flop 108 is the head address 0x0000 of the memory 101.

FIG. 28 shows that the same information can be repeatedly transmitted after reading the repeated transmission instruction data stored in the memory at the information transmission timing (1) of the configuration shown in FIG.

In FIG. 28, (1) is an information number, and in the configuration of FIG. 26, it is a chip select signal for physically selecting one of the memories 101 to 104. That is, for example, when the information number is # 1, the memory 10
Only one is supplied with the chip select signal, and reading or writing is performed.

The chip select signal is supplied from a control circuit outside the information multiplex transmission circuit, but since this is a commonly practiced technique, the description is omitted.

Further, here, since normal voice guidance is assumed, the frequency of repetition of the same data, that is, the repetition of the same information number is 8 KHz.

(2) is a memory address. Here, the address of each memory increases from 0x0100 to 0x0101 in the memory 101 storing the information # 1, and from 0x14fe to 0 in the memory 102 storing the information # 2.
x 103 ff memory 103 storing information # 3
Now, go from 0x0000 to 0x0001, information # 4
Is stored in the memory 104 from 0x1234 to 0x12
The case of stepping toward 35 is illustrated.

Here, as described with reference to FIG. 27, the address 0x1 of the repetition instruction data area of the memory 102
Since the repeat instruction data "1" is stored in 4ff, when the address 0x14ff is supplied to the memory 102, the repeat instruction data is read. This is indicated by the pulse of the repetition instruction data (read) in FIG.

Since the read pulse of the repetition instruction data is supplied to the NOR circuit 106 shown in FIG. 26, at this time, the logical level of the output of the NOR circuit 106 becomes "0" and the output of the adder 105 Is the AND circuit 107
And the address held in the delay flip-flop 108 is 0x0000.

This is supplied to the memory 102 in the next frame.
x0000 and returns the address 0x0 from the memory 102.
The head of the information stored in 000 is read.

The above operation is repeated every time the address supplied to the memory 102 becomes 0x14ff.
Information stored in the memory 102 can be repeatedly read.

Similarly, in the memory 101, the address is 0x
Each time it becomes 0fff, the address in the memory 103 is 0x2
The stored information can be repeatedly read each time the value becomes 2ff.

FIG. 29 shows that, when the recording start signal is supplied to the memory receiving the chip select signal at the information transmission timing (part 2) of the configuration of FIG. 26, the head address is stored in the memory in the next frame. 0x0000 is set to indicate that information can be stored.

In FIG. 29, it is assumed that the information number and the memory address have changed as shown in (1) and (2).

At this time, as shown in (3), information number # 4
When the logical level of the recording start signal is set to "1" at the timing of "1", the output of the NOR circuit 106 in FIG. 26 becomes "0" and the output of the adder 105 is masked by the AND circuit 107. The address stored in the delay flip-flop 108 is 0x0000. Since this address 0x0000 is supplied to the memory 104 at the timing of the information # 4 of the next frame, the head address 0x000 is stored in the memory 104 in which the information has not been stored so far.
The information is supplied as 0, and thereafter, information is stored in the memory 104.

FIG. 30 illustrates the operation when the storage of information in the memory is stopped at the information transmission timing (part 3) of the configuration shown in FIG.

In FIG. 30, it is assumed that the information number and the memory address change as shown in (1) and (2), and the address is 0x07ff at the timing of the information number # 4 in the first frame.

At this timing, as shown in (5), when the logic level of the repetition instruction data supplied to the memory 104 of FIG. 26 is set to "1", the address 0x07 of the memory 104 is obtained.
The instruction data is repeatedly written to ff. Memory 10
If the address 0x07ff of No. 4 is the last address for writing information, and the logical level of the recording stop signal is set to "1" at the same time, the NOR circuit 106 in FIG.
Becomes "0", and the output of the adder 105 is masked in the AND circuit 107. Therefore, the address stored in the delay flip-flop 108 is 0x0000, and the information # 4 is stored in the memory 104 from the next frame. It becomes readable from the first address. Then, each time the address 0x07ff is supplied to the memory 104, the address of the memory 104 is updated to 0x0000, and the information stored in the memory 104 is repeatedly read.

By operating as described above, the conventional information multiplex transmission circuit can store a plurality of information in a memory and sequentially read from each memory to multiplex the plurality of information and transmit the multiplexed information.

[0038]

As described above, in the conventional information multiplexing transmission circuit, the number of memories equal to the number of information to be stored and the number of stages of delay flip-flops equal to the number of information are used.

Therefore, in the conventional information multiplex transmission circuit, the larger the number of information to be stored, the larger the scale of the memory and the delay flip-flop, and the larger the number of wirings on the printed board unit constituting the information multiplex transmission circuit. .

When the amount of one piece of information is small, the area where the memory is not used increases, so that there is a problem that the memory use efficiency is low.

Further, as the number of information to be stored increases, the number of stages of delay flip-flops for delaying addresses increases. However, since the delay flip-flops are cascade-connected, the printed circuit board corresponds to the increase in the number of information to be stored. It is impossible to arbitrarily increase the number of stages of the delay flip-flop on the unit.

In view of the above problems, the present invention can adapt to an increase in the number of information while retaining the original function of the information multiplex transmission circuit, and can reduce the number of wirings on the printed circuit board unit. It is another object of the present invention to provide an information multiplex transmission circuit capable of increasing the use efficiency of a memory.

[0043]

A first means includes a memory for storing input data and repetition instruction data, a FIFO for holding an address of the memory and a head address of information stored in the memory, A NAND circuit for inverting and outputting the logical level of the logical AND operation of the read enable signal and the write enable signal, and adding the output of the NAND circuit to the memory address or the head address output from the FIFO An adder, a delay flip-flop that holds the output of the adder, a selector that selects one of the output of the adder and the output of the delay flip-flop, a recording start signal, a recording stop signal, a head address update signal, A logical sum circuit for performing a logical sum operation on the repetition instruction data output from the memory and supplying it as a selection signal to the selector A broadcast multiplex transmission circuit.

According to the first means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, the number of FIFOs to be used can be reduced to one, a decrease in the use efficiency of the memory can be avoided, and the number of wires in a printed circuit board unit on which an information multiplex transmission circuit is mounted is reduced. Becomes possible.

The second means includes a memory for storing input data and repetition instruction data, a lower address counter for outputting a lower address and a carry of the memory, an upper address of the memory and a head address for storing information in the memory. A FIFO for holding an upper address (hereinafter, referred to as an upper address), a NAND circuit for inverting and outputting a logical level of a logical AND operation of a read enable signal and a write enable signal of the memory, An AND circuit for performing an AND operation of the carry output by the lower address counter and the output of the NAND circuit; and an output of the AND circuit and an upper address or an upper head address of the memory output by the FIFO. Adder for adding, delay flip-flop for holding the output of the adder, output of the adder and the delay flip-flop And a logical sum circuit for performing a logical sum operation of a recording start signal, a recording stop signal, a head address update signal, and repetition instruction data read from the memory and supplying the selected signal to the selector as a selection signal. An information multiplex transmission circuit comprising:

According to the second means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, the number of FIFOs to be used can be reduced to one, and a decrease in the use efficiency of the memory can be avoided. In addition, the number of wires in a printed circuit board unit on which an information multiplex transmission circuit is mounted is reduced. It becomes possible to do.

The third means is a dynamic random access memory for storing input data and repetition instruction data.
Memory (hereinafter abbreviated as "DRAM".
micRandom Access Memory ”is a widely used acronym. ), A lower address counter for outputting the lower address and carry of the DRAM,
A FIFO for holding an upper address of the AM and an upper head address storing information in the memory, a NAND circuit for inverting and outputting a logical level of an AND operation of a read enable signal and a write enable signal of the DRAM, An AND circuit for performing an AND operation of the carry output by the lower address counter and the output of the NAND circuit; and an output of the AND circuit and an upper address or an upper head address of the DRAM output by the FIFO. An adder to be added, a delay flip-flop for holding the output of the adder, a first selector for selecting one of the output of the adder and the output of the delay flip-flop and supplying the output to the FIFO, Signal, recording stop signal, head address update signal and D
A logical sum circuit for performing a logical sum operation on the repetition instruction data read from the RAM and supplying it to the selector as a selection signal; a lower address output from the lower address counter and an upper address or an upper head address output from the FIFO; An information multiplexing transmission circuit including a second selector for selecting one and supplying it to the DRAM.

According to the third means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, the number of FIFOs to be used can be reduced to one, a decrease in the use efficiency of the memory can be avoided, and the number of wirings in the printed circuit board unit on which the information multiplex transmission circuit is mounted is reduced. It becomes possible to do.

The fourth means includes a DRAM for storing input data and repetition instruction data, a lower address counter for outputting a lower address and a carry of the DRAM,
A FIFO for holding an upper address and a lower address of a RAM and an upper head address storing information in the memory, a first delay flip-flop for holding a carry outputted by the lower address counter, a read enable signal of the DRAM, A NAND circuit for inverting and outputting a logical level of a logical AND operation of a write enable signal, and a logic for performing a logical AND operation of the carry delayed by the first delay flip-flop and the output of the NAND circuit A product circuit, an adder for adding an upper address, a lower address, and an upper head address output from the AND circuit and the FIFO, a second delay flip-flop holding an output from the adder, A first selector for selecting one of the output of the device and the output of the second delay flip-flop; a recording start signal; A logical sum circuit of a stop signal, a head address update signal, and repetition instruction data read from the DRAM and supplying the result to the first selector as a selection signal, and an output of the second delay flip-flop. A third delay flip-flop to hold, a second selector for selecting one of the output of the first selector and the output of the third delay flip-flop, a lower address output by the lower address counter, A third selector for selecting one of the outputs of the two selectors and supplying the selected output to the FIFO.

According to the fourth means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, the number of FIFOs to be used can be reduced to one, a decrease in the use efficiency of the memory can be avoided, and the number of wires in a printed circuit board unit on which an information multiplex transmission circuit is mounted is reduced. It becomes possible to do.

Fifth means includes a DRAM for storing input data and repetition instruction data, a FIFO for storing an upper address and a lower address of the DRAM, an upper head address for storing information in the DRAM, and an output of the FIFO. LSB of the lower address (“Least Significant Bit”
Abbreviation, which in this case means the lowest bit of the lower address. ), A first AND circuit for performing a logical AND operation of the signal obtained by inverting the LSB of the lower address, the LSB of the lower address, and the lower address selection signal, and carry the output of the first AND circuit. A first delay flip-flop held by a holding signal;
A NAND circuit that inverts and outputs a logical level of a logical AND operation of a read enable signal and a write enable signal of a RAM; and a logical AND operation of an output of the first delay flip-flop and an output of the NAND circuit. A second logical product circuit for performing a logical sum operation of an output of the second logical product circuit and the lower address selection signal; an output of the first logical sum circuit; The DRA output by
An adder for adding the upper address and the lower address or the upper start address of M, a second delay flip-flop holding the output of the adder, and an output of the adder and an output of the second delay flip-flop. A first selector for selecting one, a third AND circuit for performing a logical AND operation of a signal obtained by inverting the logical level of the lower address selection signal and the repetition instruction data output from the DRAM, a recording start signal, A second logical sum circuit for performing a logical sum operation of the recording stop signal and the output of the third logical product circuit and supplying it to the selector as a selection signal; and a third logical sum circuit for holding the output of the second delay flip-flop. And a third selector for selecting one of the output of the first selector and the output of the third delay flip-flop.

According to the fifth means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, the number of FIFOs to be used can be reduced to one, a decrease in the use efficiency of the memory can be avoided, and the number of wires in a printed circuit board unit on which an information multiplex transmission circuit is mounted is reduced. It becomes possible to do.

Sixth means is a memory for storing input data and repetition instruction data, and a first-in first-out memory (hereinafter referred to as a first-in first-out memory) for holding an address of the memory. Abbreviated as “FIFO.” This is “First In Fir”
st Out (Memory) is a widely used abbreviation for the acronym. Also, a FIFO that holds a memory address
Is abbreviated as “memory address FIFO”. ) And a FIFO that holds the start address of the information stored in the memory.
(Hereinafter, abbreviated as “head address FIFO”).
An adder for adding 1 to the output of the memory address FIFO, and selecting one of the output of the adder and the start address output by the start address FIFO to select the memory address FI
A first selector for supplying the signal to the FO, a logical sum circuit for supplying a logical sum operation result of the recording start signal, the recording stop signal and the repetition instruction data read from the memory to the selector as a selection signal, and an output of the adder And a second selector for selecting one of the output of the delay flip-flop and the start address output by the start address FIFO and supplying the selected start address to the start address FIFO. .

According to the sixth means, a plurality of pieces of information are stored in a single memory after the head address assigned to each piece of information, and the repetition instruction data stored at the last address assigned to each piece of information. , Each information can be repeatedly read.

In addition, it is possible to avoid a decrease in the use efficiency of the memory and to reduce the number of wires in a printed circuit board unit on which the information multiplex transmission circuit is mounted.

[0061]

FIG. 1 shows a first embodiment of the present invention, in which an address to be supplied to a memory and a FIFO for holding a head address where information is stored in the memory are shared, thereby enabling information multiplexing. In this configuration, the size of the sending circuit is reduced, and the number of wires between the large-scale integrated circuit, the memory, and the FIFO is reduced.

In FIG. 1, 1 is a memory for storing input data and repetition instruction data, 2a is a FIFO for holding an address to be supplied to the memory 1, and a FIFO for holding a head address of information stored in the memory 1, and 9 is a memory A NAND circuit that inverts and outputs the logical level of the logical AND operation result of the read enable signal and the write enable signal of No. 1;
An adder that adds the output of the NAND circuit 9 to the output of the FIFO 2a (more precisely, “adds the output of the NAND circuit 9 to 16
Addition as a decimal number "should be described, but is omitted because it is thought that the meaning can be understood. Hereinafter, the same is described. ) And 7 are delay flip-flops which hold the output of the adder 4 and delay the head address of each information number to the address timing.
The selector 6 selects one of the output of the delay flip-flop 7 and the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
Is a logical sum circuit that supplies the result of the logical sum operation of the repetition instruction data read from the selector 5 to the selector 5 as a selection signal.

The output of the FIFO 2a is supplied to the address terminal of the memory 1 (indicated as "ADD" in the figure; hereinafter, similarly designated in the figure), and the data of the service information and the repeat instruction data are supplied. The data is supplied to a data input terminal (indicated as “DIN” in the figure; hereinafter, similarly labeled in the figure), written and stored, and the stored service information data and repetition instruction data are transmitted to the data output terminal (FIG. In the following description, the data is read as “DOUT”, and the data of the read service information is output data, and the read repetition instruction data is supplied to the OR circuit 6. Is done.

At the same time as the address is supplied from the FIFO 2 a to the memory 1, the supplied address is added with the output of the NAND circuit 9 in the adder 4, supplied to the selector 5 and supplied to the delay flip-flop 7. Will be retained.

When none of the logical levels of the recording start signal, recording stop signal head address update signal and repetition instruction data is "1", the output of the adder 4 is selected by the selector 5 and supplied to the FIFO 2a.

When any one of the logical levels of the recording start signal, the recording stop signal, the head address update signal and the repetition instruction data is "1", the output of the delay flip-flop 7 is selected by the selector 5 and supplied to the FIFO 2a. Is done.

FIG. 25 is an example of a memory map according to the present invention.

In the example of FIG. 25, 1-word (8-bit) service information data is stored in the input / output data area of the memory, and 1-bit repetition instruction data is stored in the repetition instruction data area.

The information # 1 has the address 0x0000.
The repetition instruction data of the logical level “1” stored in 0 to 0x00ffff and instructing to actually read the information # 1 repeatedly is stored in the repetition instruction data area of the address 0x00fff, and the information # 2 is stored in the address 0x0
1000 to 0x024ff, and the actual repetition instruction data for information # 2 is at address 0x024f
f, and information # 3 is stored at addresses 0x02500 to 0x047ff,
It is assumed that the actual repetition instruction data for the information # 3 is stored in the repetition instruction data area at the address 0x047ff, and the information is not yet stored in the subsequent addresses.

That is, the number of bits of the address is 4 × 5 = 20.
Bit. This means that the address of each piece of information can be represented by 16 bits, as in the prior art.
Up to 16 pieces of information in memory (identified by 4 bits)
Is assumed to be stored.

Accordingly, the number of input / output bits of each component of the information multiplex transmission circuit is as shown in FIG.

In all the embodiments of the invention described hereinafter, the memory map is as shown in FIG.

FIG. 2 shows the information transmission timing of the configuration shown in FIG. 1 (part 1). After the repetition instruction data stored in the memory is read, the information corresponding to the read repetition instruction data is repeatedly transmitted. It shows what you can do.

As shown in FIG. 2 (2), the FIFO 2a of FIG. 1 stores, at the timing of each information number, the start address of the area for storing a plurality of pieces of information in the memory 1 of FIG. Addresses indicating areas for storing a plurality of pieces of information are sequentially stored. Since it is assumed that the inside of the memory 1 is mapped as shown in FIG.
For information # 1 to information # 4, the start address is 0x0
0000, 0x01000, 0x02500, 0x04
800. Then, for information # 1 to information # 3, the address in the first frame of FIG.
00100, 0x024fe, and 0x03000. It should be noted that "0x" in hexadecimal notation and "0" on the MSB side are omitted in the figure (similar omissions will be made in the figure hereinafter), "head" is added to the head address, and "0x" is used for the address. "Read" or "Write" is written in the portion ("Write" is not written in FIG. 2, but "Write" may be written in the subsequent figures). In the figures, the same notation is used.)

Since it is assumed that information # 1 to information # 3 have been written in the memory 1 in FIG. 1 and that information # 4 and thereafter have not been written, the read enable signal is (3) As shown in (1), the logical level is "0" at the address timing of the information # 1 to information # 3 of the FIFO 2a, and it is not assumed that information is written to the memory 1 at this time. 4)
As shown in the figure, the logic level is "1" continuously. That is, in this case, the read address is described at the address timing of (2). Note that the read enable signal and the write enable signal are supplied from a control circuit outside the information multiplex transmission circuit, which is the same as in the prior art.

Since the read enable signal and the write enable signal are given by (3) and (4), though not shown, the result of the NAND operation of the read enable signal and the write enable signal is represented by information in the FIFO 2a. # 1
The logical level becomes "1" at the timing of the address of the information # 3, and the logical level becomes "0" at the timing of the head address of the information # 1 to the information # 3 of the FIFO 2a.

Therefore, as shown in (10), the output of the adder 4 is that the head address of the information # 1 to information # 3 is (2)
The address is the same as the address of (2) but one step forward.

In the first frame of FIG. 2, since the logical levels of the recording start signal, the recording stop signal, the head address update signal and the repeat instruction data are all "0", the selector 5 in FIG. The output of the device 4 is selected and supplied to the FIFO 2a.

Therefore, the input of the FIFO 2a is (12)
As shown in the above, the head address is not changed from (2), and the address is obtained by incrementing the address of (2) by one step.

In the second frame, as shown in (2), the start address and the address equal to the start address of (12) are output from the FIFO 2a, and the output of the adder 4 is as shown in (10). Only the address portion of (2) is incremented by one.

In the second frame, since the address of the information # 2 is 0x024ff, the memory 1 shown in FIG.
The repetition instruction data of the logic level "1" stored in the repetition instruction data area of the address 0x024ff is read. This is indicated by the pulse in the second frame in (9).

Since the read repetition instruction data is supplied to the OR circuit 6 in FIG. 1, the output logic level of the OR circuit 6 changes to "1" at the timing of the pulse of the repetition instruction data, and the selector 5 selects and outputs the output of the delay flip-flop 7.

Here, since the delay flip-flop 7 holds and delays the output of the adder 4 and outputs the start address at the address timing, the timing of the pulse of the repetition instruction data includes the start address of the information # 2. Is output from the delay flip-flop 7.

Therefore, in the input (12) to the FIFO 2a, the head address and the addresses of information # 1 and information # 3 are equal to the output of the adder 4, and the head address is substituted for the address of information # 2.

In the third frame, FIFO2
The head address and the address input to the FIFO 2a in the second frame are output from the frame a. In this frame, the recording start signal, the recording stop signal, the head address update signal, and the repetition instruction data all keep the logical level "0". Therefore, the same operation as in the first frame is performed.

That is, the start address of each piece of information continues to be held, and the address indicating a specific storage location in the area storing each piece of information is a recording start signal, a recording stop signal, a top address update signal, and a repetition instruction. Unless any logic level of data becomes "1", the previous address is advanced. Then, when the instruction data is repeatedly read after reaching the final address of the area for storing information, the information stored in the area is repeatedly transmitted.

FIG. 3 shows the information transmission timing (No. 2) of the configuration shown in FIG. 1. When the recording start signal is supplied at the timing of the designated information, the frame following the frame to which the recording start signal is supplied is transmitted. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

In FIG. 3, it is assumed that the output of the FIFO 2a in FIG. 1 is as shown in (2) in the first frame. Accordingly, the read enable signal is as shown in (3). The basic operation is the same as the operation described in FIG.

The difference between FIG. 3 and FIG. 2 is that, as shown in (5),
At the timing of the information # 4 of the first frame, the logical level of the recording start signal becomes “1”, as shown in (4).
The logic level of the write enable signal changes to “0” at the timing of the information # 4 after the third frame. The reason why the logic level of the write enable signal changes to “0” at the same information timing in the subsequent frames after the logic level of the recording start signal changes to “1” is that the external control of the configuration of FIG. This is set from the circuit, and is the same as the conventional technology.

When the logical level of the recording start signal changes to "1", the selector 5 in FIG. 1 selects and outputs the output of the delay flip-flop 7. At this timing, since the delay flip-flop 7 holds and outputs the head address of the information # 4, as shown in (12), the information # 4 changes at the timing when the logical level of the recording start signal changes to "1". Address 0x04800 is FIFO2
a.

This is because in the second frame the FIF
Output from O2a. In this frame, as shown in (4), since the logical level of the timing write enable signal of the information # 4 becomes "0", the logical level of the output of the NAND circuit 9 becomes "0" even at the timing of the address of the information # 4. 1 ".

Therefore, in the second and subsequent frames, the information #
The addresses 1 to # 4 are incremented by one.

As described above, information # 1 to information # 3 are sequentially read from the memory 1, and information # 4 can be sequentially written to the memory 1.

FIG. 4 shows the operation of stopping the storage of information in the memory, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration of FIG. .

In FIG. 4, it is assumed that the output of the FIFO 2a in FIG. 1 is as shown in (2) in the first frame. Accordingly, the read enable signal is as shown in (3). The basic operation is the same as the operation described in FIG.

The difference between FIG. 4 and FIG. 2 is that, as shown in (6),
At the timing of the information # 4 of the first frame, the logical level of the recording stop signal changes to “1”, and as shown in (8),
At the timing of the information # 4 of the first frame, the logical level of the repetition instruction data changes to "1", and as shown in (7), the head address update signal changes to the logical level "1" at the timing of the head address of the information # 5. To "". The transition of the logic level of these signals is performed by a control circuit outside the information multiplexing transmission circuit of FIG. 1, and is the same as in the prior art.

First, as shown in (8), when the repeat instruction data is supplied to the memory 1 in FIG. 1 at the same time as the write enable signal is supplied to the memory 1 at the timing of the information # 4, the repeat instruction data at the address 0x04fff of the memory 1 is obtained. A signal of logic level "1" is written in the area.

Since the address 0x04fff is the last address of the area for storing the information # 4, the logical level of the recording stop signal changes to "1" at this timing. Thus, the selector 5 of FIG. 1 selects the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
The address of information # 4 supplied to the FO 2a includes (1
As in 2), the start address of information # 4 is substituted.

Further, when the logical level of the head address update signal changes to "1" at the timing of the head address of the information # 5, the address 0x05000 held in the delay flip-flop 7 is selected at the same timing,
As shown in (12), it is supplied to the FIFO 2a.

In the subsequent frames, the logical levels of the recording start signal, recording stop signal, head address update signal, and repetition instruction data continue to be "0".
The most basic operation described in is repeated. In this case, since the writing of the information # 4 has been completed, the logical level of the read enable signal changes to “0” at the timing of the address of the information # 4 (this is also true).
It is set from a control circuit outside the information multiplexing transmission circuit, but is the same as in the prior art. ), Since the head address 0x05000 is set for the information # 5, only the head address continues to be held.

As described above, transmission of the information # 4 becomes possible, and preparation for writing data to the information # 5 is made.

The same function as that of the conventional information multiplex transmission circuit is realized by the configuration shown in FIG. According to the configuration shown in FIG. 1, it is possible to supply an address from one FIFO and store a plurality of pieces of information in a single memory, and to store a plurality of pieces of information in a single memory. Use efficiency is increased.

Also, according to the configuration of FIG.
When a circuit other than O is configured by a large-scale integrated circuit, the wiring between the large-scale integrated circuit and the FIFO, between the FIFO and the memory, and between the input and output of the memory is 20 × 3 + 8 × 2 = 76.

On the other hand, in the configuration of FIG. 26, four memories are used to store four pieces of information. Therefore, when a circuit other than the memory is configured by a large-scale integrated circuit, the four memories and the large-scale integrated circuit are used. 16 × 4 = 64 wires are required between the integrated circuit and the input data wires and the output data wires are also required to be the same 64 wires. Therefore, the number of wires around the memory on the printed board unit is 64 × 2 = 128 lines.

Therefore, according to the configuration of FIG. 1, the number of wires between the large-scale integrated circuit and the FIFO, between the FIFO and the memory, and between the input and output of the memory can be reduced.

FIG. 5 shows a second embodiment of the present invention, in which the lower address of the memory is generated by a counter common to all information, thereby retaining the address of the memory and the head address of the information stored in the memory. The number of input / output signal lines of the FIFO is reduced.

The number of bits of the upper address and the lower address can be set arbitrarily. However, since the hexadecimal representation is assumed, the upper address and the lower address are preferably integer multiples of 4 bits. 12 bits,
An example will be described in which the lower address is 8 bits.

In FIG. 5, reference numeral 1 denotes a memory for storing input data and repetition instruction data, and 2a denotes upper 12 bits of an address to be supplied to the memory 1 and upper 12 bits of a head address of information stored in the memory 1. FI to keep
FO, 10 is a lower address counter that counts lower addresses of the memory 1, 9 is a NAND circuit that inverts and outputs a logical level of a logical AND operation result of a read enable signal and a write enable signal of the memory 1, and 11 Is
An AND circuit that performs an AND operation on the carry output by the lower address counter 10 and the output of the NAND circuit 9
Is an adder that adds the output of the AND circuit 11 to the output of the FIFO 2a. 7 holds the output of the adder 4 and delays the timing of outputting the upper 12 bits of the head address to the timing of holding the upper address. The delay flip-flop 5 to be selected selects one of the output of the adder 4 and the output of the delay flip-flop 7 and supplies it to the FIFO 2a. The selector 6 is a recording start signal, a recording stop signal, a head address update signal and a memory 1 This is a logical sum circuit that supplies the result of the logical sum operation of the repetition instruction data read from the selector 5 to the selector 5 as a selection signal.

Then, the FIFO is connected to the address terminal of the memory 1.
The 12-bit upper address output from O2a and the 8-bit lower address output by the lower address counter 10 are supplied, and the data of the service information and the repetition instruction data are supplied to the data input terminal, written and stored. The service information data and the repetition instruction data are read from the data output terminal, the read service information data becomes output data, and the read repetition instruction data is supplied to the OR circuit 6.

Then, 12 is transferred from the FIFO 2a to the memory 1.
When the upper address of the bit is supplied, the memory 1
Are added to the output of the AND circuit 11 in the adder 4 and supplied to the selector 5 and held in the delay flip-flop 7.

If any of the logical levels of the recording start signal, recording stop signal, head address update signal and repetition instruction data is not "1", the output of the adder 4 is selected by the selector 5 and supplied to the FIFO 2a. .

When the logical level of any one of the recording start signal, recording stop signal, head address update signal and repetition instruction data is "1", the output of the delay flip-flop 7 is selected by the selector 5 and supplied to the FIFO 2a. Is done.

FIG. 6 shows the basic operation of the configuration of FIG. 5 and the operation of repeatedly transmitting the information after reading the repetition instruction data at the information transmission timing (1) of the configuration of FIG. .

As shown in FIG. 6 (4), the FIFO 2a of FIG. 5 stores, at the timing of each information, the upper 12 bits of the top address of the area for storing a plurality of information in the memory 1 of FIG. The upper 12 bits of an address indicating an area for storing a plurality of pieces of information in 1 are sequentially held. Since the inside of the memory 1 is assumed to be mapped as shown in FIG. 25, for information # 1 to information # 4, the 12 bits of the head address are 0x000, 0x0
10, 0x025 and 0x048. And information #
For 1 to information # 3, the addresses in the first frame in FIG. 6 are 0x001, 0x024, 0x030
It is assumed that

Since it is assumed that information # 1 to information # 3 have been written in the memory 1 of FIG. 5 and that information # 4 and thereafter have not been written, the read enable signal is (5) As shown in (1), the logical level is "0" at the address timing of the information # 1 to information # 3 of the FIFO 2a, and it is not assumed that the information is written to the memory 1 at this time. 6)
As shown in the figure, the logic level is "1" continuously. That is, the read address is described in the address timing of (4).

Since the read enable signal and the write enable signal are given by (5) and (6), although not shown, the result of the NAND operation of the read enable signal and the write enable signal is represented by information in the FIFO 2a. # 1
The logical level becomes "1" at the timing of the address of the information # 3 through the information # 3, and the logical level becomes "0" at the timing of the head address of the information # 1 through the information # 3 of the FIFO 2a.

Now, in FIG. 6, (3) is the count value of the lower address counter 10 in FIG. The lower address counter 10 increments the count value once per frame by the clock shown in (2), but it is assumed to be 0xfe in the first frame.

In the first frame, the count value of the lower address counter 10 in FIG. 5 is 0xfe,
Since the lower address counter 10 does not output a carry, the logical level of the output of the AND circuit 11 is “0”.

Therefore, the output of the adder 4 of FIG. 5 in the first frame is the same as that of (4) as shown in (12).

At this time, since all logical levels of the recording start signal, recording stop signal, head address update signal and repetition instruction data are "0", the selector 5 in FIG. Supply to FIFO2a. Accordingly, in the first frame, the upper 12 bits of the top address and the upper 12 bits of the address supplied to the FIFO 2a are provided.
The bit is equal to (4) as in (14) and is output from FIFO 2a in the second frame.

In the second frame, the count value of the lower address counter 10 is 0xf as shown in (3).
Although not shown in the figure, the lower address counter 10 outputs a carry, since it advances to f.

The output of the NAND circuit 9 is as described above, and since the logical level of the carry of the lower address counter 10 is "1", the output of the adder 4 is as shown in (12). The upper 12 bits are the same as (4), and the upper 12 bits of the address are advanced by one.

Then, the delay flip-flop 7 of FIG. 5 delays the output of the adder 4 and outputs it, as shown in (13).

As described with reference to FIG. 25, the repetition instruction data of the logic level "1" is stored in the area of the repetition instruction data at the address 0x024ff in the memory 1 of FIG. Since the address of the memory 1 is 0x024ff at the timing of the information # 2 in the second frame, the instruction data is repeatedly read from the memory 1. This is indicated by the pulse in the second frame of (11).

Therefore, at this timing, the logical sum circuit 6
Transitions to "1", and the selector 5 selects and outputs the output of the delay flip-flop 7. On the other hand, since the logic level of the output of the OR circuit 6 is "0" at other timings of the second frame, the top address supplied by the selector 5 to the FIFO 2a and the upper 12 bits of the address are advanced by one. The upper 12 bits of the address of information # 2 are 0x010, which is equal to the upper 12 bits of the head address. This is shown at the time corresponding to the second frame in (14).

Since the input of the FIFO 2a is output from the FIFO 2a in the third frame, information # 1
And the information # 3 has the same upper address as the second frame, and the information # 2 has been changed to 0x010 which is the upper 12 bits of the head address.

That is, by reading the instruction data repeatedly in the second frame, the information # 2 returns to the head address and the data of the service information is read, so that the information # 2 can be repeatedly transmitted. it can. This is the same for other information.

The upper address is incremented only when the count value of the lower address counter 10 becomes 0xff, but the lower address counter 10 increments the count value for each frame. The address obtained by combining the addresses is incremented for each frame.

FIG. 7 shows the information transmission timing (No. 2) of the configuration shown in FIG. 5. When the recording start signal is supplied at the timing of the designated information, the next frame of the frame to which the recording start signal is supplied is shown. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

In the first frame of FIG. 7, it is assumed that the output of the lower address counter 10 of FIG. 5 is as shown in (3) and the output of the FIFO 2a is as shown in (4). Therefore, the read enable signal is as shown in (5). The basic operation is the same as the operation described in FIG.

The difference between FIG. 7 and FIG. 6 is that, as shown in (7),
At the timing of the information # 4 of the first frame, the logical level of the recording start signal becomes “1”, and as shown in (6),
The logic level of the write enable signal changes to “0” at the timing of the information # 4 after the third frame.

When the logical level of the recording start signal changes to "1", the selector 5 of FIG. 5 selects and outputs the output of the delay flip-flop 7. At this timing, since the delay flip-flop 7 holds and outputs the upper 12 bits of the head address of the information # 4, the information is output at the timing when the logical level of the recording start signal transits to "1" as shown in (14). The upper 12 bits 0x048 of the head address of # 4 are supplied to the FIFO 2a of FIG.

In the second frame, the FIF
Output from O2a. In this frame, since the lower address counter 10 does not output a carry, the output of the adder 4 becomes equal to the output of the FIFO 2a. Further, since the logical level of any of the recording start signal, the recording stop signal, the head address update signal, and the repetition instruction data does not become "1", the head address held in the FIFO 2a and the upper 12 bits of the address do not change.

However, since the lower address counter 10 increments the count value for each frame, an address obtained by combining the upper address and the lower address is incremented for each frame.

As described above, the information # 1 to the information # 3 are sequentially read from the memory 1, and the information # 4 is sequentially written to the memory 1.

FIG. 8 shows the operation of stopping the storage of information in the memory, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration of FIG. .

In FIG. 8, in the first frame, the output of the lower address counter 10 of FIG. 5 is as shown in (3), and the output of the FIFO 2a is as in (4). Accordingly, the read enable signal is as shown in (5), and the write enable signal is as shown in (6). The basic operation is the same as the operation described in FIG.

The difference between FIG. 8 and FIG. 6 is that, as shown in (8),
At the timing of the first frame information # 4, the logical level of the recording stop signal transitions to "1", and as shown in (10), at the timing of the first frame information # 4, the logical level of the repeat instruction data changes. "1", and as shown in (9), the head address update signal changes to the logical level "1" at the timing of the head address of the information # 5.

First, as shown in (10), the instruction data is repeatedly supplied to the memory 1 in FIG. 1 at the timing of the information # 4 of the first frame, and at the same time, as shown in (6).
When the write enable signal is supplied to the memory 1, the upper 12 bits of the address of the information # 4 are 0x04f and the lower 8 bits are 0xff.
A signal of logic level "1" is written in the repeat instruction data area of x04fff.

Since the address 0x04fff is the last address of the area for storing the information # 4, the logical level of the recording stop signal changes to "1" at this timing. Thus, the selector 5 in FIG. 5 selects the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
As shown in (14), the upper 12 bits of the top address of the information # 4 are assigned to the upper 12 bits of the address of the information # 4 supplied to the FO 2a.

Further, when the logic level of the start address update signal changes to "1" at the timing of the start address of the information # 5, the upper 12 bits 0x050 of the address held in the delay flip-flop 7 are selected at the same timing. Then, as shown in (14), it is supplied to the FIFO 2a.

In the subsequent frames, the logical levels of the recording start signal, recording stop signal, head address update signal, and repetition instruction data continue to be "0".
The most basic operation described in is repeated. In this case, since the writing of the information # 4 has been completed, the logical level of the read enable signal changes to “0” at the timing of the address of the information # 4. Since the head address 0x05000 has been set for the information # 5, only the head address continues to be held.

As described above, transmission of the information # 4 becomes possible, and preparation for writing data to the information # 5 is made.

The same function as that of the conventional information multiplex transmission circuit can be realized by the configuration shown in FIG. or,
According to the configuration of FIG. 5, the lower address is generated by a common counter, and the upper address of the memory and the upper head address storing the information in the memory are stored in one FIFO, so that a plurality of addresses are stored in a single memory. Since information can be stored and a plurality of pieces of information are stored in a single memory, the use efficiency of the memory is improved.

Further, according to the configuration of FIG.
In the case where a large-scale integrated circuit other than O is used, the number of wirings between the large-scale integrated circuit and the FIFO, between the FIFO and the memory, and between the input and output of the memory is 12 × 3 + 8 × 3 = 60.
The number of wirings can be reduced as compared with the configuration of FIG.

FIG. 9 shows a third embodiment of the present invention, in which the lower address of the memory is generated by a counter common to all information, thereby retaining the address of the memory and the head address of the information stored in the memory. In addition to reducing the number of input / output signal lines of the FIFO, dynamic memory
Random access memory ("Dynamic RandomAccess
The acronym “Memory” is abbreviated as “DRAM”.
Since it is a very common abbreviation, it will be referred to as "DRAM" hereinafter. ) Is applied so that an upper address and a lower address can be given alternately. Here, a so-called synchronous dynamic random access memory (Synchronous Dynamic Random A
ccess Memory. Abbreviated as “SDRAM”. ) Is naturally included in the DRAM.

Here, an example in which the upper address is 12 bits and the lower address is 8 bits will be described.

In FIG. 9, 1a is a DRAM for storing input data and repetition instruction data, and 2a is a DRAM.
1a and a FIFO holding the upper 12 bits of the top address of the information stored in the DRAM 1a.
0 is a lower address counter that counts lower addresses of the DRAM 1a, 9 is a NAND circuit that inverts and outputs the logical level of the logical AND operation result of the read enable signal and the write enable signal of the DRAM 1a, and 11 is
An AND circuit that performs an AND operation on the carry output by the lower address counter 10 and the output of the NAND circuit 9
Is an adder that adds the output of the AND circuit 11 to the output of the FIFO 2a. 7 holds the output of the adder 4 and delays the timing of outputting the upper head address of each information number to the timing of the upper address. The delay flip-flop 5 selects one of the output of the adder 4 and the output of the delay flip-flop 7 and supplies it to the FIFO 2a. The selector 6 is a recording start signal, a recording stop signal, a head address update signal and a read from the DRAM 1a. The OR circuit 12 supplies the result of the OR operation of the repeated instruction data to the selector 5 as a selection signal. The OR circuit 12 outputs the lower 8 bits of the address output from the lower address counter 10 and the FIFO 2
a selector for selecting one of the upper 12 bits of the address output by a and supplying it to the address terminal of the DRAM 1a.

Then, F is connected to the address terminal of the DRAM 1a.
A 12-bit upper address which is the output of the IFO 2a;
The 8-bit lower address output from the lower address counter 10 is alternately supplied, the service information data and the repeat instruction data are supplied to the data input terminal and written, and the stored service information data and the repeat instruction data are stored in the data input terminal. The service information data read from the output terminal becomes output data, and the read repetition instruction data is supplied to the OR circuit 6.

The 12-bit upper address is supplied from the FIFO 2a to the DRAM 1a, and at the same time, the upper address is added with the output of the AND circuit 11 in the adder 4 and supplied to the selector 5 and the delay flip-flop 7 Is held.

That is, in the configuration of FIG. 9, the upper address and the lower address are alternately supplied to the DRAM 1a.
In this configuration, a selector 12 is inserted between the memory 2 and the FIFO 2a and the lower address counter 10.

If none of the logical levels of the recording start signal, recording stop signal, head address update signal and repetition instruction data is "1", the output of the adder 4 is selected by the selector 5 and supplied to the FIFO 2a. .

When the logical level of any one of the recording start signal, recording stop signal, head address update signal and repetition instruction data is "1", the output of the delay flip-flop 7 is selected by the selector 5 and supplied to the FIFO 2a. Is done.

FIG. 10 shows the basic operation of the configuration of FIG. 9 and the operation of repeatedly transmitting the information after reading the repetition instruction data at the information transmission timing (1) of the configuration of FIG. .

As shown in FIG. 10 (4), the FIFO 2a of FIG.
The upper 12 bits of the top address of the area storing a plurality of information in the AM 1a and the upper 12 bits of the address indicating the area storing the plurality of information in the DRAM 1a are sequentially output. Since it is assumed that the inside of the DRAM 1a is mapped as shown in FIG. 25, the 12 bits of the head address are 0x00 for the information # 1 to the information # 4.
0, 0x010, 0x025, and 0x048. Then, for information # 1 to information # 3, the addresses in the first frame in FIG. 9 are 0x001, 0x024,
It is assumed that it is 0x030.

On the other hand, it is assumed that the count value of the lower address counter 10 in the first frame is 0xfe.

In the configuration shown in FIG. 9, the selector 12 selects one of the start address, the upper address and the lower address according to the logical level of the lower address selection signal shown in FIG. 10 (5), and supplies it to the address terminal of the DRAM 1a. Is supplied with an address as shown in (6).

Information # 1 is stored in DRAM 1a of FIG.
Since it is assumed that the information # 3 has been written and the information # 4 and the subsequent information have not been written, the read enable signal becomes the information # of the FIFO 2a as shown in (7).
The logic level is “0” at the timing of the address of 1 to information # 3. Further, since it is not assumed that information is written to the DRAM 1a, the write enable signal has the logic level of "1" continuously as shown in (8). That is, the read address is described in the address timing of (4) or (6).

Since the read enable signal and the write enable signal are given by (7) and (8), although not shown, the result of the NAND operation of the read enable signal and the write enable signal is represented by the information in the FIFO 2a. # 1
The logical level becomes "1" at the timing of the address of the information # 3 through the information # 3, and the logical level becomes "0" at the timing of the head address of the information # 1 through the information # 3 of the FIFO 2a.

According to the above assumption, in the first frame, the count value of lower address counter 10 in FIG. 9 is 0xfe, and lower address counter 10 does not output carry, so that the logical level of the output of AND circuit 11 is It is "0".

Therefore, the output of the adder 4 of FIG. 9 in the first frame is the same as that of (4) as shown in (14).

At this time, since all logical levels of the recording start signal, recording stop signal, head address update signal and repetition instruction data are "0", the selector 5 in FIG. Supply to FIFO2a. Accordingly, in the first frame, the upper 12 bits of the top address and the upper 12 bits of the address supplied to the FIFO 2a are provided.
The bits look like (16), which are output from FIFO 2a in the second frame.

In the second frame, the count value of the lower address counter 10 is 0xf as shown in (3).
Although not shown, the lower address counter 10 in FIG. 9 outputs a carry, since it advances to f.

The output of the NAND circuit 9 is as described above, and the logical level of the carry of the lower address counter 10 becomes "1". Therefore, the output of the adder 4 becomes as shown in (14). The upper 12 bits are the same as (4), and the upper 12 bits of the address are advanced by one.

Then, the delay flip-flop 7 sets (1
As shown in 5), the output of the adder 4, that is, (14) is delayed and output.

As described with reference to FIG. 25, the repetition instruction data of the logic level "1" is stored in the area of the repetition instruction data at the address 0x024ff of the DRAM 1a in FIG. Since the address of the DRAM 1a becomes 0x024ff at the timing of the information # 2 in the second frame, the instruction data is repeatedly read from the DRAM 1a. This is (13)
In the second frame of FIG.

Therefore, at this timing, the logical sum circuit 6
Transitions to "1", and the selector 5 selects and outputs the output of the delay flip-flop 7. On the other hand, at the other timings of the second frame, the logical level of the output of the OR circuit 6 is "0", so that the leading address supplied to the FIFO 2a by the selector 5 and the upper 12 bits of the address are advanced by one. And the upper 12 bits 0x010 of the head address are substituted for the upper 12 bits of the address of the information # 2. This is shown at the time corresponding to the second frame of (16).

Since the input of the FIFO 2a is output from the FIFO 2a in the third frame, information # 1
And the information # 3 has the same upper address as the second frame, and the information # 2 has been changed to 0x010 which is the upper 12 bits of the head address.

That is, by reading the instruction data repeatedly in the second frame, the information # 2 returns to the head address and the data of the service information is read, so that the information # 2 can be repeatedly transmitted. . This is the same for other information.

The upper address is incremented only when the count value of the lower address counter 10 is 0xff. However, the lower address counter 10 increments the count value for each frame. The combined address is incremented for each frame.

FIG. 11 shows the information transmission timing (No. 2) of the configuration shown in FIG. 9. When the recording start signal is supplied at the timing of the designated information, the next frame following the frame to which the recording start signal is supplied is displayed. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

In the first frame of FIG.
The output of the lower address counter 10 is as shown in (3), the output of the FIFO 2a is as shown in (4), and the address shown in (6) is supplied to the memory by the lower address selection signal (5). It is assumed that Accordingly, the read enable signal is as shown in (7). The basic operation is the same as the operation described in FIG.

The difference between FIG. 11 and FIG. 10 is that, as shown in (9), the logical level of the recording start signal becomes “1” at the timing of the information # 4 of the first frame, and as shown in (8), The logic level of the write enable signal changes to “0” at the timing of information # 4 in the second and subsequent frames.

When the logical level of the recording start signal changes to "1", the selector 5 in FIG. 9 selects and outputs the output of the delay flip-flop 7. At this timing, since the delay flip-flop 7 holds the upper 12 bits of the head address of the information # 4, the information # 4 changes at the timing when the logical level of the recording start signal changes to "1" as shown in (16). Upper 12 bits 0 of start address of 4
x048 is supplied to the FIFO 2a of FIG.

In the second frame, the FIF
Output from O2a. In this frame, since the lower address counter 10 does not output a carry, the output of the adder 4 becomes equal to the output of the FIFO 2a. In addition, since the logical level of any of the recording start signal, recording stop signal, head address update signal and repetition instruction data does not become "1", the head address held in the FIFO 2a and the upper 12 bits of the address are shown in (16). As described in (4).

However, since the lower address counter 10 increments the count value for each frame, an address obtained by combining the upper address and the lower address is incremented for each frame.

In this way, information # 1 to information # 3 are sequentially read from DRAM 1a, and information # 4 is
The data is sequentially written to the RAM 1a.

FIG. 12 shows the operation of stopping the storage of information in the DRAM 1a, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration of FIG. .

In the first frame of FIG.
The output of the lower address counter 10 is as shown in (3), the output of the FIFO 2a is as shown in (4), and the DRAM 1a is output by the lower address selection signal (5).
Is supplied with the address shown in (6). Accordingly, the read enable signal is as shown in (7). The basic operation is the same as the operation described in FIG.

The difference between FIG. 12 and FIG. 10 is that the logical level of the recording stop signal changes to “1” at the timing of the information # 4 of the first frame as shown in (10), and as shown in (12). At the timing of the information # 4 of the first frame, the logical level of the repeat instruction data changes to “1” and (1
As shown in 1), the head address update signal transitions to the logical level "1" at the timing of the head address of the information # 5.

First, as shown in (10), the instruction data is repeatedly supplied to the DRAM 1a in FIG. 1 at the timing of the information # 4 of the first frame, and at the same time, the write enable signal is supplied to the DRAM 1a as shown in (8). Then, the upper 12 bits of the address of information # 4 are now 0x0
4f, the lower 8 bits are 0xff.
The signal of the logic level "1" is written in the repetition instruction data area of the address 0x04fff of "a".

Since the address 0x04fff is the last address of the area for storing the information # 4, the logical level of the recording stop signal changes to "1" at this timing. As a result, the selector 5 of FIG. 9 selects the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
As shown in (16), the upper 12 bits of the head address of the information # 4 are assigned to the upper 12 bits of the address of the information # 4 supplied to the FO 2a.

Further, when the logical level of the head address update signal changes to "1" at the timing of the head address of the information # 5, the upper 12 bits 0x050 of the address held in the delay flip-flop 7 are selected at the same timing. Then, as shown in (16), it is supplied to the FIFO 2a.

In the subsequent frames, the logical levels of the recording start signal, recording stop signal, head address update signal, and repetition instruction data continue to be "0".
0, the most basic operation described above is repeated. In this case, since the writing of information # 4 has been completed,
The logical level of the read enable signal transitions to “0” at the timing of the address of the information # 4,
5 is the stage where the start address 0x05000 has been set, so that only the start address is kept held.

As described above, transmission of information # 4 is enabled, and preparation for writing data to information # 5 is ready.

The same function as that of the conventional information multiplex transmission circuit can be realized by the configuration shown in FIG. Further, according to the configuration of FIG. 9, the lower address is generated by a common counter, the upper head address and the upper address are held in one FIFO, and the output of the counter and the output of the FIFO are alternately supplied to the DRAM. This makes it possible to store multiple pieces of information in a single DRAM,
Since a plurality of pieces of information are stored in the DRAM, the use efficiency of the DRAM is improved.

According to the configuration shown in FIG. 9, when a large-scale integrated circuit is used to configure components other than the DRAM 1a and the FIFO, the number of wires between the large-scale integrated circuit and the FIFO, between the FIFO and the DRAM 1a, and between the input and output of the DRAM 1a is 12 × 3 + 8 × 2 =
52, and the number of wirings can be reduced as compared with the configuration of FIG.

FIG. 13 shows a fourth embodiment of the present invention.
The lower address is also held in the FIFO so that the output of the FIFO can be directly connected to the address terminal of the DRAM, so that between the large-scale integrated circuit and the FIFO, between the FIFO and the DRAM.
In this configuration, the number of lines between the input and output of the DRAM is reduced.

Here, an example in which the upper address is 12 bits and the lower address is 8 bits will be described.

In FIG. 13, 1a is a DRAM for storing input data and repetition instruction data, and 2a is a DRA.
The FIFO 10 holding the upper address of M1a, the upper 12 bits of the head address of the information stored in the DRAM 1a, and the lower 8 bits of the address of the memory 1 has a DRA.
The lower address counter 13 counts the lower address of M1a, 13 is a delay flip-flop holding the carry output from the lower address counter 10, and 9 is a DRA.
A NAND circuit 11 for inverting and outputting the logical level of the AND operation result of the read enable signal and the write enable signal of M1a; 11 denotes a carry of the lower address counter 10 output by the delay flip-flop 13 and a NAND circuit An AND circuit for performing an AND operation on the output of 9 and 4
The adder 7 adds the output of the AND circuit 11 to the output of the FIFO 2a as a binary number. The adder 7 holds the output of the adder 4 and determines the timing of outputting the upper address.
, A selector for selecting and outputting one of the output of the adder 4 and the output of the delay flip-flop 7, and 6 a recording start signal, a recording stop signal, DRAM
An OR circuit for supplying the result of the OR operation of the repetition instruction data read from 1a to the selector 5 as a selection signal. The OR circuit 14 holds the output of the delay flip-flop 7 and adjusts the timing of the start address to the output of A delay flip-flop for delaying to the timing of the lower address, a selector 15 for selecting one of the output of the selector 5 and the output of the delay flip-flop 14 using the head address update signal as a selection signal, and a selector 12 for outputting the lower address selection signal. As a selection signal, the lower address counter 10
Select one of the lower 8 bits of the address output by the selector and the upper 12 bits of the address output by the selector 15 and
This is a selector to be supplied to the IFO 2a.

Then, F is connected to the address terminal of the DRAM 1a.
12-bit upper address, which is the output of IFO 2a, and 8
The lower address of the bit is supplied alternately, the data of the service information and the repeat instruction data are supplied to the data input terminal and written, and the stored data of the service information and the repeat instruction data are read from the data output terminal,
The read service information data becomes output data, and the read repetition instruction data is supplied to the OR circuit 6.

At the same time when the address is supplied from the FIFO 2a to the DRAM 1a, the address is added with the output of the AND circuit 11 in the adder 4, supplied to the selector 5, and held in the delay flip-flop 7.

When any of the logical levels of the recording start signal, recording stop signal, repetition instruction data, head address update signal and lower address selection signal is not "1",
The output of the adder 4 is selected by the selector 5, the selector 15, and the selector 12, and is supplied to the FIFO 2a.

When the logical level of any one of the recording start signal, the recording stop signal, and the repetition instruction data is "1", the output of the delay flip-flop 7 is selected by the selector 5.

In the selector 15, when the logical level of the head address update signal is "0", the output of the selector 5 is selected. When the logical level of the head address update signal is "1", the output of the delay flip-flop 14 is selected. The selected signal is supplied to one input terminal of the selector 12.

The output of the lower address counter 10 is supplied to the other input terminal of the selector 12. When the logical level of the lower address selection signal is "0", the output of the selector 15 is selected. Is "1", the output of the lower address counter 10 is selected, supplied to the FIFO 2a, and held.

FIG. 14 shows the basic operation of the configuration of FIG. 13 and the operation of repeatedly transmitting the information after reading the repeat instruction data at the information transmission timing (part 1) of the configuration of FIG. .

The FIFO 2a shown in FIG.
As shown in FIG. 13, at the timing of each information, the upper 12 bits of the top address of the area storing the plurality of information in the DRAM 1a and the upper 12 bits of the address indicating the area storing the plurality of information in the DRAM 1a in FIG. And D
Lower 8 bits of an address indicating an area for storing a plurality of pieces of information in the RAM 1a are sequentially stored. DRAM1
In FIG. 25A, it is assumed that mapping is performed as shown in FIG. 25. Therefore, for information # 1 to information # 4, the upper 12 bits of the top address are 0x000, 0x010,
0x025 and 0x048. Then, for information # 1 to information # 3, the upper 12 bits of the address in the first frame in FIG. 9 are 0x001, 0x024,
It is assumed that it is 0x030.

On the other hand, the lower address counter 10 is set to (3)
, And the count value in the first frame is 0xff.

In the configuration shown in FIG. 13, the lower address output from lower address counter 10 is supplied to the address terminal of DRAM 1a with a delay of one frame in FIFO 2a. That is, as in the first frame of FIG. 14, the count value of the lower address counter 10 is 0x.
When it is ff, the lower address output from the FIFO 2a is 0xfe.

The information # is stored in the DRAM 1a of FIG.
Since it is assumed that information 1 to information # 3 have been written and information # 4 and subsequent information have not been written, the read enable signal is transmitted from the information # 1 to information # 3 of the FIFO 2a as shown in (5). The logic level is "0" at the timing of the address. Further, since it is not assumed that information is written to the DRAM 1a, the write enable signal has the logic level "1" continuously as shown in (6). That is, the read address is described in the address timing of (4).

Since the read enable signal and the write enable signal are given by (5) and (6), they are not shown, but the result of the NAND operation of the read enable signal and the write enable signal is represented by the information in the FIFO 2a. # 1
The logical level becomes "1" at the timing of the address of the information # 3 through the information # 3, and the logical level becomes "0" at the timing of the head address of the information # 1 through the information # 3 of the FIFO 2a.

According to the above assumption, in the first frame, the count value of lower address counter 10 in FIG. 13 is 0xff, and lower address counter 10 outputs a carry.

However, in the first frame, the carry output from lower address counter 10 is not output from delay flip-flop 13, so that the logical level of the output of AND circuit 11 is "0".

Therefore, FIG. 13 in the first frame
Is the same as that of (4), as shown in (12).

At this time, since all logical levels of the recording start signal, the recording stop signal, and the repetition instruction data are "0", the selector 5 in FIG. 13 selects and outputs the output of the adder 4. Then, at this time, since the logical level of the head address update signal is also “0”, the selector 15 selects and outputs the output of the selector 5. That is, the output of the selector 15 in the first frame is equal to the output of the adder 4 shown in (12).

By the way, as shown in (15), the lower address selection signal supplied as a selection signal to the selector 12 has a logical level "1" only at the timing of the lower address in each information address, and The logical level is “0” at the timing of the address and the upper address.

Therefore, the output of the selector 12 is equal to the output of the adder 4 when the logic level of the lower address selection signal is "0", and the output of the lower address counter 10 when the logic level of the lower address selection signal is "1". Equal to output. That is, in the address supplied to the FIFO 2a, only the lower address is incremented by 1 to become 0xff, and the upper 12 bits of the head address and the upper 12 bits of the address are equal to the output of the adder 4, as shown in (16). . This is 2
The data is output from the FIFO 2a in the second frame.

In the second frame, the carry output from the lower address counter 10 is output from the delay flip-flop 13, so that the logical level of the output of the AND circuit 11 is determined by the timing of the upper 12 bits of the top address. "0" and "1" at the timing of the upper 12 bits and lower 8 bits of the address.

Since the output of the AND circuit 11 is added to the output of the FIFO 2a as a binary number in the adder 4, the output of the adder 4 becomes the upper one of the top address as shown in (12).
The two bits are the same as the output of FIFO 2a, and the upper 12 bits and lower 8 bits of the address are
Output is incremented by one.

That is, the carry is output from the lower address counter 10 when the count value of the lower address counter 10 is 0xff, but the address output from the FIFO 2a is incremented by one.
Is 0x00, which is one frame behind the timing at which the carry is output, so that the delay flip-flop 13 absorbs this timing shift.

The output of the adder 4 is output from the delay flip-flop 7 with a delay of one timing as shown in (13), and is output from the delay flip-flop 14 with a further delay as shown in (14).

In the second frame, the address corresponding to information # 2 is 0x024ff,
In the repeat instruction data area of the address 0x024ff of AM1a, the logic level “1” is set as the repeat instruction data.
, The instruction data is repeatedly read. This is indicated by the pulse in (11).

The logic level of the repetition instruction data is "1"
At this timing, the logic level of the output of the OR circuit 6 changes to “1” at this timing, and the selector 5 selects the output of the delay flip-flop 7. Further, at this time, the logical level of the head address update signal is "0", so that the selector 15 selects and outputs the output of the selector 5 at the selector 15.

Since the lower address selection signal supplied as a selection signal to the selector 15 makes a transition of the logic level as shown in (15), the selector 12 selects and outputs the signal when the logic level of the repetition instruction data is "1". When "0", the output of the adder 4 and the logic level of the repeat instruction data are "1", and when the logic level of the lower address selection signal is "0", regardless of the output of the delay flip-flop 7 and the logic level of the repeat instruction data. When the logical level of the lower address selection signal is "1", the lower address counter 10
Is the output of Therefore, in the second frame, the address supplied from the selector 12 to the FIFO 2a is (16)
It looks like

That is, the upper 12 bits of the head address are substituted for the upper 12 bits of the address of information # 2. Then, when this address is used in the third frame,
Output from O2a.

In the third frame, the logical levels of the recording start signal, the recording stop signal, the head address update signal, and the repeat instruction data are "0", so that the same operation as in the first frame is performed. The address corresponding to is advanced.

That is, in FIG. 14, information # 2 has been described as an example. However, it can be seen that the address can be returned to the head address by repeatedly reading the instruction data, whereby the information can be repeatedly transmitted.

Note that the upper address is incremented only when the count value of the lower address counter 10 is 0x00, but the lower address counter 10 increments the count value for each frame. The combined address is incremented for each frame.

FIG. 15 shows the information transmission timing (No. 2) of the configuration shown in FIG. 13. When the recording start signal is supplied at the timing of the designated information, the frame next to the frame supplied with the recording start signal is transmitted. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

In the first frame of FIG.
It is assumed that the output of the lower address counter 10 of No. 3 is as shown in (3), the output of the FIFO 2a is as shown in (4), and the address shown in (4) is supplied to the DRAM 1a. Therefore, the read enable signal is as shown in (5). And the basic operation is
4 is the same as the operation described in FIG.

The difference between FIG. 15 and FIG. 14 is that the logical level of the recording start signal becomes “1” at the timing of the information # 4 of the first frame, as shown in (7), and as shown in (6), The logic level of the write enable signal changes to “0” at the timing of information # 4 in the second and subsequent frames.

When the logical level of the recording start signal changes to "1", the selector 5 in FIG. 13 selects and outputs the output of the delay flip-flop 7. At this timing, since the delay flip-flop 7 holds the upper 12 bits of the head address of the information # 4, the information # 4 changes at the timing when the logical level of the recording start signal changes to "1" as shown in (16). Upper 12 bits 0 of start address of 4
x048 is supplied to the FIFO 2a of FIG.

This is because in the second frame the FIF
Output from O2a. In this frame, since the lower address counter 10 does not output a carry, the output (12) of the adder 4 becomes equal to the output (4) of the FIFO 2a. Since the logical level of any of the recording start signal, the recording stop signal, the head address update signal and the repetition instruction data does not become "1", the head address held in the FIFO 2a and the upper 12 bits (16) of the address are stored in the FIFO.
This is the same as the output (4) of O2a.

However, since the lower address counter 10 increments the count value for each frame and is selected by the selector 12 by the lower address selection signal, the address obtained by combining the upper address and the lower address is incremented for each frame. Is done.

Thus, information # 1 to information # 3 are sequentially read from DRAM 1a, and information # 4 is
The data is sequentially written to the RAM 1a.

FIG. 16 shows the operation of stopping the storage of information in the DRAM, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration of FIG. .

In the first frame of FIG.
It is assumed that the output of the lower address counter 10 is as shown in (3) and the output of the FIFO 2a is as shown in (4). Therefore, the read enable signal is (5)
It is like. The basic operation is the same as the operation described in FIG.

The difference between FIG. 16 and FIG. 14 is that as shown in (8), the logical level of the recording stop signal changes to “1” at the timing of the information # 4 of the first frame, and as shown in (10). DR at the timing of information # 4 of the first frame
The logical level of the repetition instruction data written to AM1a changes to “1”, and as shown in (9), the head address update signal changes to the logical level “1” at the timing of the start address of information # 5. is there.

First, as shown in (10), the instruction data is repeatedly supplied to the DRAM 1a in FIG. 1 at the timing of the information # 4 of the first frame, and at the same time, the write enable signal is supplied to the DRAM 1a as shown in (6). Then, the upper 12 bits of the address of information # 4 are now 0x0
4f, the lower 8 bits are 0xff.
The repetition instruction data of the logic level "1" is written in the repetition instruction data area of the address 0x04fff of "a".

Since the address 0x04fff is the last address of the area for storing the information # 4, the logical level of the recording stop signal changes to "1" at this timing. Thus, the selector 5 of FIG. 13 selects the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
Upper 12 addresses of information # 4 supplied to IFO 2a
As shown in (16), the upper 12 bits of the leading address of the information # 4 are assigned to the bits.

Further, as shown in (9), when the logical level of the head address update signal changes to "1" at the timing of the head address of the information # 5, the address of the address held in the delay flip-flop 14 at the same timing. Top 12
The bit 0x050 is selected and supplied to the FIFO 2a at the timing of the start address as shown in (16).

In the subsequent frames, the logical levels of the recording start signal, recording stop signal, head address update signal, and repetition instruction data continue to be "0".
The most basic operation described in 4 is repeated. In this case, since the writing of information # 4 has been completed,
The logical level of the read enable signal transitions to “0” at the timing of the address of the information # 4,
5, since the start address 0x05000 is set, only the start address continues to be held.

As described above, transmission of information # 4 becomes possible, and preparation for writing data to information # 5 is made.

The same function as that of the conventional information multiplex transmission circuit can also be realized by the configuration shown in FIG.
According to the configuration of FIG. 13, the counter for generating the lower address is made common, and the upper start address, the upper address, and the lower address are stored in one FIFO, so that a plurality of information is stored in a single DRAM. And store multiple pieces of information in a single DRAM,
The usage efficiency of the DRAM increases.

In addition, according to the configuration of FIG.
When a device other than the IFO is constituted by a large-scale integrated circuit, the large-scale integrated circuit and the FIFO, the FIFO and the DRAM, and the DR
The number of wirings for input and output of AM is 12 × 3 + 8 × 2 = 52, and the number of wirings can be reduced as compared with the configuration of FIG.

FIG. 17 shows a fifth embodiment of the present invention.
13. The circuit scale of the information multiplexing transmission circuit is reduced by removing the lower address counter, the selector for selecting one of the lower address output from the lower address counter, and the address obtained by incrementing the address output from the FIFO, from the configuration of FIG. Is what you do.

Note that, here, an example in which the upper address is 12 bits and the lower address is 8 bits will be described.

Referring to FIG. 17, reference numeral 1a denotes a DRAM for storing input data and repetition instruction data, and 2a denotes a DRA.
The upper 12 bits and lower 8 bits of the address of M1a and the upper 12 bits of the top address of the information stored in the DRAM 1a.
The FIFO 16 holding the bits is an abbreviation of an LSB (Least Significant Bit) of the lower address selection signal and the lower address 8 bits output by the FIFO 2a. In this case, the lowest weight of the lower 8 bits is used. The AND circuit 13 performs an AND operation of 7 bits except for the lower bit of the LSB of the lower address and a signal obtained by inverting the logical level of the LSB of the lower address. The AND circuit 13 holds the output of the AND circuit 16 by a carry holding signal. A delay flip-flop 9 is a NAND circuit for inverting and outputting a logical level of a logical AND operation result of the read enable signal and the write enable signal of the DRAM 1a, and 11 is an output of the delay flip-flop 13 and a NAND circuit. The AND circuit 17 performs an AND operation on the output of the AND circuit 9 and the output of the AND circuit 11 and the lower address selection signal. An OR circuit 4 performs an OR operation, 4 is an adder that adds the output of the OR circuit 17 to the output of the FIFO 2a as a binary number, and 7 is an output of the adder 4 that holds the output of the adder 4 to determine the timing of the start address. The delay flip-flop 5 for delaying to the timing of the upper address in the output of the adder 4, a selector 5 for selecting and outputting one of the output of the adder 4 and the output of the delay flip-flop 7, and 18 for a lower address selection signal An AND circuit 6 performs an AND operation on the inverted signal of the logical level and the repetition instruction data read from the DRAM 1a. The OR circuit 14 supplies the output of the delay flip-flop 7 and outputs the timing of the head address to the output of the adder 4. Is a selector which selects one of the output of the selector 5 and the output of the delay flip-flop 14 using the head address update signal as a selection signal and supplies it to the FIFO 2a. .

Then, F is connected to the address terminal of the DRAM 1a.
12-bit upper address, which is the output of IFO 2a, and 8
The lower address of the bit is supplied alternately, the data of the service information and the repeat instruction data are supplied to the data input terminal and written, and the stored data of the service information and the repeat instruction data are read from the data output terminal,
The read service information data is output data, and the read repetition instruction data is output by the AND circuit 18.
Supplied to

At the same time when the address is supplied from the FIFO 2a to the DRAM 1a, the address is output from the OR circuit 17 in the adder 4 and is a signal equivalent to the carry of the lower address counter in the embodiment of the invention described above. Is supplied to the selector 5 and held in the delay flip-flop 7.

That is, in the configuration of FIG. 13, the lower address counter 10 and the selector 12 are deleted in the configuration of FIG. 17 so that the lower address is also held in the FIFO 2a, and in the configuration of FIG.
In FIG. 17, the carry generated by 0 is generated by the AND circuit 16 and held by the delay flip-flop 13.

When the logical level of any of the recording start signal, recording stop signal, head address update signal and repetition instruction data is not "1", the output of the adder 4 is selected by the selector 5 and the selector 15 and the FIFO 2a
Supplied to

When the logical level of any one of the recording start signal, recording stop signal, and repetition instruction data is "1" and the logical levels of the head address update signal and the lower address selection signal are "0", the delay flip-flop 7 is supplied to the FIFO 2a.

When the logical level of the head address update signal is "1", the output of the delay flip-flop 14 is FI regardless of the logical levels of the recording start signal, recording stop signal, repetition instruction data and lower address selection signal.
It is supplied to the FO 2a.

FIG. 18 shows the basic operation of the configuration of FIG. 17 and the operation of repeatedly transmitting the information after reading the repeat instruction data at the information transmission timing (1) of the configuration of FIG. .

The FIFO 2a shown in FIG.
As shown in FIG. 17, at the timing of each information, the upper 12 bits of the top address of the area storing the plurality of information in the DRAM 1a and the upper 12 bits of the address indicating the area storing the plurality of information in the DRAM 1a in FIG. And D
Lower 8 bits of an address indicating an area for storing a plurality of pieces of information in the RAM 1a are sequentially stored.

Since it is assumed that the inside of the DRAM 1a is mapped as shown in FIG. 25, the upper 12 bits of the head address are 0 for information # 1 to information # 4.
x000, 0x010, 0x025, 0x048. Then, for information # 1 to information # 3, the upper 12 bits of the address in the first frame in FIG. 17 are 0x001, 0x024, and 0x030.

On the other hand, it is assumed that the lower address in the first frame is 0xfe as shown in (2).

Information # is stored in DRAM 1a of FIG.
Since it is assumed that information 1 to information # 3 have been written and information # 4 and subsequent information have not been written, the read enable signal is transmitted from the information # 1 to information # 3 of the FIFO 2a as shown in (5). The logic level is "0" at the timing of the address. Further, since it is not assumed that information is written to the DRAM 1a, the write enable signal has the logic level "1" continuously as shown in (6). That is, what is described in the address timing of (2) is the read address.

Since the read enable signal and the write enable signal are given by (5) and (6), though not shown, the result of the NAND operation of the read enable signal and the write enable signal is represented by the information # in the FIFO 2a. The logical level becomes "1" at the timing of the address of 1 to information # 3, and the logical level becomes "0" at the timing of the head address of the information # 1 to information # 3 of the FIFO 2a.

Since the lower address in the first frame is assumed to be 0xfe as described above, the output of the AND circuit 16 outputs "1" when the logic level of the lower address selection signal is "1". And this is held in the delay flip-flop 13 by the carry holding signal and becomes 1
Output with frame delay. That is, the output of the delay flip-flop 13 has the logic level “1” in the second frame, and the logic level in the first frame is “0”.

Therefore, in the first frame, the logic level of the output of the AND circuit 11 is "0".

Therefore, the output of the OR circuit 17 is "1" only when the logic level of the lower address selection signal is "1".
Is added to the lower address output from the FIFO 2a in the adder 4. That is, the output of the adder 4 is (1
As shown in 3), only the lower address of (2) is advanced, and the upper 12 bits of the top address and the upper 1 bit of the address are increased.
The two bits have no change.

In the first frame, since the logical levels of the recording start signal, the recording stop signal, and the repetition instruction data are all "0", the selector 5 selects and outputs the output of the adder 4. .

Further, in the first frame, since the logical level of the head address update signal is also "0", the selector 15 selects the output of the adder 4 and supplies it to the FIFO 2a.

Therefore, the address supplied to the FIFO 2a is as shown in (18), which is supplied from the FIFO 2a in the second frame.

In the second frame, the logic level of the output of delay flip-flop 13 transitions to "1" as described above. Therefore, the output of the OR circuit 17 becomes “1” when the logical level of the lower address selection signal is “1” and at the timing of the upper address and the lower address corresponding to each information, and the adder becomes 4 is supplied to one input terminal. This is shown at the time corresponding to the second frame in (12).

Accordingly, as shown in the time corresponding to the second frame of (13), the output of the adder 4 is such that only the upper 12 bits of the head address remain the same as (2), and the upper 12 bits and lower 8 bits of the address. Both bits are obtained by incrementing (2) by one.

The output of the adder 4 is held in the delay flip-flop 7 and the delay flip-flop 14, and is output from the delay flip-flop 7 and the delay flip-flop 14 with a delay of one timing each.

By the way, in the second frame, the address corresponding to the information # 2 is 0x024ff. As described with reference to FIG. 25, since the repeat instruction data is stored in the address 0x024ff of the DRAM 1a, the address 0x024f corresponding to the information # 2 is stored.
The instruction data is repeatedly read at the timing f.
This is indicated by the pulse in (11).

The instruction data is repeatedly read from DRAM 1a, and the logical level becomes "1" at the timing of the address of information # 2.
The logic level of the selection signal supplied to
The output of delay flip-flop 7 is selected and output.

At this time, since the logical level of the head address update signal remains "0", the output of the delay flip-flop 7 is selected by the selector 15 and the FI
It is supplied to the FO 2a. Therefore, the address supplied to the FIFO 2a is equal to the output of the adder 4 when the logic level of the repetition instruction data is "0", as shown at the time corresponding to the second frame of (18). When the logic level of the data is "1" and the logic level of the lower address selection signal is "0", that is, 0x010, which is the upper 12 bits of the first address, is assigned to the upper address at the timing of the upper address corresponding to information # 2. And
When the logic level of the repetition instruction data is "1" and the logic level of the lower address selection signal is "1", that is, information # 2
Is equal to the lower address of (13).

In the third frame, the FIFO
2a. At this time, the logical levels of the recording start signal, the recording stop signal, and the repetition instruction data are “0”.
Since the logical level of the head address update signal is also "0", the address supplied to the FIFO 2a is (1
8), which is equal to (13) indicating the output of the adder 4.

Note that the upper address is incremented only when the count value of the lower address counter 10 is 0x00, but the lower address counter 10 increments the count value for each frame. The combined address is incremented for each frame.

As described above, the address corresponding to each piece of information is advanced, and the repetition instruction data stored at the last address of the area where each piece of information is stored in DRAM 1a is read. The information can be repeatedly transmitted.

FIG. 19 shows the information transmission timing (No. 2) of the configuration shown in FIG. 17, and when the recording start signal is supplied at the timing of the designated information, the frame following the frame to which the recording start signal is supplied is transmitted. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

In the first frame of FIG.
7, the output of the FIFO 2a is as shown in (2).
It is assumed that the address shown in (2) is supplied to the RAM 1a. Therefore, the read enable signal is as shown in (5). The basic operation is the same as the operation described in FIG.

The difference between FIG. 19 and FIG. 18 is that the logical level of the recording start signal becomes “1” at the timing of the information # 4 of the first frame, as shown in (7), and as shown in (6), The logic level of the write enable signal changes to “0” at the timing of information # 4 in the second and subsequent frames.

When the logical level of the recording start signal transits to "1" and the logical level of the lower address selection signal supplied to the AND circuit 18 of FIG. 17 is "0", the selector 5 of FIG. The output of the loop 7 is selected and output. At this timing, since the delay flip-flop 7 holds the upper 12 bits of the head address of the information # 4, the information # 4 changes at the timing when the logical level of the recording start signal changes to "1" as shown in (16). 0x048, which is the high-order 12 bits of the top address of No. 4 in FIG.
3 is supplied to the FIFO 2a.

At timings other than the above in the first frame, the upper 12 bits of the start address are equal to the upper 12 bits of the start address in (2), and the upper 12 bits and lower 8 bits of the address are advanced by one. This is,
As shown in (18), the data is supplied to the FIFO 2a.

This is because in the second frame the FIF
Output from O2a. In this frame, since the logic level of the output of the delay flip-flop 13 is “0”, the output of the adder 4 at the timing of the upper address is (1).
2), which is equal to (2) indicating the output of the FIFO 2a. Since the logical level of any of the recording start signal, recording stop signal, head address update signal and repetition instruction data does not become "1", the head address held in the FIFO 2a and the upper 12 bits of the address are (1).
As in (8), the output of the FIFO 2a is the same as (2).

However, as described with reference to FIG. 18, the lower address increments the count value for each frame.
An address obtained by combining the upper address and the lower address is incremented for each frame.

Thus, information # 1 to information # 3 are sequentially read from DRAM 1a, and information # 4 is
The data is sequentially written to the RAM 1a.

FIG. 20 shows the operation of stopping the storage of information in the DRAM, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration of FIG. .

In the first frame of FIG.
7, the output of the FIFO 2a is as shown in (2). Therefore, the read enable signal is as shown in (5). The basic operation is the same as the operation described in FIG.

The difference between FIG. 20 and FIG. 18 is that the logical level of the recording stop signal changes to “1” at the timing of the information # 4 of the first frame as shown in (8), and as shown in (10). DR at the timing of information # 4 of the first frame
The logical level of the repetition instruction data written to AM1a changes to “1”, and as shown in (9), the head address update signal changes to the logical level “1” at the timing of the start address of information # 5. is there.

First, as shown in (10), the instruction data is repeatedly supplied to the DRAM 1a in FIG. 17 at the timing of the information # 4 of the first frame, and at the same time, the write enable signal is supplied to the DRAM 1a as shown in (6). Then, the upper 12 bits of the address of information # 4 are now 0x0
4f, the lower 8 bits are 0xff.
The signal of the logic level "1" is written in the repetition instruction data area of the address 0x04fff of "a".

Since the address 0x04fff is the last address of the area for storing the information # 4, the logical level of the recording stop signal changes to "1" at this timing. Thus, the selector 5 of FIG. 17 selects the output of the delay flip-flop 7 and supplies it to the FIFO 2a.
Upper 12 addresses of information # 4 supplied to IFO 2a
As shown in (16), the upper 12 bits 0x048 of the head address of the information # 4 are assigned to the bits.

Further, when the logic level of the start address update signal changes to "1" at the start address timing of the information # 5, the upper 12 bits 0x050 of the address held in the delay flip-flop 14 are selected at the same timing. Then, as shown in (16), it is supplied to the FIFO 2a at the timing of the start address.

In the subsequent frames, the logical levels of the recording start signal, recording stop signal, head address update signal, and repetition instruction data continue to be "0".
The most basic operation described in 8 is repeated. In this case, since the writing of information # 4 has been completed,
The logical level of the read enable signal transitions to “0” at the timing of the address of the information # 4,
5 is the stage where the start address 0x05000 has been set, so that only the start address is kept held.

As described above, transmission of information # 4 becomes possible, and preparation for writing data to information # 5 is made.

Now, according to the configuration of FIG. 17, the same function as that of the conventional information multiplex transmission circuit can be realized. or,
According to the configuration of FIG. 17, the lower address is also held in one FIFO, the carry is generated by logically processing the lower address held in the FIFO, the lower address counter is omitted, and the upper address held in the FIFO is saved. By supplying the start address, the upper address, and the lower address to a single DRAM, it is possible to store a plurality of information in a single DRAM, and to provide a single DRAM.
Since a plurality of pieces of information are stored in the DRAM, the use efficiency of the DRAM is improved. There is also an effect that the lower address counter can be omitted.

According to the structure of FIG.
When a device other than the IFO is constituted by a large-scale integrated circuit, the large-scale integrated circuit and the FIFO, the FIFO and the DRAM, and the DR
The number of wirings for input and output of AM is 12 × 3 + 8 × 2 = 52, and the number of wirings can be reduced as compared with the configuration of FIG.

FIG. 21 shows a sixth embodiment of the present invention.
In order to hold the address of the memory and to hold the head address where the information is stored in the memory, one FI
FO is used.

In FIG. 21, 1 is a memory for storing input data and repetition instruction data, 2 is a memory address FIFO for holding an address of the memory 1, and 3 is a head address for information stored in the memory 1. The start address FIFO 4 is an adder that adds 1 to the output of the memory address FIFO 2, and the adder 5 selects one of the output of the adder 4 and the start address output by the start address FIFO 3 and supplies it to the memory address FIFO 2. selector,
Reference numeral 6 denotes a logical sum circuit that supplies a logical sum operation result of the recording start signal, the recording stop signal, and the repetition instruction data read from the memory 1 to the selector 5 as a selection signal, and 7 holds an output of the adder 4, The delay flip-flop 8, which delays the head address of each information number to the address timing, selects one of the output of the delay flip-flop 7 and the head address output by the head address FIFO 3 by the head address update signal, and selects the head address FIFO.
3 is a selector supplied to the selector 3.

The output of the memory address FIFO2 is supplied to the address terminal of the memory 1, the data of the service information and the repetition instruction data are supplied to the data input terminal and written, and the stored data of the service information and the repetition instruction data are supplied. Is read from the data output terminal, and the data of the read service information becomes output data,
The read repetition instruction data is supplied to the OR circuit 6.

The memory address FIFO2 contains the memory 1
The addresses indicating the areas for storing a plurality of pieces of information are sequentially stored in correspondence with each piece of information.
In the IFO 3, the start addresses of the areas for storing a plurality of pieces of information in the memory 1 are sequentially stored.

At the same time when the address is supplied from the memory address FIFO 2 to the memory 1, the supplied address is added with 1 in the adder 4, supplied to the selector 5, and held in the delay flip-flop 7.

When none of the logical levels of the recording start signal, the recording stop signal, and the repetition instruction data read from the memory 1 is "1", the output of the adder 4 is selected by the selector 5 and is stored in the memory address FIFO2. Supplied.

When the logical level of any one of the recording start signal, recording stop signal and repetition instruction data is "1", the output of the head address FIFO3 is selected by the selector 5 and supplied to the memory address FIFO2.

Further, the output of the adder 4 is held in the delay flip-flop 7, and when the logical level of the head address update signal is "1", the address held in the delay flip-flop 7 is selected by the selector 8 and a new address is selected. The output of the start address FIFO 3 is supplied to the start address FIFO 3 as the start address, and when the logical level of the start address update signal is “0”, the output of the start address FIFO 3 is selected by the selector 8 and supplied to the start address FIFO 3 again.

FIG. 22 shows that the same information can be repeatedly transmitted after reading the repetition instruction data stored in the memory at the information transmission timing (1) of the configuration of FIG.

In FIG. 22, in the initial state of the memory address, information # 1 is 0x00100, information # 2
0x024fe for information and 0x0 for information # 3
It is assumed to be 3000.

If the logical levels of the recording start signal and the recording stop signal are not supplied and the instruction data is not repeatedly read from the memory 1 in FIG. 21, (4), (4) in the first frame in FIG. As shown in 5) and (8), the logical levels of the recording start signal, the recording stop signal, and the repetition instruction data are "0", so that the output of the adder 4 is selected in the first selector 5 of FIG. , The input terminal of the memory address FIFO2 has the address shown in (9),
That is, an address obtained by incrementing the address of (2) by one step is supplied.

If the start address is not updated, the output of the start address FIFO3 is selected by the selector 8 in FIG. 21 because the logical level of the start address update signal is "0" as shown in (6). The input terminal of the start address FIFO3 is supplied with the start address shown in (10), that is, the same start address as (3).

In the second frame, from the memory address FIFO2, as shown in (2), 0x00101 for information # 1 and 0x024 for information # 2.
For ff and information # 3, 0x03001 is sequentially supplied to the memory 1, and from the start address FIFO3, (3)
, The same start address as one frame before is output.

Also in this frame, the logical levels of the recording start signal, the recording stop signal, and the repetition instruction data for information # 1 and information # 3 are "0".
The selector 5 selects the output of the adder 4 and supplies the input terminal of the memory address FIFO 2 with an address obtained by incrementing the above address by one step as shown in (9).

On the other hand, in this frame, information # 2
Is 0x024ff. As shown in FIG. 25, since the repetition instruction data of the logical level "1" is stored in the repetition instruction data area of the address 0x024ff, it is read from the memory 1 of FIG. Is output as the pulse shown in the frame. As a result, the logic level of the output of the OR circuit 6 in FIG. 21 changes to “1”.

For this reason, since the output of the head address FIFO3 is selected in the selector 5 of FIG.
As for (2), the start address 0x01000 is supplied to the memory address FIFO2 as shown in (9).

In this frame, (8)
Since the logical level of the head address update signal is "0", the output of the head address FIFO3 is selected by the selector 8 in FIG.
3 input terminal. That is, the start address FIF
O3 holds the same start address as before.

Therefore, in the third frame, from the memory address FIFO2 in FIG. 21, the addresses 0x00102, 0x01000, and 0x for the information # 1 to # 3 are stored.
03002 is output, and from the start address FIFO3, the start address 0x000 for information # 1 to # 3
00, 0x01000 and 0x02500 are output.

[0303] Also in this frame, a recording start signal,
Since the logical levels of the recording stop signal, the head address update signal, and the read data of the repeat instruction data are “0”,
The memory address is incremented by one for all information, and the head address is kept as it was at the previous address. Later,
The above operation is repeated.

[0304] Although only the case where the instruction data is repeatedly read for information # 2 is described above, the repeated instruction data is also read for information # 1 and information # 3 when the last address of the storage area is reached. Since the same operation as described above is performed, the information stored in memory 1 in FIG. 21 can be repeatedly transmitted.

FIG. 23 shows the information transmission timing (part 2) of the configuration shown in FIG. 21. When the recording start signal is supplied at the timing of the designated information, the frame following the frame to which the recording start signal is supplied is transmitted. Indicates that the head address is supplied to the memory at a timing corresponding to the information, and the information can be stored.

As shown in (2), the memory address in the first frame is 0x00103, 0x01001, and 0x03 for information # 1 to information # 3, respectively.
003. Further, since the start address is as assumed in FIG. 25, as shown in (3), for information # 1 to information # 4, 0x0000, 0
x01000, 0x02500, and 0x04800.

[0307] At this time, as shown in (4), it is assumed that the logical level of the recording start signal becomes "1" at the timing of information # 4. As a result, the logic level of the output of the OR circuit 6 in FIG. 21 changes to “1”, and the selector 5 selects the output of the head address FIFO 3 and supplies it to the memory address FIFO 2. On the other hand, for information # 1 to information # 3, the logical level of the recording start signal is "0", so that the selector 5 selects the output of the adder 4 and supplies it to the memory address FIFO2.

Therefore, in this frame, the memory address FIFO2 has the incremented address 0x00104 for the information # 1, the incremented address 0x01002 for the information # 2, and the incremented address for the information # 3. For 0x03004 and information # 4, the start address 0x04800 is supplied. As shown in (10), the same start address as in (3) is supplied to the start address FIFO3.

In the second frame, the above address and the above start address are output from the memory address FIFO 2 and the start address FIFO 3 in FIG.

[0310] After this frame, the recording start signal, the recording stop signal, and the read data of the repetition instruction data have logical levels "0" as shown in (4), (5), and (8). Until the memory address is reached, the memory address is incremented by one, and the leading address holds the previous address.

That is, information # 4 can be stored in an area after 0x04800 where no information was stored in the initial state. After storing the information # 4, the information # 1 to the information # 4 can be repeatedly transmitted as described in FIG.

FIG. 24 shows the operation of stopping the storage of information in the memory, writing repetition instruction data to the last address, and updating the start address at the information transmission timing (part 3) of the configuration shown in FIG. .

As shown in (2), the memory addresses in the first frame are 0x00903, 0x01801, and 0x033 for information # 1 to information # 3, respectively.
803, 0x04fff, and the start address is
As shown in (3), for information # 1 to information # 4, 0x0000, 0x01000, 0x02500,
It is assumed that it is 0x04800.

At this time, as shown in (7), when the logical level of the repeat instruction data is set to “1” at the timing of information # 4, the logical level “1” is stored in the repeat instruction data area of the address 0x04fff of the memory 1 in FIG. Is written. As a result, the subsequent address 0x04f
At ff, the instruction data is repeatedly read from the memory, and the information # 4 can be repeatedly transmitted as described above.

Further, as shown in (5), when the logical level of the recording stop signal is set to “1” at the timing of information # 4,
As a result, the logical level of the output of the OR circuit 6 in FIG.
Since x04800 is selected and supplied to the memory address FIFO2, the memory address FIFO2 in this frame includes the address 0x00904 for information # 1, which is incremented by one, the address 0x01802, which is incremented for information # 2, and information # 3. Is supplied by one step address 0x03804, and the leading address 0x04800 is supplied for information # 4. Therefore, in the second frame, the above address is output from the memory address FIFO2.

Further, as shown in (6), when the logical level of the head address update signal is set to "1" at the timing of the information # 5, the selector 8 in FIG. 21 selects the output of the delay flip-flop 7.

The delay flip-flop 7 holds the output of the adder 4 and outputs it with a delay of one timing.
Therefore, the delay flip-flop 7 outputs, at the timing of information # 5, the address 0x05000 obtained by increasing the address 0x04fff by one step and held at the timing of information # 4. This address is supplied to the start address FIFO 3 as the start address of the information # 5 as shown in (11). This start address is the start address F in the next frame.
Since the data is output from the IFO 3, the head address corresponding to each information is, as shown in the second frame of (3),
0x00000, 0x01000, 0x02500, 0
x04800 and 0x05000.

Then, the subsequent operation is as described above.

The same function as that of the conventional information multiplex transmission circuit can be realized by the configuration shown in FIG.
Further, according to the configuration of FIG. 21, it is possible to store a plurality of information in a single memory by using a FIFO that holds a memory address and a FIFO that holds a head address where information is stored in the memory. In other words, since a plurality of pieces of information are stored in a single memory, the efficiency of memory use is improved.

According to the configuration of FIG. 21, the memory and the FI
In the case where a circuit other than the FO is configured by a large-scale integrated circuit, the wiring between the large-scale integrated circuit and the FIFO, between the FIFO and the memory, and the input / output wiring of the memory is 20 × 5 + 8 × 2 = 116, which is compared with the configuration of FIG. As a result, the number of wirings is reduced.

(Supplementary Note 1) A memory for storing input data and repetition instruction data, and a FIFO for holding an address of the memory and a head address of information stored in the memory
A NAND circuit for inverting and outputting a logical level of a logical AND operation of the read enable signal and the write enable signal of the memory; an output of the NAND circuit;
An adder that adds the memory address or the head address output from the adder, a delay flip-flop that holds the output of the adder, and a selector that selects one of the output of the adder and the output of the delay flip-flop. An information multiplexing circuit which performs a logical sum operation of a recording start signal, a recording stop signal, a head address update signal, and repetition instruction data output from the memory and supplies the result to the selector as a selection signal. Sending circuit.

(Supplementary Note 2) A memory that stores input data and repetition instruction data, a lower address counter that outputs a lower address and a carry of the memory, and at least an upper address of the memory and an upper address that stores information in the memory. A FIFO for holding a start address, a NAND circuit for inverting and outputting a logical level of an AND operation of a read enable signal and a write enable signal of the memory, a carry output from the lower address counter, and the NAND An AND circuit for performing an AND operation with an output of the circuit, an adder for adding the output of the AND circuit and the upper address or the upper head address of the memory output by the FIFO, and holding the output of the adder A delay flip-flop, and a selector for selecting one of the output of the adder and the output of the delay flip-flop. An OR circuit for performing a logical OR operation of a recording start signal, a recording stop signal, a head address update signal, and repetition instruction data read from the memory, and supplying the result to the selector as a selection signal. Multiplex transmission circuit.

(Supplementary Note 3) The information multiplex transmission circuit according to Supplementary Note 2, wherein the memory stores input data and repetition instruction data, a lower address counter that outputs a lower address and a carry of the memory, and a higher address of the memory. A FIFO for holding an address and a high-order top address storing information in the memory, a NAND circuit for inverting and outputting a logical level of a logical AND operation of a read enable signal and a write enable signal of the memory, An AND circuit for performing an AND operation of the carry output by the counter and the output of the NAND circuit; and an output of the AND circuit and the FI
An adder for adding an upper address or an upper head address of the memory output by the FO, a delay flip-flop holding an output of the adder, and selecting one of an output of the adder and an output of the delay flip-flop A selector, and a logical sum circuit for performing a logical sum operation of a recording start signal, a recording stop signal, a head address update signal, and repetition instruction data read from the memory, and supplying the result as a selection signal to the selector. Multiplex transmission circuit.

(Supplementary Note 4) The information multiplexing and transmitting circuit according to Supplementary Note 2, wherein the dynamic random access memory (hereinafter, referred to as a “memory”) stores input data and repeat instruction data.
Abbreviated as "DRAM". ), A lower address counter that outputs a lower address and a carry of the DRAM, a FIFO that holds an upper address of the DRAM and a head address storing information in the memory, and a read enable signal and a write enable signal of the DRAM. A NAND circuit for inverting and outputting the logical level of the AND operation, an AND circuit for performing an AND operation of the carry output from the lower address counter and the output of the NAND circuit, An adder for adding an output and an upper address or an upper head address of the DRAM output by the FIFO; a delay flip-flop holding an output of the adder; and one of an output of the adder and an output of the delay flip-flop A first selector for selecting a recording start signal, a recording stop signal,
The logical sum circuit of the start address update signal and the repetition instruction data read from the DRAM to supply the selected signal to the first selector as a select signal, and the lower address select signal as a select signal, the output of the FIFO, A second selector for selecting one of the outputs of the lower address counter and supplying the selected output to an address terminal of the DRAM.

(Supplementary Note 5) The information multiplex transmission circuit according to Supplementary Note 2, wherein the DRAM stores input data and repetition instruction data, a lower address counter that outputs a lower address and a carry of the DRAM, and a higher address of the DRAM. A FIFO that holds an address, a lower address, and a head address that stores information in the memory, a first delay flip-flop that holds a carry output by the lower address counter, and a read enable signal and a write enable signal of the DRAM. A NAND circuit for inverting and outputting a logical level of an AND operation, an AND circuit for performing an AND operation of the carry delayed by the delay flip-flop and the output of the NAND circuit, The output of the circuit and the upper address and lower address or upper head address output by the FIFO are An adder to be added, a second delay flip-flop for holding the output of the adder, a first selector for selecting one of the output of the adder and the output of the second delay flip-flop, A logical sum circuit of a signal, a recording stop signal, and repetition instruction data read from the DRAM and supplying the selected selector with a logical sum circuit, and an output of the second delay flip-flop. A third delay flip-flop; a second selector for selecting one of the output of the first selector and the output of the third delay flip-flop; a lower address output by the lower address counter; A third selector for selecting one of the outputs of the selector and supplying the selected output to the FIFO.

(Supplementary Note 6) A DRAM for storing input data and repetition instruction data, a FIFO for holding an upper address and a lower address of the DRAM, a head address for storing information in the DRAM, and a lower address output by the FIFO A first logical AND operation of a signal obtained by inverting the logical level of the LSB of LSB (“Least Significant Bit”), a bit of the lower address excluding the LSB, and a lower address selection signal is performed. An AND circuit; a first delay flip-flop for holding an output of the first AND circuit by a carry holding signal;
A NAND circuit for inverting and outputting the logical level of the AND operation of the read enable signal and the write enable signal of M, a carry of the lower address held by the first delay flip-flop, and an output of the NAND circuit A second AND circuit that performs a logical AND operation of the first logical OR circuit, a first logical OR circuit that performs a logical OR operation of the output of the second logical AND circuit and the lower address selection signal, and the DRAM that the FIFO outputs An adder for adding an upper address and a lower address or an upper head address of the first and the output of the first OR circuit, a second delay flip-flop holding an output of the adder, an output of the adder, A first selector for selecting one of the outputs of the second delay flip-flop; a signal obtained by inverting the logical level of the lower address selection signal; A third logical product circuit for performing a logical product operation of data and a second logical sum circuit for performing a logical sum operation of a recording start signal, a recording stop signal, and an output of the logical product circuit and supplying the result as a selection signal to the selector And a third delay flip-flop that holds the output of the second delay flip-flop, and selects one of the output of the first selector and the output of the third delay flip-flop and supplies it to the FIFO. An information multiplexing transmission circuit, comprising:

(Supplementary Note 7) A memory for storing input data and repetition instruction data, and a first first-in first-out memory (hereinafter abbreviated as "FIFO") for holding an address of the memory. , A second FIFO holding a head address of information stored in the memory.
An adder for adding 1 to the output of the first FIFO;
A first selector for selecting one of the output of the adder and the head address output by the second FIFO and supplying it to the first FIFO, a recording start signal, a recording stop signal, and a repetition read from the memory An OR circuit that supplies the result of the OR operation of the instruction data to the first selector as a selection signal, a delay flip-flop that holds the output of the adder, an output of the delay flip-flop, and the second FIFO.
And a second selector for selecting one of the start addresses output by the first selector and supplying the selected start address to the start address FIFO.

[0328]

As described above in detail, according to the present invention, since a plurality of pieces of information are stored in a single memory, the use efficiency of the memory is improved.

When the memory and the FIFO other than the FIFO are constituted by a large-scale integrated circuit, when the large-scale integrated circuit and the FIFO
The number of wires between the IFO and the memory and the number of input / output lines of the memory can be reduced as compared with the conventional information multiplex transmission circuit.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 shows information transmission timing of the configuration of FIG. 1 (part 1).

FIG. 3 is an information transmission timing of the configuration of FIG. 1 (part 2);

FIG. 4 is an information transmission timing (3) of the configuration of FIG. 1;

FIG. 5 shows a second embodiment of the present invention.

FIG. 6 shows information transmission timing of the configuration of FIG. 5 (part 1).

FIG. 7 shows information transmission timing of the configuration of FIG. 5 (part 2).

FIG. 8 shows information transmission timing of the configuration of FIG. 5 (part 3).

FIG. 9 shows a third embodiment of the present invention.

FIG. 10 shows information transmission timing of the configuration of FIG. 9 (part 1).

FIG. 11 is an information transmission timing of the configuration of FIG. 9 (part 2).

FIG. 12 shows information transmission timing of the configuration of FIG. 9 (part 3).

FIG. 13 shows a fourth embodiment of the present invention.

FIG. 14 is an information transmission timing of the configuration of FIG. 13 (part 1).

FIG. 15 shows information transmission timing of the configuration of FIG. 13 (part 2).

FIG. 16 is an information transmission timing (part 3) of the configuration of FIG. 13;

FIG. 17 shows a fifth embodiment of the present invention.

FIG. 18 shows information transmission timing of the configuration of FIG. 17 (part 1).

FIG. 19 is an information transmission timing (part 2) of the configuration of FIG. 17;

FIG. 20 is an information transmission timing (3) of the configuration of FIG. 17;

FIG. 21 shows a sixth embodiment of the present invention.

FIG. 22 shows information transmission timing of the configuration of FIG. 21 (part 1).

FIG. 23 shows information transmission timing of the configuration of FIG. 21 (part 2).

FIG. 24 is an information transmission timing of the configuration of FIG. 21 (part 3).

FIG. 25 shows an example of a memory map according to the present invention.

FIG. 26 shows a conventional information multiplex transmission circuit.

FIG. 27 shows a memory in a conventional information multiplex transmission circuit.
Example of a map.

FIG. 28 is an information transmission timing (1) of the configuration of FIG. 26;

FIG. 29 is an information transmission timing (part 2) of the configuration of FIG. 26;

FIG. 30 is an information transmission timing (3) of the configuration of FIG. 26;

[Explanation of symbols]

 Reference Signs List 1 memory 1a DRAM 2 memory address FIFO 2a FIFO 3 start address FIFO 4 adder 5 selector 6 OR circuit 7 delay flip-flop 8 selector 9 NAND circuit 10 lower address counter 11 AND circuit 12 selector 13 delay flip-flop 14 delay Flip-flop 15 selector 16 logical product circuit 17 logical sum circuit 18 logical product circuit

(72) Inventor Hideaki Yamada 3-22-8 Hakata-ekimae, Hakata-ku, Fukuoka, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Masayuki Ishii Hakata-ekimae, Hakata-ku, Fukuoka, Fukuoka No. 22-8, Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Akihide Otonari 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture F-term, Fujitsu Kyushu Digital Technology Co., Ltd. (Reference) 5K015 AF02 GA01 5K028 AA07 CC05 KK01 SS02 SS26

Claims (3)

[Claims] 1. A memory for storing input data and repetition instruction data, a first-in first-out memory (hereinafter, “FIFO”) for storing an address of the memory and a head address of information stored in the memory. ), A NAND circuit for inverting and outputting a logical level of an AND operation of the read enable signal and the write enable signal of the memory, an output of the NAND circuit, and a memory output from the FIFO. An adder for adding an address or a head address, a delay flip-flop holding an output of the adder, a selector for selecting one of an output of the adder and an output of the delay flip-flop, a recording start signal, A logical sum operation of a recording stop signal, a head address update signal and repetition instruction data output from the memory is performed, and the selector is operated. And an OR circuit for supplying the selected signal as a selection signal. 2. A memory for storing input data and repetition instruction data, a lower address counter for outputting a lower address and a carry of the memory, at least an upper address of the memory and an upper head address for storing information in the memory. A NAND circuit for inverting and outputting a logical level of a logical product operation of a read enable signal and a write enable signal of the memory; a carry output from the lower address counter; An AND circuit for performing an AND operation with an output, an adder for adding an output of the AND circuit and an upper address or an upper head address of the memory output by the FIFO, and a delay for holding an output of the adder A flip-flop, a selector for selecting one of the output of the adder and the output of the delay flip-flop, An information multiplexing circuit comprising: a logical sum circuit for performing a logical sum operation of a start signal, a recording stop signal, a head address update signal, and repetition instruction data read from the memory, and supplying the result to the selector as a selection signal. circuit. 3. A DRAM for storing input data and repetition instruction data, an upper address and a lower address of the DRAM, and the DRAM.
And a LSB (“Least”) of a lower address output by the FIFO.
Abbreviation for "Significant Bit." ), A first AND circuit for performing a logical AND operation of the signal obtained by inverting the LSB of the lower address, the LSB of the lower address, and the lower address selection signal, and carrying the output of the first AND circuit. A first delay flip-flop held by a holding signal; a NAND circuit for inverting and outputting a logical level of an AND operation of a read enable signal and a write enable signal of the DRAM; A second AND circuit for performing an AND operation on the carry of the held lower address and the output of the NAND circuit; and a second AND circuit for performing an OR operation on the output of the second AND circuit and the lower address selection signal. An OR circuit for adding an upper address and a lower address or an upper head address of the DRAM output from the FIFO and an output of the first OR circuit; A second delay flip-flop that holds the output of the adder; a first selector that selects one of the output of the adder and the output of the second delay flip-flop; A third logical product circuit for performing a logical product operation of a signal obtained by inverting the logical level of the above and the repetition instruction data output from the DRAM; A second OR circuit that supplies the selection signal to the selector; a third delay flip-flop that holds an output of the second delay flip-flop; an output of the first selector; A third selector for selecting one of the outputs of the delay flip-flop and supplying the selected output to the FIFO.