JPH08130414A - Synthesizer circuit - Google Patents

Abstract

PURPOSE: To reduce the required capacity of a ROM, to reduce circuit scale and to reduce power consumption by providing three devices for respectively generating specified data, and providing the waveform data of a sine wave by adding the data of these three devices. CONSTITUTION: A bit inverter 2 is composed of an EX-OR step. The outputs of the bit inverter 2 are data corresponding to the phases from '0' to π/2. With these data as inputs, the sine waveform data corresponding to the phases from '0' to π/2 are separately generating, calculating following three data, data [1:M-1] are data to be linearly increased from the value of sine waveform data at the time of phase '0', data B (B[1:M-4]) are data of the 1/4 value of data A at the phases from '0' to π/4, and data C (C[1:M-4]) are data for correction. These three kinds of amplitude data are added by a full adder 5 so that the half-wave rectified waveform of a sine wave can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DDS which generates a sine wave or a cosine wave, and more particularly to a DDS which requires reduction of ROM capacity.

[0002]

2. Description of the Related Art A direct digital synthesizer (DDS) is a device for logically synthesizing and oscillating an arbitrary waveform such as a sine wave having an arbitrary frequency. FIG. 3 shows its basic configuration. The phase accumulator 1 in FIG. 3 outputs the phase amount data ΔPHASE that advances per unit time given by the reference signal Fclk, and outputs the phase of the output signal at an arbitrary time as L-bit data. The output data is a sawtooth wave-shaped signal when replaced with an analog image, and its cycle is the cycle of the output signal. The waveform generation circuit 7 is a device that converts the sawtooth phase data output from the phase accumulator 1 into an arbitrary M-bit waveform. That is, the waveform generation circuit 7 can be said to be a circuit that outputs an arbitrary function. In order to realize an arbitrary function at high speed, there is a method of recording a function output for input data as a function table using a memory such as a ROM. In this case, the capacity of ROM is 2 ^ L * when the input address is 2 ^ L words and the number of output bits is M bits.
M-bit capacity is required.

(1) If the DDS oscillation signal is limited to an M-bit sine wave, the ROM capacity can be reduced by utilizing the characteristics of the signal waveform. The sine wave is a function that is symmetric in the amplitude direction across π in the range of 0 to 2π, and is a function that is symmetric in the phase direction across π / 2 in the range of 0 to π. That is, if there is a 1/4 sine wave generation circuit that generates sine wave waveform data for a phase input of 0 to π / 2, sine wave waveform data of 0 to 2π can be obtained by using inversion / non-inversion of the input and output. Will be obtained. Since this inversion / non-inversion control is realized by a simple logic gate, the 1/4 sine wave generation circuit is
By configuring the lookup table (function table) by the OM, the number of input bits of the ROM required for the sine wave generation circuit can be reduced.

If the output of the sine wave generation circuit is M bits, the output data of the look-up table is 0 to 0.
Since it corresponds to π / 2 sine wave waveform data output, the data becomes M−1 bits and the number of output bits is also reduced.

In the method of generating all the sine wave waveform data corresponding to the phase of 0 to 2π by the look-up table by the ROM, the capacity of the ROM is 2 ^ L words for the input word number and 2 ^ L word for the output bit number M bits. What required M bits was 2 ^ (L-2) words with 1/4 the number of input words and 2 ^ (L-2) words with M-1 with one output bit reduced by the above method. XM-1 bits.

A sine wave generation circuit embodying this method is shown in FIG. In addition, FIG. 5 is a diagram in which signals of respective parts are written in an analog image. The operation of each unit will be described with reference to FIGS. First, the phase accumulator 1 outputs L-bit phase data PHA [1: L]. This signal is a sawtooth signal whose frequency has the same frequency as the output sine wave. Next, the most significant bit (PHA [L]) is removed to control the polarity of the sine wave output. Next, the upper 2nd bit (PHA [L-1]) is extracted, and if this is 1, the signal (PHA [1: L-2]) of the upper 3 bits or less is inverted by the first bit inverter 2 and 0 If so, leave it as non-inverted. Ie

[0007]

[Equation 1]

[0008] The phase of PHA [0: L-2] corresponds to 0 to π / 2. P [0: L-2] is a quarter sine wave generation circuit 8 including a lookup table by ROM.
To obtain amplitude data D [1: M-1]. D [1:
[M-1] is data in the form of a half-wave rectified sine wave,
The second bit inverter 9 according to the value of PHA [L]
The sine wave waveform data SIN [1: M] is obtained by performing the inversion / non-inversion processing by.

By including some logic in this way, it is possible to reduce the scale of the ROM used.

(2) Consider the sine function SINθ divided as in the following equation.

[0011]

[Equation 2]

The second term of the equation (2) is a function of a straight line connecting SIN0 and SINπ / 2 as shown in FIG. 6 in the range of 0 ≦ θ ≦ π / 2, and the first term (in []) is It is a function whose maximum value is 1/4 or less compared to SINθ. FIG. 7 shows a configuration diagram of a sine wave generation circuit using a method in which SINθ-2θ / π and 2θ / π data are separately generated by utilizing this and the sine wave waveform data is obtained by adding the data.
2θ / π can be obtained by truncating lower bits if necessary from the input phase data. Phase data L bit, sine wave waveform data M bit or (SINθ-2θ
/ Π) is generated by a look-up table in the ROM 10. At this time, the RO required for the sine wave generation circuit
The output bit number of M10 is the bit number M of the sine wave waveform data.
On the other hand, since it is M-3 bits, the number of bits of 2 bits can be further reduced by using the ROM capacity reducing method shown in (1).

(Reference: HT Nicholas, III,
et al. “A 150MHz Direct Digital Frequenc
y Synthesizer in 1.25-μm CMOS with-90d
Bc Sprious Performance ", IEEE.J.SSC, v
ol. 26, No. 12, DEC 1991)

[0014]

In the DDS circuit, the ROM of the sine wave generation circuit generally occupies the largest area.
For this reason, it is necessary to reduce the capacity of the ROM and reduce the size.
It greatly contributes to the reduction of the circuit scale of the entire DS. Also, R
The smaller the capacity of the OM, the more advantageous it is for lower power consumption and higher speed. Therefore, by further reducing the capacity of the ROM as compared with the conventional one, the DDS circuit itself can be downsized, the power consumption can be reduced, and the speed can be increased.

[0015]

According to the present invention, in order to further reduce the capacity of a ROM used in a sine wave generation circuit as compared with a conventional one, a 1/4 sine waveform generation circuit from 0 to π / 2 is used when the phase is 0. Of the data generated by the device 1 in the phases 0 to π / 4, and the device 1 that generates data that linearly increases from the value of the sine wave waveform data of 1 to the value of the sine wave waveform data when the phase is π / 2. Generates data with a value of 1/4 and phase π /
Π / of the data of 0 to π / 4 in 4 to π / 2
Device 2 for generating data that changes in a triangular shape symmetrical to 4
And a device 3 that generates a difference between the sum of the output data of the devices 1 and 2 and the waveform data of the sine wave. By adding the output data of the devices 1, 2, and 3, the sine wave waveform data is obtained. obtain.

[0016]

FIG. 8 shows the ratio of signals output from the above devices. FIG. 8B shows components of each output (data A to C) output from the device 1, the device 2, and the device 3,
FIG. 8 (a) shows the situation when these components are added together. The output data (data A) of the device 1 and the output data (data B) of the device 2 are linear data, respectively, and their magnitudes are represented by the powers of 2 of the phase data. 2 can be configured by a simple logic gate. Since the output data (data C) of the device 3 needs to be recorded in advance, only the device 3 is configured by the ROM. Data C is compared to the desired sine wave waveform data,
The size is 1/8 or less. Therefore, the number of output bits of the ROM can be reduced by 3 bits as compared with the case where the sine wave waveform data is directly output from the ROM.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an embodiment of this patent. Further, FIG. 2 is a diagram in which data changes in the circuit of the embodiment are written in an analog signal image. Bit inverter 2 in FIG.
Is a circuit for realizing the function represented by the formula (1) in the prior art, and is realized by a single EX-OR stage. The output of the first bit inverter 2 is data corresponding to a phase of 0 to π / 2 as described in the section of the prior art. Using this as an input, sine wave waveform data for phases 0 to π / 2 is obtained by separately generating the following three data and adding them. The data A (A [1: M-1]) is data that linearly increases from the value of the sine wave waveform data when the phase is 0 to the value of the sine wave waveform data when the phase is π / 2. It is obtained by extracting the upper M-1 bits of 1: L-2]. In order to ensure the accuracy of the sine wave waveform data, L generally needs to be sufficiently larger than M.
Therefore, A [1: M-1] is obtained only by a simple bit truncation process and does not require a gate. The data B (B [1: M-4]) is data having a value of ¼ of the data A in the phases 0 to π / 4, and the phase π / 4.
Up to π / 2, π / 4 of the above-mentioned data of 0 to π / 4
Data that is symmetrical with respect to the upper M-4 bit (P [L-3)-of P [1: L-3] by the second bit inverter 3.
(M-4): L-3]), using P [L-2], if P [L-2] is 1, it is inverted, and if it is 0, non-inverted processing is performed to obtain a triangular shape. This is changing data. This is realized by one stage of EX-OR gate. Data C (C [1: M-4]) is data for correction, and is data A and data B between phases 0 to π / 2.
Difference between the sum of and the sine wave waveform data, that is,

[0018]

(Equation 3)

It is the data of This data is generated by storing it in the ROM 4 as a look-up table in advance. A sine wave half-wave rectified waveform is obtained by adding the above three amplitude data by the adder. The bit inverter 3 is used to invert / non-invert half-wave rectified waveform data according to the value of PHA [L], whereby M-bit sinusoidal waveform data SIN [1: M] is obtained.

As an example, the size of the ROM in each of the following methods when the input of the waveform generation circuit of the phase accumulator is 12 bits and the output is 10 bits will be compared. (1) Method shown in the embodiment, (2) Method in which all waveform data is generated by ROM, (3) Method shown in Conventional Example 1, (4) Method shown in Conventional Example 2.

Number of input words Number of output bits Capacity Remarks (1) 1024 6 6144 (2) 4096 10 40960 (3) 1024 9 9216 (4) 1024 7 7168

[0022]

The present invention reduces the ROM capacity required by adding a simple logic circuit in a DDS that generates a sine wave, thereby reducing the circuit scale.
It is possible to reduce power consumption and increase operating speed.

[Brief description of drawings]

[Figure 1] Basic DDS configuration

FIG. 2 is a configuration of a DDS shown in Conventional Example 1.

FIG. 3 is an image of sine wave waveform generation of DDS shown in Conventional Example 1.

FIG. 4 is an image of sine wave waveform generation in Conventional Example 2.

FIG. 5 is a configuration example of a sine wave generation circuit shown in Conventional Example 2.

FIG. 6 is an image of sinusoidal waveform generation according to the present invention.

FIG. 7 is a configuration of a first embodiment of the present invention.

FIG. 8 is an image of generating a sine wave according to the first embodiment.

[Explanation of symbols]

 1 Phase Accumulator 2 Bit Inverter 3 Bit Inverter 4 ROM 5 Full Adder 6 Bit Inverter 7 Waveform Generation Circuit 8 1/4 Sine Wave Generation Circuit 9 Bit Inverter 10 ROM

Claims (1)

[Claims] 1. A sine waveform generation circuit for generating sine wave waveform data with respect to an arbitrary phase data input, and a phase accumulator for cumulatively adding arbitrary phase steps at fixed time intervals to generate phase data at a certain time. Of the direct logic synthesis type synthesizer, the output of the phase accumulator is input to the sine wave waveform generation circuit to sequentially output sine wave waveform data to obtain sine wave waveform data having a desired frequency. 0 as a waveform generator
It has a 1/4 sine wave waveform generation circuit that generates signal waveform data for the input of phase data of up to π / 2, and a bit inversion circuit is inserted at the input / output of this 1/4 sine wave waveform generation circuit to invert In a synthesizer that uses a waveform generation circuit that generates waveform data of 0 to 2π by controlling inversion, a phase 0 is used as the 1/4 sine wave waveform generation circuit.
A device 1 for generating data that linearly increases from the value of the sine wave waveform data when the phase is 0 to the value of the sine wave waveform data when the phase is π / 2 in the range of π / 2 to π / 2; The data having a value of 1/4 of the data generated by the device 1 is generated up to / 4, and the 0-value is generated in the phase π / 4 to π / 2.
The device 1 has a device 2 that generates data that is symmetric to π / 4 of the π / 4 data, and a device 3 that generates a difference between the sum of the output data of the devices 1 and 2 and the waveform data of the sine wave. A synthesizer circuit using a waveform generating circuit, wherein sine wave waveform data is obtained by adding output data of the device 3.