JPH08130222A - High-output semiconductor device - Google Patents

High-output semiconductor device

Info

Publication number
JPH08130222A
JPH08130222A JP28865594A JP28865594A JPH08130222A JP H08130222 A JPH08130222 A JP H08130222A JP 28865594 A JP28865594 A JP 28865594A JP 28865594 A JP28865594 A JP 28865594A JP H08130222 A JPH08130222 A JP H08130222A
Authority
JP
Japan
Prior art keywords
pad
hbt
emitter
collector
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28865594A
Other languages
Japanese (ja)
Other versions
JP2655104B2 (en
Inventor
Nobuyuki Hayama
信幸 羽山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6288655A priority Critical patent/JP2655104B2/en
Publication of JPH08130222A publication Critical patent/JPH08130222A/en
Application granted granted Critical
Publication of JP2655104B2 publication Critical patent/JP2655104B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To uniformly operate each HBT on a chip, and improve gain,and power efficiency, by making the longitudinal directions of emitters of a plurality of transistors radial, and arranging the transistors on a closed loop, at nearly equal intervals. CONSTITUTION: HBT's constituted of base electrodes 6, emitter electrodes 8 and collector electrodes 7 are arranged at a plurality of positions on a circumference. Each of the emitter electrodes 8 is connected with an emitter pad 4 arranged inside the circumference. The distance between the electrode 8 and the pad 4 is set almost constant. The emitter pad 4 is connected with ground conductor formed on the back, through a viahole 9 penetrating a semi-insulating GaAs substrate 1. The base electrode 6 of each of the HBT's is electrically connected with a base pad 2 through a base electrode wiring 6a outside the circumference. The collector electrode 7 is electrically connected with a collector pad 3 through a collector wiring 7a. Thereby electric uniformity in the HBT's can be ensured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高出力用半導体装置、
特に複数のトランジスタを並列に接続して高出力化を図
る半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-output semiconductor device,
In particular, the present invention relates to a semiconductor device in which a plurality of transistors are connected in parallel to achieve high output.

【0002】[0002]

【従来の技術】通信機器の発達とともに高周波高出力用
半導体装置の需要が大幅に伸びている。特に、自動車電
話、携帯電話等に代表される情報端末携帯機器では、電
池駆動で高出力動作、長時間通話を行うため、高効率で
動作する高出力用半導体装置が必要となっている。即
ち、半導体装置内部での電力損失を極力小さくし、印加
する直流電力を効率よく高周波電力に変換する高出力用
半導体装置が望まれている。
2. Description of the Related Art The demand for high-frequency and high-power semiconductor devices has greatly increased with the development of communication equipment. In particular, in information terminal mobile devices typified by car phones, mobile phones, and the like, a high-power semiconductor device that operates with high efficiency is required because battery-powered high-power operation and long-term communication are performed. That is, there is a demand for a high-output semiconductor device that minimizes power loss inside the semiconductor device and efficiently converts the applied DC power into high-frequency power.

【0003】GaAs半導体を用いた電界効果トランジ
スタは、このような需要を満たす高出力用半導体装置と
して実用化、量産化が進められているが、近年、化合物
半導体のヘテロ接合を利用したバイポーラトランジスタ
(以下「HBT」という)が、その優れた高周波特性と
高電流駆動能力から、高出力用半導体装置として注目さ
れている。
A field effect transistor using a GaAs semiconductor has been put into practical use and mass-produced as a high-output semiconductor device satisfying such demands. HBT) has attracted attention as a high-output semiconductor device because of its excellent high-frequency characteristics and high current driving capability.

【0004】このような高出力半導体装置では、高周波
の大電力を取り扱うため、半導体基板上に複数のトラン
ジスタを配置し、これらを互いに並列形態に接続するこ
とで高出力化を図っている。
In such a high-output semiconductor device, in order to handle high-frequency high power, a plurality of transistors are arranged on a semiconductor substrate, and these transistors are connected to each other in parallel to achieve high output.

【0005】例えば、特開平5−315352号公報に
は、チップサイズを大きくすることなく、各トランジス
タセルから接地用パッドまでの配線距離を大幅に低減し
て且つ等しくし、同時に入力パッドから各トランジスタ
セルを経て出力パッドに至る電気長をいずれのトランジ
スタセルでも等しくし、高周波におけるトランジスタの
利得を改善することを目的として、図2に示すように、
複数のHBTを基板上に配列した高出力半導体装置が提
案されている。
For example, Japanese Patent Application Laid-Open No. 5-315352 discloses that the wiring distance from each transistor cell to the ground pad is greatly reduced and equalized without increasing the chip size, and at the same time, each transistor is connected from the input pad to each transistor. As shown in FIG. 2, for the purpose of equalizing the electrical length from the cell to the output pad in any transistor cell and improving the gain of the transistor at high frequencies, as shown in FIG.
A high-output semiconductor device in which a plurality of HBTs are arranged on a substrate has been proposed.

【0006】図2を参照して、トランジスタ領域15内
に複数のHBTが一列に並んで配置され、各HBTのベ
ース電極16、コレクタ電極17、及びエミッタ電極1
8はそれぞれ互いに接続され、それぞれベースパッド1
2、コレクタパッド13、エミッタパッド14に接続さ
れている。
Referring to FIG. 2, a plurality of HBTs are arranged in a line in a transistor region 15, and a base electrode 16, a collector electrode 17, and an emitter electrode 1 of each HBT are provided.
8 are connected to each other and each of the base pads 1
2, the collector pad 13 and the emitter pad 14.

【0007】ベースパッド12はトランジスタセルの並
んだ方向の延長線上に配置され、トランジスタセルをは
さんでベースパッドの反対側にコレクタパッド13が配
置され、ベースパッド12とコレクタパッド13とを結
ぶ直線の直角方向にトランジスタセルの近傍にエミッタ
パッド14が形成されている。
The base pad 12 is arranged on an extension line in the direction in which the transistor cells are arranged, a collector pad 13 is arranged on the opposite side of the base pad across the transistor cell, and a straight line connecting the base pad 12 and the collector pad 13 is formed. An emitter pad 14 is formed in the vicinity of the transistor cell in the direction perpendicular to the.

【0008】エミッタパッド14は接地用端子、ベース
パッド12は入力用端子、コレクタパッド13は出力用
端子として外部回路との接続に用いる。
The emitter pad 14 is used as a ground terminal, the base pad 12 is used as an input terminal, and the collector pad 13 is used as an output terminal for connection to an external circuit.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、このよ
うにチップ上で複数のHBTを一列に配列した構成で
は、ベースパッド12、及びコレクタパッド13を通じ
て電源として投入された直流電力の一部、あるいは信号
としての高周波電力の一部が電力損失として熱に変換さ
れる際、隣接するHBTの熱的干渉により、配列の中央
近傍のHBTの温度上昇が周辺部のHBTに比べ大きく
なる。
However, in such a configuration in which a plurality of HBTs are arranged in a line on the chip, a part of the DC power supplied as a power supply through the base pad 12 and the collector pad 13 or a signal When a part of the high frequency power is converted into heat as power loss, the temperature rise of the HBT near the center of the array becomes larger than that of the peripheral HBT due to thermal interference of the adjacent HBT.

【0010】また、これに伴って、中央近傍のHBTに
コレクタ電流が集中するようになり、ますます温度上昇
が激しくなり、中央近傍のHBTに熱が集中するように
なる。
Along with this, the collector current concentrates on the HBT near the center, the temperature rises more and more, and the heat concentrates on the HBT near the center.

【0011】この結果、全HBTの均一な動作ができな
くなり、利得の低下、電力効率の低下を招いている。場
合によっては、このような一連の熱暴走により素子の劣
化、破壊の原因にもなっていた。
As a result, uniform operation of all HBTs cannot be performed, resulting in a decrease in gain and a decrease in power efficiency. In some cases, such a series of thermal runaways may cause deterioration or destruction of the element.

【0012】ところで、各HBTを均一に動作させるた
めに、各HBTのエミッタ電極と接地間にバラスト抵抗
を挿入することにより、熱暴走を防ぎ、均熱化を図る手
段がとられるが、これはトランジスタの高周波特性を損
なうことになり、高周波領域での使用には得策ではな
い。
By the way, in order to make each HBT operate uniformly, a means for preventing thermal runaway and equalizing the temperature by inserting a ballast resistor between the emitter electrode of each HBT and the ground is used. This impairs the high-frequency characteristics of the transistor, and is not advantageous for use in a high-frequency region.

【0013】また、バラスト抵抗を作成するための製造
プロセスの増加をもたらす。
Further, the number of manufacturing processes for producing a ballast resistor increases.

【0014】更に、各HBTの配置間隔を広げることで
素子の熱的干渉を低減する手法も採り得るが、チップ面
積の増加を伴うためチップ価格の上昇が避けられない。
Further, a method of reducing the thermal interference of the elements by increasing the arrangement intervals of the HBTs can be adopted, but an increase in chip area is unavoidable due to an increase in chip area.

【0015】従って、本発明の目的は前記従来の問題点
を解決し、チップ上で複数のHBTを均一に動作させ、
利得の向上、電力効率の向上を図った高出力半導体装置
を提供することにある。
Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, to allow a plurality of HBTs to operate uniformly on a chip,
It is an object of the present invention to provide a high-output semiconductor device in which the gain and the power efficiency are improved.

【0016】[0016]

【課題を解決するための手段】前記目的を達成するた
め、本発明の高出力半導体装置は、半導体基板上に配置
された複数のトランジスタを互いに並列形態に接続して
高出力動作を行う半導体装置において、前記複数のトラ
ンジスタのエミッタの長手方向が放射状となり、所定の
閉曲線上に前記複数のトランジスタを略等間隔で配置す
るとともに、各トランジスタの電気的接地点を前記所定
の閉曲線の内側に配置したことを特徴とする。
In order to achieve the above object, a high-power semiconductor device according to the present invention performs a high-output operation by connecting a plurality of transistors arranged on a semiconductor substrate in parallel with each other. The longitudinal direction of the emitters of the plurality of transistors is radial, and the plurality of transistors are arranged at substantially equal intervals on a predetermined closed curve, and the electrical ground point of each transistor is disposed inside the predetermined closed curve. It is characterized by the following.

【0017】また、本発明の高出力半導体装置において
は、前記電気的接地点が、前記半導体基板を貫通するヴ
ィアホールを介して、前記半導体基板裏面の接地導体に
接続されていることを特徴とする。
Further, in the high-power semiconductor device according to the present invention, the electrical ground point is connected to a ground conductor on the back surface of the semiconductor substrate via a via hole penetrating the semiconductor substrate. I do.

【0018】そして、本発明の高出力半導体装置におい
ては、好ましくは、前記所定の閉曲線が円周とされ、前
記電気的接地点が前記円周の略中心部に配置されること
を特徴とする。
In the high-power semiconductor device according to the present invention, preferably, the predetermined closed curve is a circle, and the electric ground point is arranged at a substantially central portion of the circle. .

【0019】[0019]

【作用】本発明によれば、全てのエミッタ電極が等間隔
で相隣るため、各HBTの発熱、及び熱干渉に伴って、
特定のHBTに熱が集中することが回避される。
According to the present invention, since all the emitter electrodes are adjacent to each other at equal intervals, heat generation and thermal interference of each HBT cause
Concentration of heat on a particular HBT is avoided.

【0020】また、本発明によれば、電気的接地点から
各エミッタ電極までの配線距離は全て等しくできるた
め、配線部での寄生素子(抵抗、インダクタンス、容
量)も等しくなり、各トランジスタを均一動作できる。
Further, according to the present invention, since the wiring distances from the electrical ground point to each emitter electrode can be all equal, the parasitic elements (resistance, inductance, capacitance) in the wiring portion are also equal, and each transistor can be made uniform. Can work.

【0021】さらに、本発明によれば、エミッタ電極、
エミッタパッド及びヴィアホールを通じての各トランジ
スタのチップ裏面への放熱経路が、全く等しいことも均
熱化に寄与する。従って、本発明では、全てのチップ上
の全てのトランジスタを電気的にも熱的にも均一に動作
させることができる。
Further, according to the present invention, an emitter electrode,
The fact that the heat radiation paths to the back surface of the chip of each transistor through the emitter pad and the via hole are exactly the same also contributes to the uniform heat distribution. Therefore, according to the present invention, all the transistors on all the chips can be uniformly operated both electrically and thermally.

【0022】[0022]

【実施例】以下、本発明について図面を参照して実施例
に即して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings according to embodiments.

【0023】図1は、本発明の一実施例に係るトランジ
スタとしてAlGaAs/GaAsHBTを用いた高出
力半導体装置の平面図である。
FIG. 1 is a plan view of a high-power semiconductor device using an AlGaAs / GaAs HBT as a transistor according to one embodiment of the present invention.

【0024】図1を参照して、ベース電極6、エミッタ
電極7、及びコレクタ電極8から構成されるHBTが複
数個、所定円の円周上に等間隔で配置されている。各々
のエミッタ電極7は、HBTの並ぶ円周の内側に配置さ
れたエミッタパッド4に接続されている。そして、エミ
ッタ電極7とエミッタパッド4間の距離は略同一に設定
されている。
Referring to FIG. 1, a plurality of HBTs each comprising a base electrode 6, an emitter electrode 7, and a collector electrode 8 are arranged at regular intervals on the circumference of a predetermined circle. Each of the emitter electrodes 7 is connected to an emitter pad 4 arranged inside the circumference where the HBTs are arranged. The distance between the emitter electrode 7 and the emitter pad 4 is set substantially equal.

【0025】また、エミッタパッド4は半絶縁性のGa
As基板1を貫通するヴィアホール9を通じて、GaA
s基板1の裏面に設けられた接地導体(図示せず)に接
続されている。
The emitter pad 4 is made of semi-insulating Ga.
Through the via hole 9 penetrating the As substrate 1, GaA
The substrate 1 is connected to a ground conductor (not shown) provided on the back surface of the substrate 1.

【0026】さらに、各HBTのベース電極6はHBT
が配置された円周の外側のベース電極配線6aを通じて
ベースパッド2に電気的に接続されている。コレクタ電
極7はコレクタ電極7aを通じてコレクタパッド3に電
気的に接続されている。
Further, the base electrode 6 of each HBT is
Are electrically connected to the base pad 2 through the base electrode wiring 6a outside the circumference on which is disposed. Collector electrode 7 is electrically connected to collector pad 3 through collector electrode 7a.

【0027】本実施例のパターン配列においては、チッ
プキャリアに実装される際、エミッタパッド4は裏面の
接地導体を通じて電気的に接地状態となり、ベースパッ
ド2及びコレクタパッド3は、ワイヤボンディング等に
よりそれぞれ入力端子及び出力端子として機能する。
In the pattern arrangement of this embodiment, when mounted on a chip carrier, the emitter pad 4 is electrically grounded through the ground conductor on the back surface, and the base pad 2 and the collector pad 3 are respectively connected by wire bonding or the like. Functions as an input terminal and an output terminal.

【0028】本実施例によれば、電気的接地点から各エ
ミッタ電極8までの配線距離は複数のHBT間で全て等
しくできるため、配線部における寄生素子(抵抗、イン
ダクタンス、容量)も等しくなり、各HBT間における
電気的均一性を確保することができる。また、各HBT
からの発熱は、エミッタ電極8、エミッタパッド4、ヴ
ィアホール9等を経由して基板の裏面から放熱される
が、この放熱経路も各HBTで等しくなるため、各HB
Tの熱的均一化が確保され、従って、チップ上の全ての
HBTを均一に動作させることができ、利得の向上、電
力効率の向上が図られる。
According to the present embodiment, since the wiring distances from the electrical ground point to each emitter electrode 8 can be all equal among a plurality of HBTs, the parasitic elements (resistance, inductance, and capacitance) in the wiring portion are also equal, Electrical uniformity among the HBTs can be ensured. In addition, each HBT
Is radiated from the back surface of the substrate via the emitter electrode 8, the emitter pad 4, the via hole 9, and the like.
Thermal uniformity of T is ensured, and therefore, all HBTs on the chip can be operated uniformly, and gain and power efficiency are improved.

【0029】また、本実施例によれば、エミッタ電極8
が互いに等間隔で相隣るように配設されるため、特定の
HBTに電流集中、熱集中が生ずるということはなく、
HBTの特性劣化及び破壊が回避され、高信頼化、高歩
留化が達成される。
Further, according to the present embodiment, the emitter electrode 8
Are arranged so as to be adjacent to each other at equal intervals, current concentration and heat concentration do not occur in a specific HBT.
Deterioration and destruction of HBT characteristics are avoided, and high reliability and high yield are achieved.

【0030】以上本発明を上記実施例に即して説明した
が、本発明は上記態様にのみ限定されるものでなく、本
発明の原理に準ずる各種態様を含む。例えば、上記実施
例では、HBTを真円上に配置した構成を示したが、楕
円上に配置されている場合であっても、HBTが等間隔
で配列した場合には、同様の効果を達成する。
Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment but includes various embodiments according to the principle of the present invention. For example, in the above-described embodiment, the configuration in which the HBTs are arranged on a perfect circle is shown. However, even when the HBTs are arranged on an ellipse, the same effect is achieved when the HBTs are arranged at equal intervals. I do.

【0031】[0031]

【発明の効果】以上説明したような本発明(請求項1)
によれば、全てのエミッタ電極が等間隔で相隣るため、
各トランジスタの放熱に伴って、特定のトランジスタに
熱が集中することが回避されるという効果を有する。
The present invention as described above (Claim 1)
According to, all the emitter electrodes are adjacent to each other at equal intervals,
This has an effect that heat is prevented from being concentrated on a specific transistor due to heat dissipation of each transistor.

【0032】また、本発明(請求項1)によれば、電気
的接地点から各エミッタ電極までの配線距離は全て等し
くできるため、配線部での寄生素子(抵抗、インダクタ
ンス、容量)も等しくなり、各トランジスタを電気的均
一性を保てる。
Further, according to the present invention (claim 1), since the wiring distances from the electrical ground point to the respective emitter electrodes can be made equal, the parasitic elements (resistance, inductance, capacitance) in the wiring portion also become equal. , Each transistor can maintain electrical uniformity.

【0033】さらに、本発明(請求項2)によれば、ト
ランジスタからの発熱は、エミッタ電極、エミッタパッ
ド、ヴィアホール等を経由して基板の裏面から放熱され
るが、この放熱経路も各トランジスタで同じとなるた
め、各トランジスタの均熱性が保持される。
Further, according to the present invention (claim 2), heat generated from the transistor is radiated from the back surface of the substrate via the emitter electrode, the emitter pad, the via hole, and the like. , The temperature uniformity of each transistor is maintained.

【0034】このように、本発明(請求項1、2)によ
れば、チップ上の全てのトランジスタを均一に動作させ
ることができ、利得の向上、電力効率の向上が図られ
る。
As described above, according to the present invention (claims 1 and 2), all the transistors on the chip can be operated uniformly, and the gain and the power efficiency can be improved.

【0035】また、本発明(請求項1、2)によれば、
特定のトランジスタに電流集中、熱集中がないため、こ
れに伴うトランジスタの特性劣化及び破壊が避けられ高
信頼化、高歩留化が図れる。
According to the present invention (claims 1 and 2),
Since current concentration and heat concentration do not occur in a specific transistor, deterioration and destruction of characteristics of the transistor due to the current concentration and heat concentration can be avoided, and high reliability and high yield can be achieved.

【0036】そして、好ましくは、本発明(請求項3)
のように構成した場合にも上記各効果を同様にして達成
する。
Preferably, the present invention (claim 3)
The same effects can be achieved in the same manner as described above.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の高出力半導体装置の一実施例の構成を
示す平面図である。
FIG. 1 is a plan view showing a configuration of an embodiment of a high-power semiconductor device of the present invention.

【図2】従来の高出力半導体のトランジスタの配置を示
す平面図である。
FIG. 2 is a plan view showing an arrangement of conventional high-power semiconductor transistors.

【符号の説明】[Explanation of symbols]

1、11 GaAs基板 2、12 ベースパッド 3、13 コレクタパッド 4、14 エミッタパッド 15 トランジスタ領域 6、16 ベース電極 6a ベース電極配線 7、17 コレクタ電極 7a コレクタ電極配線 8、18 エミッタ電極 9 ヴィアホール 1, 11 GaAs substrate 2, 12 base pad 3, 13 collector pad 4, 14 emitter pad 15 transistor region 6, 16 base electrode 6a base electrode wiring 7, 17 collector electrode 7a collector electrode wiring 8, 18 emitter electrode 9 via hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に配置された複数のトランジ
スタを互いに並列形態に接続して高出力動作を行う半導
体装置において、 前記複数のトランジスタのエミッタの長手方向が放射状
となり、所定の閉曲線上に前記複数のトランジスタを略
等間隔で配置するとともに、各トランジスタの電気的接
地点を前記所定の閉曲線の内側に配置したことを特徴と
する高出力半導体装置。
1. In a semiconductor device for performing a high output operation by connecting a plurality of transistors arranged on a semiconductor substrate in parallel to each other, the emitters of the plurality of transistors have a radial direction in which a predetermined closed curve is formed. A high output semiconductor device, wherein the plurality of transistors are arranged at substantially equal intervals, and an electric ground point of each transistor is arranged inside the predetermined closed curve.
【請求項2】前記電気的接地点が、前記半導体基板を貫
通するヴィアホールを介して、前記半導体基板裏面の接
地導体に接続されていることを特徴とする特許請求の範
囲第1項記載の高出力半導体装置。
2. The electric ground point is connected to a ground conductor on the back surface of the semiconductor substrate via a via hole penetrating the semiconductor substrate. High power semiconductor device.
【請求項3】前記所定の閉曲線が円周とされ、前記電気
的接地点が前記円周の略中心部に配置されることを特徴
とする請求項1記載の高出力半導体装置。
3. The high-power semiconductor device according to claim 1, wherein the predetermined closed curve is a circle, and the electrical ground point is arranged substantially at the center of the circle.
JP6288655A 1994-10-31 1994-10-31 High power semiconductor devices Expired - Lifetime JP2655104B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6288655A JP2655104B2 (en) 1994-10-31 1994-10-31 High power semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6288655A JP2655104B2 (en) 1994-10-31 1994-10-31 High power semiconductor devices

Publications (2)

Publication Number Publication Date
JPH08130222A true JPH08130222A (en) 1996-05-21
JP2655104B2 JP2655104B2 (en) 1997-09-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP6288655A Expired - Lifetime JP2655104B2 (en) 1994-10-31 1994-10-31 High power semiconductor devices

Country Status (1)

Country Link
JP (1) JP2655104B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999026294A1 (en) * 1997-11-13 1999-05-27 Northrop Grumman Corporation High power density microwave hbt with uniform signal distribution
KR20030075993A (en) * 2002-03-22 2003-09-26 삼성전자주식회사 Heterojunction bipolar transistor having horse shoe type emitter node and method of manufacturing the same
US7235860B2 (en) 2001-07-27 2007-06-26 Nec Electronics Corporation Bipolar transistor including divided emitter structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999026294A1 (en) * 1997-11-13 1999-05-27 Northrop Grumman Corporation High power density microwave hbt with uniform signal distribution
US7235860B2 (en) 2001-07-27 2007-06-26 Nec Electronics Corporation Bipolar transistor including divided emitter structure
US7239007B2 (en) 2001-07-27 2007-07-03 Nec Electronics Corporation Bipolar transistor with divided base and emitter regions
KR20030075993A (en) * 2002-03-22 2003-09-26 삼성전자주식회사 Heterojunction bipolar transistor having horse shoe type emitter node and method of manufacturing the same

Also Published As

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