JPH08129567A - Delay time evaluating device - Google Patents

Abstract

PURPOSE: To evaluate the delay time of an electric circuit which is larger in scale than a conventional delay time evaluating device. CONSTITUTION: A block name input part 1 and a port name input part 2 are provided and the block name of the electronic circuit and the names of ports connected to respective blocks are inputted. Further, a circuit delay time input part 3 and a circuit driving information input part 4 are provided and driving information on delay times between ports, an input load, etc., is inputted. Those data are edited by a data editing part 5 and stored on a storage medium 9. When a data retrieval part 6 retrieves a port name, a signal path in the whole electronic circuit is calculated and an adder 8 calculates the delay time of the whole electronic circuit from the delay time information on the respective circuit blocks. Consequently, the operation time is shortened and the delay time of the electronic circuit which is larger in scale can be evaluated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time evaluation device used in the development of electronic circuits.

[0002]

2. Description of the Related Art Delay time evaluation devices are currently used to evaluate the delay time of electronic circuits. A conventional delay time evaluation device is designed by an electronic circuit design device, and in an electronic circuit that is a target of delay time evaluation, the connection state between the logic circuits forming this electronic circuit is checked and stored in advance in the delay time evaluation device. The delay time of the entire electronic circuit has been obtained by calculating the delay times of all the logic circuits existing between the input port and the output port based on the delay time information regarding the existing logic circuit.

[0003]

However, the conventional delay time evaluation apparatus must also store the information on the connection relationship between the logic circuits, and the electronic delay time evaluation apparatus can be used in accordance with the storage capacity of the storage medium used for the delay time evaluation. There is a problem in that the circuit scale that can evaluate the delay time is limited in the entire circuit. Therefore, the delay time cannot be evaluated in a large-scale electronic circuit having an information amount exceeding the storage capacity of the storage medium.

The present invention has been made in view of such conventional problems, and the delay time in a large-scale electronic circuit can be evaluated only by inputting the minimum information to the storage medium. The purpose is to realize a delay time evaluation device.

[0005]

According to a first aspect of the present invention, there are provided an electronic circuit designing apparatus, a block name input section for reading the names of a plurality of electronic circuit blocks constituting an electronic circuit, and an electronic circuit designing apparatus. , A port name input section for reading the input / output port name of the electronic circuit block, a circuit delay time input section for reading the circuit delay time from the electronic circuit design device to one input / output port, and a circuit delay The circuit delay time read by the time input unit is stored in the storage medium, and the data editing unit stores it in the storage medium in association with the port name read by the port name input unit and the block name read by the block name input unit. Check the connection status between electronic circuit blocks by searching for the same port name from the existing information, and read the circuit delay time of the electronic circuit blocks in the connection relationship. A data search unit and an adder that adds the respective circuit delay times read from the storage medium by the data search unit, and the output of the adder is used to configure a plurality of electronic circuit blocks as constituent elements. It is characterized in that the delay time of a large-scale electronic circuit as a part is evaluated.

According to a second aspect of the present invention, a block name input section for reading the names of a plurality of electronic circuit blocks constituting an electronic circuit from the electronic circuit designing device, and an electronic circuit block input from the electronic circuit designing device. A port name input section for reading the output port name, a circuit delay time input section for reading the circuit delay time from one input / output port to another input / output port from the electronic circuit design apparatus, and an electronic circuit design apparatus Circuit drive information input section that reads circuit drive information including input load of input / output port of block and output intensity of input / output port, and circuit drive information read by circuit drive information input section and circuit read by circuit delay time input section The delay time is stored in the first storage medium in association with the port name read by the port name input section and the block name read by the block name input section. The data editing unit and the data search that searches the connection status between electronic circuit blocks by searching the same port name from the information stored in the storage medium and reads the circuit drive information and circuit delay time of the electronic circuit blocks in the connection relationship Block and the electronic circuit block are connected, the delay time between blocks is calculated based on the circuit drive information read by the data search unit, and the port name and block name input by the port name input unit are input. An inter-block delay calculation unit for storing in the first storage medium or the second storage medium corresponding to the block name read by the unit, and a circuit read from the first or second storage medium by the data search unit An adder for adding the delay time and the inter-block delay time, and using the output of the adder to configure a plurality of electronic circuit blocks It is characterized in that performing a delay time evaluation of large-scale electronic circuits part.

[0007]

According to the invention of claim 1 of the present application having the above characteristics, the names of electronic circuit blocks, the names of input / output ports, and the delay times of the respective blocks obtained by the electronic circuit design device are respectively taken in and the connection relationship is established. To retrieve information about electronic circuit blocks and input / output ports. Then, the circuit delay time of each electronic circuit block is added by the adder to calculate the signal delay time of the entire electronic circuit.

According to the invention of claim 2 of the present application, not only the name of the electronic circuit block, the name of the input / output port, and the delay time of each block obtained from the electronic circuit design device, but also the circuit drive of the electronic circuit block By inputting the information, the delay time between the electronic circuit blocks is calculated based on the input load of the input port and the output intensity of the output port.
Then, the adder adds the delay time between the blocks, which has a connection relationship with the delay time of the electronic circuit block itself. By doing so, the signal delay time in the entire electronic circuit can be calculated more accurately.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A delay time evaluation device in each embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the delay time evaluation apparatus of the present invention.
2 to 5 show an example of a method of storing the circuit delay time required for delay time evaluation, the circuit drive information, and the delay time between electronic circuit blocks in association with the port name and block name of the electronic circuit. 2 to 5, it is assumed that the electronic circuit that is the target of delay time evaluation includes a plurality of blocks and an input port and an output port connected to each block. Here, the names of electronic circuit blocks (called electronic circuit blocks) are block 1, block 2, block 3, ..., Block A, block B, block C.
Call it ... For example, in block A, input port names are called port 1, port 2, port 3 ..., and output port names are called port A, port B, port C.

First, the delay time evaluation apparatus of the first embodiment (claim 1) will be described. In FIG. 1, the name of each electronic circuit block is input to the block name input unit 1 from the information obtained from the existing electronic circuit design device, the name of the port in each electronic circuit block is input to the port name input unit 2, and each electronic circuit block is input. The circuit delay time of 1 is taken into the circuit delay time input section 3, respectively. The data editing unit 5 creates a table in which the circuit delay time is associated with the port name and the block name as shown in FIGS. 2 and 3, and stores the table in the storage medium 9. For example, as shown in FIG. 2, in the block A, a table of circuit delay times for all signal paths from the input ports 1 to 6 to the output ports A to F is created and the result is stored. Also in the block B of FIG. 3, the same table as the block A of FIG. 2 is created.

In order to check the delay time of the entire electronic circuit blocks having a connection relationship, the data search section 6 refers to the information in the storage medium 9 and the same port as shown in block A of FIG. 2 and block B of FIG. Check if there is an electronic circuit block with the given name. Then, the circuit search time in the electronic circuit block confirmed to have the same port name is searched by the data search unit 6 by the port name and the block name. In this way, information is read from the storage medium 9 and input to the adder 8 while tracking the connection relationship of the electronic circuit blocks. Adder 8
It is possible to output the delay time of the entire electronic circuit by sequentially adding the obtained circuit delay times.

Next, a delay time evaluation device according to a second embodiment (claim 2) of the present invention will be described. As shown in Figure 1,
First, the name of each electronic circuit block is taken into the block name input unit 1 from the information obtained from the existing electronic circuit design device. The name of the port in each electronic circuit block is input to the port name input unit 2, the circuit delay time of each electronic circuit block is input to the circuit delay time input unit 3, and the circuit drive information of each electronic circuit block is input to the circuit drive information input unit 4. Take in each. The circuit drive information refers to the input load of the input port of the electronic circuit block, the output intensity of the output port, and the like.

Next, the data editing section 5 creates a table in which circuit delay times are associated with each other as shown in FIGS. 2 and 3, and circuit drive information is associated with port names and block names as shown in FIG. To memorize. In this case, although the circuit delay time and the circuit drive information are stored in the same storage medium 9 in FIG. 1, they may be stored in different storage media.

In order to check the delay time of all electronic circuit blocks having a connection relationship, the data search section 6 refers to the information in the storage medium 9 and refers to the same port as in block A of FIG. 2 and block B of FIG. Check if there is an electronic circuit block with the given name. The signal delay time generated between the output port of the block A and the input port of the block B when the electronic circuit block A is connected to the electronic circuit block A via the input / output port of the other electronic circuit block B is called an inter-block delay time.
For the electronic circuit block which is confirmed by the data search unit 6 to have the same port name, the data search unit 6 outputs the circuit drive information regarding the port of the specified port name in order to calculate the inter-block delay time. It is passed from the storage medium 9 to the inter-block delay calculation unit 7.

The inter-block delay calculation unit 7 calculates the inter-block delay time based on the obtained circuit drive information by using the same method as the conventional delay time evaluation device. Then, data as shown in FIG. 5, that is, a list of inter-block delay times associated with port names and block names is stored in the storage medium 10. Here, the delay time between blocks is set to the dedicated storage medium 10
However, the circuit delay time and the circuit drive information may be stored in the same storage medium.

The data search unit 6 includes a storage medium 9 and a storage medium 1.
0 is searched for the data by the port name and the block name, and the circuit delay time stored in the storage medium 9 and the inter-block delay time stored in the storage medium 10 are added while tracing the connection relationship of the electronic circuit blocks. Give to vessel 8. Then, the adder 8 can obtain and output the delay time of the entire electronic circuit by sequentially adding the input circuit delay time and inter-block delay time.

[0017]

As described above, according to the present invention, the information necessary for delay time evaluation is limited to the port name, block name, delay time information, and circuit drive information. With a storage medium having the same storage capacity, it is possible to evaluate the delay time of a larger-scale electronic circuit. Further, by storing the circuit drive information in association with each port of the electronic circuit block, the circuit drive information can be automatically set for each port. Therefore, when designing a large-scale electronic circuit, it is possible to accurately evaluate the delay time and shorten the working time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a delay time evaluation device of the present invention.

FIG. 2 is a diagram showing an example (part 1) of a circuit delay time storage method.

FIG. 3 is a diagram showing an example (No. 2) of a circuit delay time storage method.

FIG. 4 is a diagram showing an example of a method of storing circuit drive information.

FIG. 5 is a diagram showing an example of a method of storing inter-block delay time.

[Explanation of symbols]

 1 block name input unit 2 port name input unit 3 circuit delay time input unit 4 circuit drive information input unit 5 data editing unit 6 data search unit 7 inter-block delay time calculation unit 8 adder 9, 10 storage medium

Claims (2)

[Claims] 1. A block name input section that reads the names of a plurality of electronic circuit blocks that form an electronic circuit from an electronic circuit designing device, and an input / output port name of the electronic circuit block that is read from the electronic circuit designing device. A port name input section, a circuit delay time input section for reading the circuit delay time from the one input / output port to the other input / output port from the electronic circuit design device, and a circuit read by the circuit delay time input section Delay time,
A data editing unit that stores the port name read by the port name input unit and the block name read by the block name input unit in a storage medium, and searches for the same port name from the information stored in the storage medium By checking the connection state between electronic circuit blocks,
A data search unit for reading out a circuit delay time of electronic circuit blocks in a connection relationship; and an adder for adding each circuit delay time read out from the storage medium by the data search unit, the adder A delay time evaluation device for evaluating a delay time of a large-scale electronic circuit having a plurality of electronic circuit blocks as a part of its constituent elements by using the output of the above. 2. A block name input unit that reads the names of a plurality of electronic circuit blocks that form an electronic circuit from the electronic circuit designing device, and an input / output port name of the electronic circuit block that is read from the electronic circuit designing device. A port name input section, a circuit delay time input section for reading a circuit delay time from the one input / output port to the other input / output port from the electronic circuit design apparatus, and the electronic circuit design apparatus from the electronic circuit A circuit drive information input unit that reads circuit drive information including an input load of an input / output port of the block and an output intensity of the input / output port, a circuit drive information read by the circuit drive information input unit, and a circuit delay time input unit. The circuit delay time corresponding to the port name read by the port name input section and the block name read by the block name input section. A data editing unit to be stored in one storage medium, and a connection state between the electronic circuit blocks is checked by searching for the same port name from the information stored in the storage medium, and circuit driving of electronic circuit blocks in a connection relationship is performed. A data search unit that reads out information and circuit delay time, and an inter-block delay time caused by connecting between the electronic circuit blocks are calculated based on the circuit drive information read by the data search unit, and the port name The first name is associated with the port name read by the input unit and the block name read by the block name input unit.
Inter-block delay calculation section to be stored in the storage medium or the second storage medium, and an addition for adding the circuit delay time and the inter-block delay time read from the first or second storage medium by the data search section. And a delay time evaluation apparatus for evaluating a delay time of a large-scale electronic circuit having a plurality of electronic circuit blocks as a part of its components, using the output of the adder.