JPH08129505A - Eeprom control unit - Google Patents

Abstract

PURPOSE: To shorten the write wait time of an EEPROM, to prevent a write conflict of the EEPROM, to prevent a write omission of the EEPROM, and to decrease the write frequency of the EEPROM without unnecessary writing to the EEPROM and unnecessary processing. CONSTITUTION: Tasks 4a-4d access a dummy memory 2a of a RAM 2 instead of accessing the EEPROM 3 in normal operation. An EEPROM processing routine 1 checks a write request flag 2b of the RAM 2 at constant intervals of time and writes the data of the dummy memory 2 in the EEPROM 3 on condition that there is a write request. The EEPROM processing routine 1 checks data of the EEPROM 3, page by page, unless there is the write request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM controller, and more particularly to an electrically writable and erasable non-volatile memory [hereinafter referred to as EEPROM (Electrically).
Erasable & Programmable Re
Ad Only Memory)].

[0002]

2. Description of the Related Art In a microprocessor system having an EEPROM, there are some restrictions on writing and reading data to and from the EEPROM. That is, since the EEPROM memory is divided into pages, the CPU can continuously write only to the data within the same page. In that case, in order to write data to another page, it is necessary to wait for the end of the write operation (hereinafter, referred to as a write cycle) to the current page, and this write cycle is about 10 ms.

If the next address and data are not input within a fixed time (about 100 μs) when writing data in the same page, a write cycle is started.
If writing is performed during this write cycle, the write data is not guaranteed. Further, since the number of writings to the EEPROM has a life, it is necessary to avoid useless writing to the EEPROM.

Therefore, the control shown in FIGS. 5 to 7 is required for writing to the EEPROM. First,
As a simple method, after writing data (step S11 in FIG. 5), write cycle time (about 7 to 10 ms)
Is waited for (steps S12 and S13 in FIG. 5) and the process proceeds to the next step.

In order to reduce the wait time of the write cycle as compared with this method, it is possible to know the end of the write cycle by reading the last written data and the function of continuously writing data in the EEPROM in page units. This can be realized by using an EEPROM having a function capable of writing and using a writing program as follows.

In the case of byte unit, after writing 1 byte of data (step S21 in FIG. 6), comparison of write data is continued until the data match (step S2 in FIG. 6).
2, 23), and if they match, it is determined whether writing to another page (step S24 in FIG. 6). In this case, the next data can be written after the write cycle ends.

Further, when writing a large amount of data, first, the data for one page is edited (step S3 in FIG. 7).
1) Write the edited data for one page (step S32 in FIG. 7). After that, the last written data is EE
Compare with the read data of PROM (step S3 in FIG. 7).
3) This comparison is continued until they match (step S in FIG. 7).
33, 34). If the comparisons match, it is possible to check the writing to another page (step S35 in FIG. 7) as the end of the write cycle.

[0008]

DISCLOSURE OF THE INVENTION The conventional EEP described above
When the control for the ROM is used in a system using interrupts or multitasks, there is a method of releasing the waiting time of the write cycle of the EEPROM to other tasks or interrupts in order to effectively utilize the CPU.

In the case of this method, EEPRO is used during that period.
Since it is impossible to access M, it is necessary to perform control to avoid contention between writing and reading data in the EEPROM, which results in complicated software.

Further, in order to use the data in the EEPROM surely, a sufficient write cycle during writing is taken,
Data check must be performed, but the longer the time, the more hindrance to other processing.

Further, even if the data in the same page on the EEPROM is accessed from another location on the program, each write cycle interval is secured, so that useless waiting time and useless writing occur. Cause.

In order to solve these problems, in Japanese Unexamined Patent Publication No. 2-81398, a RAM having the same storage capacity as that of the EEPROM is used, and the RAM is accessed in the normal operation state, and selectively as needed. RAM and EEPRO
A method for transferring data to and from M has been proposed.

In this method, the data in the RAM is transferred to the EEPROM when the power is turned off, the data in the EEPROM is transferred to the RAM when the power is turned on, or the RAM and the EEPROM are used.
The data at the same address is read out, and if they do not match, the data in the EEPROM is rewritten according to the data in the RAM to reduce the number of times of rewriting to the EEPROM. The data is rewritten at a high speed by transferring data between the EEPROM and the RAM in units of word lines via the latch circuit.

However, when the power is turned off, the data in the RAM is transferred to the EEPROM, and when the power is turned on, the EEPROM is
In the method of transferring the data to RAM, the data need not be rewritten, so that unnecessary rewriting to the EEPROM occurs.

Further, the data of the same address in the RAM and the EEPROM are read, and if they do not match, the EE
In the method of rewriting the PROM data according to the RAM data, it is not possible to know in which part the rewriting is performed without rewriting unless all the data is read from the RAM and the EEPROM, and all the addresses of the RAM and the EEPROM are read. Since it is necessary to read data from the memory and compare them, the number of man-hours for rewriting the EEPROM becomes large and the processing time for rewriting the EEPROM also becomes long.

Therefore, an object of the present invention is to solve the above-mentioned problems, shorten the writing time of the EEPROM, prevent the writing conflict of the EEPROM, and write the EEPROM without performing unnecessary rewriting and processing of the EEPROM. An object of the present invention is to provide an EEPROM control device capable of preventing leakage and reducing the number of times of writing to the EEPROM.

[0017]

EEPRO according to the present invention
The M control device is an EEPROM control device of an information processing device having an electrically writable and erasable non-volatile memory and a readable and writable storage device including a storage area for storing all contents of the non-volatile memory. A means for replacing the access to the non-volatile memory with an access to the storage area during normal operation, a holding means for holding a write request indicating whether or not writing to the storage area, and a preset predetermined cycle. And a means for writing the content of the storage area corresponding to the write request into the non-volatile memory when the write request is held in the holding means.

Another EEPROM control apparatus according to the present invention has, in addition to the above configuration, means for operating asynchronously with the information processing apparatus and for generating an interrupt to the information processing apparatus at the predetermined intervals. are doing.

In addition to the above configuration, another EEPROM control device according to the present invention operates in the predetermined cycle and checks the data in the nonvolatile memory when the write request is not held in the holding means. It is equipped with means.

[0020]

In the normal operation, the access to the EEPROM is replaced with the access to the pseudo memory and executed, and the write request indicating whether or not the pseudo memory is written is held in the write request flag.

EEP for activating interrupts at regular intervals
If the write request is held in the write request flag when the ROM processing routine is activated, the corresponding data in the EEPROM is updated with the data in the pseudo memory corresponding to the write request.

As a result, the task for accessing the EEPROM and the normal processing routines such as the interrupt routine only access the normal RAM.
Data can be read / written from / to the EEPROM without following the procedure peculiar to the OM, and the time management and memory management burden of software is reduced.

Further, since it is not necessary to wait for the end of data writing to the EEPROM, the CPU occupation time is not lost. Furthermore, since the location of the program for accessing the EEPROM is limited by the presence or absence of the write request in the write request flag or the value of the verify counter, it becomes easy to create the EEPROM management program such as checking the number of writes.

Furthermore, since the EEPROM processing routine operates while avoiding the write cycle interval, there is no risk of duplicate memory access. In this case, the EEPROM
No matter how many times data is rewritten within one page access interval, the EEPROM processing routine only accesses the EEPROM once, so the number of writings to the EEPROM is reduced accordingly.

Therefore, the writing waiting time of the EEPROM is reduced, the writing conflict of the EEPROM is prevented, and the writing conflict of the EEPROM is prevented without performing the unnecessary rewriting and the unnecessary processing of the EEPROM.
It is possible to prevent the writing failure of the EPROM and reduce the number of writing times of the EEPROM.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the EEPROM processing routine 1 operates asynchronously with the tasks 4a to 4d, and operates by interrupting the processing of the tasks 4a to 4d at regular intervals.

When the EEPROM processing routine 1 starts its operation by this interrupt, it checks the write request flag 2b provided in the RAM 2 in advance, and writes the write request flag 2b.
, The pseudo memory 2a provided in the RAM 2 in advance.
Data of the page corresponding to the flag in the EEPROM3
Write to the corresponding page of.

In the EEPROM processing routine 1, if the write request flag 2b is not set, the EEPROM 3
For each page, data check processing (verify check) is performed.

Here, the pseudo memory 2a of the RAM 2 is EE
An area of the same size as the PROM 3 is secured. The write request flag 2b indicates whether or not there is a write request for each page of the EEPROM 3, that is, whether or not there is information indicating whether or not writing to the pseudo memory 2a has been performed. In addition, E to be used at a constant interval to generate an interrupt
A time slightly longer than the write cycle of the EPROM 3 is set.

FIG. 2 shows an EEPRO according to an embodiment of the present invention.
It is a block diagram which shows the microprocessor system using the M control method. In the figure, in this microprocessor system, the CPU 4 has a RAM 2 and an EEPROM 3
And the ROM 5 are connected to each other.

Here, the CPU 4 operates according to a program stored in the ROM 5, and executes the EEPROM processing routine 1 and the tasks 4a to 4d, respectively. C
PU4 is a normal routine that executes tasks 4a-4d
When the data of the EPROM 3 is accessed, all the accesses are replaced with the access to the pseudo memory 2a in the RAM 2 and executed.

FIG. 3 shows the EEPROM processing routine 1 of FIG.
3 is a flowchart showing the processing operation of FIG. These Figure 1
The processing operation of the EEPROM processing routine 1 will be described with reference to FIG.

When the EEPROM processing routine 1 is started, a constant time interrupt is first generated (step S1 in FIG. 3),
After that, the presence / absence of a write request is checked by referring to the write request flag 2b of the RAM 2 (step S2 in FIG. 3).

If there is a write request, the EEPROM processing routine 1 updates the data of the corresponding page of the EEPROM 3 with the data of the pseudo memory 2a of the RAM 2 corresponding to the write request (step S3 in FIG. 3). EEPROM
When the data update to the EEPROM 3 is completed, the processing routine 1 issues the write request of the write request flag 2b to 1
After deleting the page (step S4 in FIG. 3), the process is terminated and the next interrupt start waits.

On the other hand, if there is no write request, the EEPROM processing routine 1 selects a page to be processed by a verify counter (not shown) and verifies the data in the pseudo memory 2a and the EEPROM 3 corresponding to the selected page. Is performed (step S5 in FIG. 3).
6).

If there is data that does not match in this verify check, the EEPROM processing routine 1 uses the data in the pseudo memory 2a corresponding to the selected page to read the EEPROM.
3 is updated (step S7 in FIG. 3), the verify counter is updated (step S8 in FIG. 3), the process is terminated, and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter (step S8 in FIG. 3).
The process is completed and the next interrupt is activated.

FIG. 4 is a timing chart showing the flow of processing in the CPU 4 of FIG. In the figure, the order of priority of processing is the EEPROM processing routine 1, task 4d, task 4c, task 4b, and task 4a.

When tasks 4a to 4d are started while the microprocessor system is powered on and the tasks 4a to 4d are not processed, the EEPROM processing routine 1 first generates a constant time interrupt, and then the RAM 2 The presence / absence of a write request is checked with reference to the write request flag 2b.

In this case, since there is no write request in the EEPROM processing routine 1, the first page is selected as the page to be processed by the verify counter, and the pseudo memory 2 is selected.
A verify check is performed on the first page data of a and the first page data of the EEPROM 3.

If there is data that does not match in the verify check, the EEPROM processing routine 1 issues a write command for updating the first page data of the EEPROM 3 with the first page data of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

Next, during the processing of task 4a, the EEPROM
When the processing routine 1 is activated, the EEPROM processing routine 1 generates a constant time interrupt, and then refers to the write request flag 2b of the RAM 2 to check whether or not there is a write request.

In this case, since the EEPROM processing routine 1 has no write request, the second page is selected as the page to be processed by the verify counter, and the pseudo memory 2 is selected.
A verify check is performed on the second page data of a and the second page data of the EEPROM 3.

If there is data that does not match in the verify check, the EEPROM processing routine 1 issues a write command for updating the second page data of the EEPROM 3 with the second page data of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

During this time, the processing of task 4a is interrupted, and E
When the processing of the EPROM processing routine 1 is completed, the control is returned and restarted. After the restart, when the processing of the task 4b interrupts the processing of the task 4a, the processing of the task 4a is interrupted and the processing of the task 4b is started. During this time, EEPR
In the OM3, when a write command is issued by the data update in the EEPROM processing routine 1, a write cycle by the write command is entered, and tasks 4a,
The write cycle process is performed in parallel with the process of 4b.

When the EEPROM processing routine 1 is started during the processing of the task 4b, the EEPROM processing routine 1
Generates a constant time interrupt, and then refers to the write request flag 2b of the RAM 2 to check the presence / absence of a write request.

In this case, since the EEPROM processing routine 1 has no write request, the third page is selected as the page to be processed by the verify counter, and the pseudo memory 2 is selected.
A verify check is performed on the data on the third page of a and the data on the third page of the EEPROM 3.

If there is data that does not match in this verify check, the EEPROM processing routine 1 issues a write command for updating the third page data of the EEPROM 3 with the third page data of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

The processing of the task 4b interrupted by the processing of the EEPROM processing routine 1 is restarted when the processing of the EEPROM processing routine 1 is completed. This task 4
When the processing of b is completed, the processing of task 4a is restarted. When the processing of the task 4c interrupts the processing of the task 4a after the processing of the task 4a is restarted, the processing of the task 4a is interrupted and the processing of the task 4c is started. During this time, EEP
In the ROM 3, when the write command is issued by the data update in the EEPROM processing routine 1, the write cycle by the write command is started, and the task 4
The write cycle process is performed in parallel with the processes b, 4a, and 4c.

When the EEPROM processing routine 1 is started during the processing of the task 4c, the EEPROM processing routine 1
Generates a constant time interrupt, and then refers to the write request flag 2b of the RAM 2 to check the presence / absence of a write request.

In this case, since the EEPROM processing routine 1 has no write request, the fourth page is selected as the page to be processed by the verify counter, and the pseudo memory 2 is selected.
A verify check is performed between the data on the fourth page of a and the data on the fourth page of the EEPROM 3.

If there is data that does not match in this verify check, the EEPROM processing routine 1 issues a write command for updating the data on the fourth page of the EEPROM 3 with the data on the fourth page of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

The processing of the task 4c interrupted by the processing of the EEPROM processing routine 1 is restarted when the processing of the EEPROM processing routine 1 is completed. This task 4
When data is written to one page of the pseudo memory 2a during the processing of c, a flag is set at a position corresponding to one page of the write request flag 2b. During this time, when a write command is issued by the data update in the EEPROM processing routine 1 in the EEPROM 3, the write cycle by the write command is started, and the write cycle processing is performed in parallel with the processing of the task 4c.

During the processing of the task 4c after the writing of data to one page of the pseudo memory 2a, the EEPR is executed.
When the OM processing routine 1 is started, the EEPROM processing routine 1 generates a constant time interrupt, and then the RAM 2
The presence or absence of a write request is checked with reference to the write request flag 2b of.

At this time, since the EEPROM processing routine 1 has a write request, the data of the first page of the EEPROM 3 is updated with the data of the first page of the pseudo memory 2a corresponding to the write request. When the issuance of the write command for updating the data to the EEPROM 3 is completed, the EEPROM processing routine 1 deletes one page of the write request of the write request flag 2b, then ends the processing and waits for the next interrupt activation.

The processing of the task 4c interrupted by the processing of the EEPROM processing routine 1 is restarted when the processing of the EEPROM processing routine 1 is completed. This task 4
When the processing of task 4d interrupts the processing of c, the processing of task 4c is interrupted and the processing of task 4d is started.

The processing of task 4c is restarted when the processing of task 4d is completed. When the processing of this task 4d is completed, the processing of task 4c is restarted. During this time, EEP
In the ROM 3, when a write command is issued by the data update of the first page in the EEPROM processing routine 1, the write cycle of the write command is entered, and the write cycle processing is performed in parallel with the processing of the tasks 4c and 4d.

When the EEPROM processing routine 1 is started during the processing of the task 4c, the EEPROM processing routine 1
Generates a constant time interrupt, and then refers to the write request flag 2b of the RAM 2 to check the presence / absence of a write request.

In this case, since the EEPROM processing routine 1 has no write request, the fifth page is selected as the page to be processed by the verify counter, and the pseudo memory 2 is selected.
A verify check is performed between the data on the fifth page of a and the data on the fifth page of the EEPROM 3.

If there is data that does not match in the verify check, the EEPROM processing routine 1 issues a write command for updating the fifth page data of the EEPROM 3 with the fifth page data of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

The processing of the task 4c interrupted by the processing of the EEPROM processing routine 1 is restarted when the processing of the EEPROM processing routine 1 is completed. This task 4
When the processing of c is completed, the processing of task 4a is restarted. During this period, when a write command is issued in the EEPROM 3 by the data update in the EEPROM processing routine 1, the write cycle of the write command is entered, and the write cycle processing is performed in parallel with the processing of the tasks 4c and 4a.

When the EEPROM processing routine 1 is started during the processing of the task 4a after the processing of the task 4a is restarted,
The EEPROM processing routine 1 generates a constant time interrupt,
After that, the presence / absence of a write request is checked by referring to the write request flag 2b of the RAM2.

In this case, since the EEPROM processing routine 1 has no write request, the sixth page is selected as the page to be processed by the verify counter and the pseudo memory 2 is selected.
A verify check is performed on the data on the fourth page of a and the data on the sixth page of the EEPROM 3.

If there is data that does not match in this verify check, the EEPROM processing routine 1 issues a write command for updating the data on the 6th page of the EEPROM 3 with the data on the 4th page of the pseudo memory 2a,
After updating the verify counter, the processing is terminated and the next interrupt activation waits.

If all the data match in this verify check, the EEPROM processing routine 1 updates the verify counter, then ends the processing, and waits for the next interrupt activation.

As described above, in the normal operation, the EEPROM 3
Access to the pseudo memory 2a is executed and the write request indicating whether or not the pseudo memory 2a is written is held in the write request flag 2b. If the write request is held in the write request flag 2b when the EEPROM processing routine 1 for activating the interrupt is activated, the data in the pseudo memory 2a corresponding to the write request is EE.
By updating the corresponding data in PROM3,
An ordinary RA is used for normal processing routines such as tasks 4a to 4d for accessing the EEPROM 3 and interrupt routines.
Since only M2 is accessed, it is possible to read / write data from / to the EEPROM 3 without following the procedure peculiar to the EEPROM 3, and the load of time management and memory management by software is reduced.

Further, since it is not necessary to wait for the end of data writing to the EEPROM 3, the loss of the CPU occupation time is eliminated accordingly. Further, since the location of the program for accessing the EEPROM 3 is limited by the presence / absence of a write request in the write request flag 2b or the value of the verify counter, the number of times of writing is checked, etc.
The ROM management program can be easily created.

Furthermore, the EEPROM processing routine 1
Since it operates while avoiding the write cycle interval, there is no risk of duplicate memory access. In this case, EEPRO
No matter how many times the data is rewritten within the access interval for one page of M3, the EEPROM processing routine 1 accesses the EEPROM 3 for the page only once, so that the number of times of writing to the EEPROM 3 can be reduced accordingly. .

Therefore, the writing waiting time of the EEPROM 3 is shortened, the writing conflict of the EEPROM 3 is prevented, the writing omission of the EEPROM 3 is prevented, and the writing of the EEPROM 3 is prevented without performing unnecessary rewriting or wasteful processing of the EEPROM 3.
It is possible to reduce the number of writing times of 3.

[0076]

As described above, according to the present invention, it is possible to access a non-volatile memory that is electrically writable and erasable during normal operation and to access a storage area that stores all the contents of the non-volatile memory. If a write request is held when the presence or absence of a write request is checked at a preset predetermined cycle, then the write request is held By writing the contents of the storage area corresponding to the above into the non-volatile memory, the writing waiting time of the EEPROM is shortened, the writing conflict of the EEPROM is prevented, and the writing failure of the EEPROM is prevented without performing unnecessary rewriting or wasteful processing of the EEPROM. And the number of writings to the EEPROM can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a microprocessor system using an EEPROM control method according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a processing operation of an EEPROM processing routine of FIG.

FIG. 4 is a timing chart showing a processing flow in the CPU of FIG.

FIG. 5 is a flowchart showing a control operation of an EEPROM according to a conventional example.

FIG. 6 is a flowchart showing a control operation of an EEPROM according to a conventional example.

FIG. 7 is a flowchart showing a control operation of an EEPROM according to a conventional example.

[Explanation of symbols]

 1 EEPROM processing routine 2 RAM 2a Pseudo memory 2b Write request flag 3 EEPROM 4a to 4d Task

Claims (3)

[Claims] 1. An EEPROM control device for an information processing apparatus having an electrically writable and erasable nonvolatile memory and a readable and writable storage device including a storage area for storing all contents of the nonvolatile memory. A means for replacing the access to the non-volatile memory with an access to the storage area during normal operation, a holding means for holding a write request indicating whether or not writing to the storage area, and a preset predetermined cycle. And a means for writing the content of the storage area corresponding to the write request into the non-volatile memory when the write operation is held in the holding means. 2. The E according to claim 1, further comprising means that operates asynchronously with the information processing apparatus and that generates an interrupt to the information processing apparatus at the predetermined intervals.
EPROM controller. 3. The method according to claim 1, further comprising means for performing a data check of the non-volatile memory when operating in the predetermined cycle and when the write request is not held in the holding means. The described EEPROM control device.