JPH08129440A - Image forming device - Google Patents

Abstract

PURPOSE: To decrease the number of harness and I/O ports by simultaneously processing the serial signal that is sent to a control panel by a transmission means and the serial signal that is converted by an input conversion means. CONSTITUTION: When a CPU sends the transfer data to an internal bus 1 to start the transfer of data, an LD 3 is generated by a control signal generation part, the transfer data are sent to a shift register 4, and the internal state of the shift register 4 becomes a state where transfer data are loaded. Thereafter, 8 shots of SCK 2 are generated by a clock generation part, and the trailing edges of these SCK 2 are synchronized with each other and the register 4 shifts the data, and the data emerge at a TXD via D flip-flop 5. At the same time, the state of an RXD is shifted in a shift register 6 synchronously with the starting of the SCK 2. Thus the received data are available in the register 6 when 8 shots of SCK 2 are finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation panel of an image forming apparatus using a serial communication system.

[0002]

2. Description of the Related Art With the multi-functionalization of image forming apparatuses, the number of display units and input keys on the operation panel is gradually increasing, and the harness connecting the operation panel and the control unit of the image forming apparatus is also increasing at the same time. Therefore, in order to reduce the number of harnesses and the number of ports required for display and input, time-division drive for display and time-division sensing for key input are generally performed. There are also high-class image forming apparatuses in which the operation panel itself has a CPU for displaying and key input, and a serial communication method is used for communication with the control unit.

However, in order to pursue a low cost, there has been devised a structure capable of reducing the harness without a dedicated CPU. In such a case, the conventional I / F
Uses time-division drive for display and time-division input for key input. In this case, three types of signal lines are required: a) display signal line, b) time division drive line, and c) input line. For example, assuming an operation panel with 80 LED displays and 40 keys, a total of 23 signal lines are required, 10 for display signal lines, 8 for time division drive lines, and 5 for input lines. (In case of 8 × 10 display matrix and 8 × 5 key matrix). Furthermore, as the number of I / O ports,
23 ports of the output port 18 and the input port 5 are required (if the 3TO8 decoder is used for the time division drive signal, the output port will be 13).

Further, in a model having a more advanced structure, a serial transfer system is adopted for an output signal. According to this, the display signal and the time-division drive signal are converted into serial data and sent out, and converted again into parallel signals on the operation panel. On the other hand, the input signals are processed as parallel signals. In this case, assuming the operation panel described above, one serial data line, one serial clock line,
A total of eight signal lines, one data strobe line and five input signal lines, will suffice. However, a serial-parallel conversion element is required for the operation panel, and a power supply and a ground line are also required for this element. In addition to the serial port, the number of ports will be 6 ports including the output port 1 and the input port 5 for the data strobe.

[0005]

Generally, since a serial communication function of a type which is built in a CPU and which transmits and receives data in synchronization with a serial clock is a half-duplex function, input / output is simple. Data cannot be transferred at the same time.

Therefore, a first object of the present invention is to provide an image forming apparatus having a structure in which input and output can be transferred at the same time, both output and input are serial signals, and are transferred at the same time, and the number of harnesses and I / O ports is further reduced. Is to provide. A second object of the present invention is to provide an image forming apparatus in which the number of harnesses and the number of ports are further reduced by making the data strobe lines, which are originally required for input and output, common. Further, a third object of the present invention is to transfer the same data a plurality of times by utilizing the difference between the data length of serial output data and the data length of serial input data.
An object of the present invention is to provide an image forming apparatus that reduces data errors due to the influence of noise and the like.

[0007]

According to a first aspect of the present invention, an image forming apparatus sends an operation panel, time-division drive data for time-division driving display data and display to the operation panel as a serial signal. And a conversion means for converting these signals into parallel signals when performing time-division driving of the display on the operation panel, and an input conversion means for converting operation input signals input in time-division into serial signals. The first object is achieved by simultaneously processing the serial signal sent from the sending means and the serial signal converted by the input converting means. According to a second aspect of the present invention, the image forming apparatus according to the first aspect converts the data strobe signal for converting the serial signal into the parallel signal by the converting means and the operation input signal into the serial signal by the input converting means. The second object is achieved by performing data transfer by using the data strobe signal for performing the data transfer as a common signal.

According to a third aspect of the invention, in the image forming apparatus according to the second aspect, the output of the serial signal converted by the input converting means is connected to the terminal for inputting the serial signal of the input converting means, The third object is achieved by transferring the same data a plurality of times by utilizing the difference between the signal length of the serial signal sent to the operation panel by the sending means and the signal length of the serial signal input from the operation panel. To do.

[0009]

According to the present invention, the serial signal sent from the sending means to the operation panel and the serial signal converted by the input converting means are processed simultaneously. According to the second aspect of the present invention, the data strobe signal for converting the serial signal into the parallel signal by the converting means and the data strobe signal for converting the operation input signal into the serial signal by the input converting means are used as common signals. Transfer. According to the third aspect of the invention, the output of the serial signal converted by the input converting means is connected to the terminal for inputting the serial signal of the input converting means converting means, and the serial signal transmitted by the transmitting means to the operation panel is transmitted. By using the difference between the signal length and the signal length of the serial signal input from the operation panel, the same data is transferred a plurality of times to reduce data errors due to the influence of noise and the like.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the image forming apparatus of the present invention is shown in FIG.
It will be described in detail with reference to FIGS. FIG. 1 is a block diagram showing the CPU (central processing unit) of the control circuit of the image forming apparatus.
3 illustrates a basic configuration of a portion related to the present embodiment.
Reference numeral 1 is an internal data bus of this CPU. The CPU transfers data to and from each of the internal functional blocks through this data bus. Reference numeral 2 denotes an SCK serial transfer clock, which is eight clock signals generated by a clock generation unit (not shown) in response to a transfer start command. It is output to the outside and becomes the reference clock for data transfer. Reference numeral 3 is a signal for transferring the transfer data from the LD internal data bus to the shift register 4 and is generated prior to the generation of the serial transfer clock by the transfer start command, and the transfer data is loaded into the shift register by this signal. It

Reference numeral 4 is an 8-bit parallel-in / serial-out type shift register, which shifts the data loaded by the LD3 at the falling edge of SCK2 and outputs the most significant bit MSB from Q. Reference numeral 5 is a D flip-flop, which takes in the D input at the falling edge of SCK2 and outputs the internal state from Q. This output is output to the outside as a serial signal output TXD.

Reference numeral 6 is an 8-bit serial-in / parallel-out type shift register, which shifts in the D input at the rising edge of SCK2 and converts it into a parallel signal. RD7 is generated in response to a data read command from the CPU, and a parallel signal is output to the internal data bus. This D
The input is externally input as a serial signal input RXD. Further, although not shown, it also has a function of generating an interrupt at the end of 8-bit data transfer, and the CPU causes the CPU to read the input data and load the next transfer data.

Similarly, although not shown, a flag register is provided to determine whether or not data is being transferred. In this embodiment, the transfer is started by loading the transfer data, but by providing a register between the internal data bus 1 and the shift register 4, the transfer data loading and the transfer start are separated. It can also be configured to perform. Further, by providing a register between the shift register 6 and the internal data bus 1, it is possible to read the received data even during the transfer.

FIG. 2 is a time chart showing the operation of FIG. When the CPU sends the transfer data to the internal data bus 1 to start the data transfer, the control signal generating unit (not shown) generates LD3, the transfer data is transferred to the shift register 4, and the internal state of the shift register 4 is the transfer data. Will be loaded. After that, 8 shots of S
CK2 is generated by a clock generator (not shown), the shift register 4 shifts the data in synchronization with the falling edge, and the data appears in TXD via the D flip-flop 5. Simultaneously with this operation, the state of RXD is shifted into the shift register 6 in synchronization with the rising edge of SCK2, and when the eight SCK2's are completed, the received data is arranged inside the shift register 6. .

FIG. 3 is an excerpted portion of the circuit of the operation panel, which is relevant to this embodiment. 10, 11
Is an 8-bit serial-in / parallel-out type shift register, which shifts in the D input at the rising edge of SCK2 and converts it into a parallel signal. T in FIG.
XD is connected to this terminal RXD, and the display data and time-division drive data transferred as a serial signal are converted into a parallel signal. The Q input of 10 is connected to the D input of 11, and 10 and 11 function as a shift register of 16-bit length. Reference numerals 12 and 13 are 8-bit D flip-flops, which are set to 1 by the STB1 signal.
Latch the outputs of 0 and 11. The D flip-flops 12 and 13 prevent display data and time-division drive data from changing during data transfer.

Reference numeral 14 is a transistor for selectively supplying power to the drive line for time-division drive. The transistors connected to Q0 to Q7 of the D flip-flop 12 are turned on one by one in a time-sharing manner, and the LED 15 connected to the time-division line to which power is supplied is selectively selected by the output data of the D flip-flop 13. Drive to. In this driving method, N × time division lines and M display data lines are used, and M ×
N LEDs can be driven. Reference numeral 16 is an 8-bit parallel-in / serial-out type shift register,
The data loaded by TB2 is shifted at the falling edge of SCK2, and the most significant bit MSB is output from Q.

Reference numeral 17 denotes a D flip-flop, which is SC
The D input is taken in at the falling edge of K2, and the internal state is output from Q. This output is the serial signal output TXD
To the outside. This TXD is connected to the RXD of FIG. 1 to transmit key input data on the operation panel. 18 is
A key switch connected to the sensor matrix. When the key information is loaded by the STB 2 at a specific timing, only the information of the key switch connected to the drive line supplied with power at that timing is loaded. With this sensing method, M × M key switches can be sensed for N time divisions and M input lines. Note that STB1 and STB2
Is not shown in FIG. 1, but is the output signal from the output port.

FIG. 4 is a time chart showing the operation of FIG. Prior to the output of new time-division data, key input is performed using the current time-division data, so STB2 is output and the current state is loaded into the shift register 16. After that, when data transfer is started, data is output to RXD in synchronization with the fall of SCK2. This is SC
At the rising edge of K2, it is shifted into the shift registers 10 and 11, STB1 is output when the transfer of 2 times (16 bits) is completed, and latched in the D flip-flops 12 and 13. As a result, the time division data and the display data are updated. At the same time as this transfer, the key input data loaded by the STB2 from the shift register 16 and the D flip-flop 17 is shifted out and transferred in synchronization with the fall of SCK2. At this time, the output data length is 16 bits, whereas the input data length is 8 bits, so invalid data will appear in TXD during the second transfer. Therefore, the CPU reads the key data at the end of the first transfer and before the start of the second transfer, and the key data at the end of the second transfer is invalid and must be discarded.

In the first embodiment, the CPU of the control circuit of the image forming apparatus sends display data and time-division driving data for time-division driving the display as serial signals to the operation panel, while the operation panel displays , These signals are converted into parallel signals for time-division driving of display, the operation input signals input in time-division are converted into serial signals, and at the same time when the serial signals are sent, the image forming apparatus is controlled from the operation panel. Since it is input to the CPU of the circuit, it is possible to reduce the number of harnesses and I / O ports.

Next, a second embodiment will be described. As described above, when data is transferred at the same time as input and output by using time-division driving and time-division sensing, first, input data is loaded into the shift register 16, this data is transferred to the CPU, and new time-division driving data Since it is necessary to transfer the display data to the operation panel and then latch the data in the D flip-flops 12 and 13 to update the time-division drive data and the display data, 2
Two strobe signals STB1 and STB2 are required.
However, since SCK2 is not output until the next STB2 is output after STB1 is output, the shift register 1
The states of 0 and 11 have changed. Therefore, even if STB1 is output at the timing of STB2, the D flip-flop 1
The states of 2 and 13 do not change. STB1 using this
And STB2 are the same signal. This operation is shown in the configuration by the one-dot chain line X in FIG. 3 and the time chart in FIG. In the second embodiment, the data strobe lines, which should originally be required for the input and the output, can be shared, and the number of harnesses and the number of ports can be further reduced as compared with the first embodiment.

Next, a third embodiment will be described. When the output data length is 16 bits and the input data length is 8 bits as shown in FIG. 3, the transfer of two times becomes one cycle, but as described above, the transfer data of the second time becomes invalid. I will end up. Therefore, when the Q output of the shift register 16 is connected to the serial input terminal SER of this element as shown by the dotted line Y in FIG. 3, the Q output is shifted into the shift register 16 again by SCK2, and when one transfer is completed, the shift is completed. The internal state of register 16 is
It has returned to the state before the transfer started. Therefore, the same input data as in the first transfer is also transferred in the second transfer. Therefore, the same data can be transferred twice in one transfer operation. This can be used to increase the security of data.

Further, when data is erroneous due to disturbance such as noise, there is a high probability that the data will not match twice. Therefore, if the data of the first time and the data of the second time are compared and they do not match, by making this invalid data, the probability of preventing an error increases. Shift register 16 of the time chart of FIG.
The internal state and the TXD term show how the same data is transferred by this connection.

[0023]

According to the first aspect of the invention, since the serial signal sent from the sending means of the image forming apparatus and the serial signal converted by the input converting means are processed simultaneously,
The configuration of the image forming apparatus can be simplified. For example, the number of harnesses and I / O ports of the image forming apparatus can be reduced. According to the second aspect of the invention, the data strobe line, which should be originally required for the input and the output, can be shared by the image forming apparatus, and the number of harnesses and the number of ports can be further reduced as compared with the invention of the first aspect. According to the third aspect of the invention, the difference between the data length of the serial output data and the data length of the serial input data is used to transfer the same data a plurality of times, thereby reducing data errors due to the influence of noise or the like. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a portion of a CPU (central processing unit) of a control circuit of an image forming apparatus, which is related to the present embodiment.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a diagram showing an excerpt of a portion of a circuit of an operation panel, which is relevant to the present embodiment.

FIG. 4 is a time chart showing the operation of FIG.

FIG. 5 is a time chart showing the operation of the second and third embodiments.

[Description of Reference Signs] 1 data bus 2 serial transfer clock 4 shift register 5 D flip-flop 6 shift register 10 shift register 11 shift register 12 D flip-flop 13 D flip-flop 14 transistor 16 shift register 17 D flip-flop 18 key switch

Claims (3)

[Claims] 1. An operation panel, sending means for sending display data and time-division driving data for time-division driving the display as a serial signal to the operation panel, and time-division driving of display by the operation panel. At this time, it comprises a conversion means for converting these signals into a parallel signal and an input conversion means for converting an operation input signal input in time division into a serial signal, and the serial signal transmitted from the transmission means and the input signal An image forming apparatus, wherein the serial signals converted by the converting means are simultaneously processed. 2. A data strobe signal for converting a serial signal into a parallel signal by the converting means and a data strobe signal for converting an operation input signal into a serial signal by the input converting means are transferred as a common signal. The image forming apparatus according to claim 1, wherein: 3. The output of the serial signal converted by the input conversion means is connected to a terminal for inputting the serial signal of the input conversion means, and the signal length of the serial signal sent to the operation panel by the sending means and 3. The image forming apparatus according to claim 2, wherein the same data is transferred a plurality of times by utilizing a difference in signal length of serial signals input from the operation panel.