JP2000324896A - Data transmission system and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a plurality of pulse motors having the same characteristics simultaneously operable, and to decrease bundled wires by causing a serial communication controlling means which transmits and receives data to have data registers and a phase data generating means, connecting them to a plurality of child communication means, and transferring phase data to the data registers. SOLUTION: A control unit controls serial communication between the control unit and a load unit. A communication controller 601 has a serial communication part 630, a phase data generating part 639, etc. The communication part 630 is provided with data registers, etc. The load unit has a plurality of child communication ICs 602, and to the ICs 602, etc., a plurality of pulse motors 605, etc., are connected. The data registers are caused to make one-to-one correspondence to the addresses of the child communication ICs. The motors 605, etc., are operated in the following way. A host CPU 600 makes phase data of the pulse motors transferable to the data registers, and transmits phase data to the IC 602, when the phase data is generated. The phase data is outputted from the IC 602, and operation of the motor 605 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly, to serially transmitting phase data of a pulse motor used in an image forming apparatus to a plurality of slave communication means at the same time to simultaneously control the pulse motor. The present invention relates to a data transmission system and an image forming apparatus using the same.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration example of a conventional serial communication system. The serial communication system of FIG.
A communication controller 101; a child communication IC 102 to which a motor driver 105 for driving a motor 104 is connected;
The slave communication IC 103 to which the plurality of sensors 106 are connected is cascade-connected via a set of two signal lines including a synchronous clock (CLK) line and a data (DATA) line for serial communication. I have.

In the example shown in FIG. 1, up to eight child communication ICs can be cascaded for one communication controller.
Each child communication IC can specify a unique address (address 0, address 1,...). Here, two child communication ICs 102 and 103 are connected. Eight data registers 0 to 7 are provided in the communication controller 101. These data registers 0 to 7 correspond to addresses (addresses 0 to 7) unique to the child communication IC, and the communication is selected by the serial communication control unit.

Then, such a communication controller 10
1 performs transmission or reception communication with a communication IC corresponding to each data register. At the time of transmission, data is transmitted via the transmission buffer 132 and the shift register 133, and at the time of reception, data is received via the shift register 135 and the reception buffer 134.

FIG. 2 is a block diagram showing a case where the serial communication system shown in FIG. 1 is incorporated in an image forming apparatus 1 such as a copying machine.

In FIG. 2, a host CPU 200 and a communication controller 201 are bus-connected by an address bus, a data bus, and a control signal, and the communication controller 201 and a motor driver 208 for driving a motor 206 disposed at an appropriate position in the apparatus. The connected child communication IC 202 and each driver 20 for driving a plurality of solenoids 207
9 and a plurality of sensors 2 connected thereto.
The slave communication IC 204 to which the plurality of sensors 211 are connected is connected to the slave communication IC 204 to which the plurality of sensors 211 are connected via a set of signal lines. These communication controllers 20 are transmitted by a transmission command or a reception command from the host CPU 200.
1 and each of the child communication ICs 102 to 105 perform data communication.

A unique address (address 0, address 1, address 2,...) Is determined for each slave communication IC irrespective of the location of the slave communication ICs 202 to 205 in the apparatus. Reference numeral 201 designates an address in a communication frame (pulse train) to perform transmission / reception communication with the child communication IC having the corresponding address.

An outline of the operation of the serial communication system will be described. When performing a transmission operation of transmitting predetermined data to operate the solenoid 207, the host CP
U200 sets a transmission flag for performing transmission in communication controller 201 (not shown), and writes transmission data to data register 1. When the transmission data is written, the communication controller 201 sends a pulse train of a predetermined frequency to the CLK line. In synchronization with the pulse train, the communication controller 201 and the slave communication IC 203
Data transmission processing in the data register 1 is performed by the transmission data protocol shown in FIG.

In FIG. 3, first, the communication controller 2
01 sends a start bit indicating the start of communication,
Bits to specify transmission or reception communication sequentially from the next,
The address bit string, transmission data bit string, and parity bit of the desired slave communication IC are transmitted. The slave communication IC recognizes the start bit at the first rising edge of CLK, and the next C
Recognizes transmission or reception communication at the rise of LK, then fetches transmission data and parity bit only when the transmitted address bit string matches its own address, and checks parity bit from transmission data and parity bit And the resulting ACK
(Acknowledge) to the communication controller 201. The communication controller 201 reads ACK at the rising edge of CLK, sends a stop bit indicating the end of communication to the child communication IC only when the ACK is normal, and ends the transmission operation. If the ACK is abnormal, the transmission operation is terminated without transmitting a stop bit. The slave communication IC determines whether or not the data transmitted by the stop bit is determined (output). Communication is performed with the slave communication IC 203 in the above sequence to drive the solenoid 207.

Next, a receiving operation for reading the value of the sensor 210 connected to the slave communication IC 204 will be described. When performing a reception operation, the host CPU 200 sets a reception flag for performing reception in the communication controller 201 (not shown). When the reception flag is set, the communication controller 201 sends a pulse train of a predetermined frequency to the CLK line. In synchronization with the pulse train, the communication controller 201 and the slave communication IC 204 perform reception processing according to the reception protocol shown in FIG.

In FIG. 4, first, the communication controller 2
01 sends a start bit indicating the start of communication,
Bits to specify transmission or reception communication sequentially from the next,
The address bit string of the desired slave communication IC is transmitted. The slave communication IC sends the transmission data and the parity bit to the communication controller 201 only when the sent address bit string matches its own address. The communication controller 201 checks the parity from the received data and the parity bit, and if the result is normal, determines the received data and terminates the receiving and transmitting operation. If the parities do not match, the data is invalidated. Communication is performed with the child communication IC 204 in the above sequence, and the value of the sensor 210 is read.

With such a system configuration, it is possible to operate a load group such as a large number of motors, solenoids, sensors, etc., disposed at various places in the entire apparatus by using two cascade-connected signal lines and to read information. Can be done. In this example, the data of one address is 8 bits,
The configuration for exchanging the information for the address between the communication controller and the child communication IC has been described. However, they can be changed to an appropriately optimized configuration by deciding the communication data format. Further, by providing a plurality of communication controller functions, it is possible to increase the number of child communication ICs to be handled by increasing the number of signal lines correspondingly.

Conventionally, when a plurality of identical pulse motors are operated, a configuration as shown in FIG. 5 is employed. When operating the pulse motors 505 to 507, the host CP
The phase data is output from the port of U500. The phase data is input to the motor drivers 508 to 510 via the buffers 502 to 504, respectively, to operate the motor.
At this time, an enable signal for selecting whether or not to output data from the buffers 502 to 504 is transmitted to the host CP.
By inputting from the port of U500 to the gates of the buffers 502 to 504, the operations of the motors 505 to 507 can be turned on / off.

[0014]

However, in the configuration shown in FIG. 5, in order to operate a plurality of identical pulse motors arranged in close proximity to each other, it is necessary to extend the bundle to each pulse motor separately. No. In addition, since a large current capacity is required, a thick bundle is required.

Therefore, an object of the present invention is to reduce the number of bundles by handling the phase data of the pulse motors by serial communication when operating a plurality of pulse motors having the same characteristics, and to reduce the number of bundles to the motor. An object of the present invention is to provide a data transmission system capable of forming an efficient image forming apparatus by shortening the same and an image forming apparatus using the same.

[0016]

In order to achieve the above object, the invention according to claim 1 controls serial communication for transmitting and receiving predetermined serial data in a time series on one communication line. Communication control means for performing communication, and a plurality of child communication means connected to the communication control means for transmitting and receiving the data to and from the communication control means, wherein the communication control means comprises: A data register for storing communication data corresponding to the one-to-one correspondence, phase data generating means for generating phase data for driving a pulse motor, and phase data generated by the phase data generating means. A first select register in which information about which data register to transfer to the data register is set, and the plurality of data based on the first select register. Phase data transfer means for transferring to a register, transferring the phase data to a plurality of data registers by the phase data transfer means, connecting to predetermined child communication means and serially transmitting the phase data, The plurality of pulse motors are driven by the same control by outputting the phase data from the slave communication means.

According to a second aspect of the present invention, the phase data generation means includes a phase data storage means for storing the phase data, and a time for performing speed control of acceleration / constant speed / deceleration of the pulse motor. And timer means for transferring the phase data of the phase data storage means to the plurality of data registers based on the first select register when the timer means detects that a predetermined timer time has elapsed. It is characterized by doing.

According to a third aspect of the present invention, the transfer information set in the first select register is determined in accordance with the number of the child communication means and a load condition connected to the child communication means. It is characterized by that.

According to a fourth aspect of the present invention, there is provided an image forming apparatus for controlling image formation in an image forming unit by a plurality of control units, wherein the data transmission system according to any one of the first to third aspects is provided. Incorporating the child communication unit of the data transmission system into the image forming unit,
The communication control means of the data transmission system is incorporated in the control unit, and the plurality of pulse motors are made the same by serially transmitting phase data for controlling the pulse motors from the communication control means to the plurality of slave communication means. It is characterized by being driven by control.

According to a fifth aspect of the present invention, there is provided a communication control means for controlling serial communication for transmitting and receiving predetermined serial data in a time series on one communication line, and the communication control means, A plurality of child communication means for transmitting and receiving the data to and from the control means, the communication control means, a data register for storing communication data corresponding to the plurality of child communication means one-to-one And phase data generating means for generating phase data for driving the pulse motor, and information on which data register of the plurality of data registers the phase data generated by the phase data generating means is set. A first select register; phase data transfer means for transferring the phase data to the plurality of data registers based on the first select register; A plurality of communication input / output means connected between the control means and the plurality of child communication means, and a communication selection means provided in the communication control means, for selecting the plurality of communication input / output means in a time-division manner, Transferring the phase data to a plurality of data registers by the phase data transfer means,
By selecting the plurality of communication input / output units in a time division manner by the communication selection unit, the communication unit is connected to a predetermined slave communication unit to serially transmit the phase data and output the phase data from the plurality of slave communication units. Thus, a plurality of pulse motors are driven by the same control.

According to a sixth aspect of the present invention, the phase data generating means has phase data storing means for storing the phase data, and timer means for controlling speed of the pulse motor such as acceleration / constant speed / deceleration. When the timer detects that a predetermined timer time has elapsed, the phase data is converted to the first data.
The data is transferred to the plurality of data registers based on the select register.

According to a seventh aspect of the present invention, the transfer information set in the first select register is determined according to the number of the child communication means and a load state connected to the child communication means. It is characterized by that.

In the invention described in claim 8, the communication selecting means is configured to set connection information indicating to which communication input / output means the plurality of child communication means corresponding to the data register are connected. Is provided.

According to a ninth aspect of the present invention, the connection information set in the second select register is determined according to the number of the child communication means and / or a load condition connected to the child communication means. It is characterized by being determined.

According to a tenth aspect of the present invention, in the plurality of communication input / output means, only the communication input / output means selected by the communication input / output means inputs / outputs a synchronous clock and a communication pulse train. Features.

According to an eleventh aspect of the present invention, there is provided an image forming apparatus for controlling image formation in an image forming unit by a plurality of control units, and the data transmission system according to any one of the fifth to tenth aspects. Incorporating the child communication unit of the data transmission system into the image forming unit, incorporating the communication control unit of the data transmission system into the control unit, and providing the communication between the communication control unit and the child communication unit. Connected by a plurality of communication input / output means, the communication control means selects the plurality of communication input / output means in a time-division manner, and serially transmits phase data for controlling the pulse motors so that the plurality of pulse motors can It is characterized by being driven by control.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, an example will be described in which the same phase data is transmitted to three slave communication ICs to simultaneously drive three pulse motors.

FIG. 6 shows a schematic configuration of a serial communication system according to the present invention.

The serial communication system can be configured as an electrophotographic image forming apparatus such as a copying machine. Hereinafter, in this example, an example in which the image forming apparatus is configured as an image forming apparatus will be described.

The control unit and the load unit are
It is built into the image forming apparatus. The control unit is configured as a control unit of the apparatus main body, and controls serial communication with the load unit. The load units include a child communication IC 602 (address 0), a child communication IC 603 (address 1), and a child communication IC 6 as child communication means.
04 (address 2),...

The child communication ICs 602 to 604 are connected to motor drivers 608 to 610 for driving pulse motors 605 to 607 arranged at appropriate positions in the apparatus.

Between the control unit including the communication controller 601 and the load units including the slave communication ICs 602 to 604, one set of communication lines CLK and DAT
A and + 5V, GND, + 24V, P
They are connected by GND.

Here, the internal configuration of the control unit according to the present invention will be described. A host CPU 60 that controls the image forming apparatus is provided in the control unit.
0 and a communication controller 601 as communication control means for controlling serial communication for transmitting or receiving predetermined data in a time series on a data line (DATA). The host CPU 600 includes a communication controller 6
01, and exchanges communication commands and data with the communication controller 601.

The communication controller 601 includes a serial communication section 630, a transfer section 640, and a phase data generation section 63.
9.

The serial communication unit 630 includes data registers 0 to 7 and a serial communication control unit 631 as shown in FIG.
, A transmission buffer 632, a shift register 633, a reception buffer 634, and a shift register 635. The data registers 0 to 7 are configured to correspond one-to-one with addresses 0 to 7 of the child communication IC.

The transfer section 640 has a transfer register 641 shown in FIG. In this transfer register 641, information on transfer information as to which data register to transfer the phase data of the pulse motor generated in the phase data generator 639 is set. The information set in the transfer register 641 is determined by the number of slave communication ICs and the number of pulse motors connected to the slave communication IC, and is programmed in advance in the host CPU 600. Is set by

FIG. 8 shows the configuration of the transfer register 641 in the communication controller 601. For example, assume that the transfer register 641 in FIG. 8 is set to “00000111”. As a result, the phase data of the pulse motor generated in the phase data generator 639 is stored in the data register 0,
The data is sequentially transferred to the data register 1 and the data register 2. When the phase data is transferred to each data register, the phase data is sequentially transmitted to each child communication IC,
Each pulse motor operates by outputting the phase data from the slave communication IC.

When the transfer register 641 is set to "00000011" while the phase data generator 639 is operating, the transfer of the phase data to the data register 2 is stopped. As a result, the operation of the pulse motor connected to the slave communication IC 604 (address 2) is also stopped.

Next, the operation of the communication controller 601 for operating the pulse motors 605 to 607 will be described.

First, the host CPU 600 sets a transmission flag in the communication controller 601 to enable transmission. Next, the host CPU 600 sets the transfer register 641 to “00000111” so that the phase data of the pulse motor generated in the phase data generation unit 639 can be transferred to the data registers 0 to 2. Next, the host CPU 600
9 to enable the phase data generator 6
39 is operated.

When the phase data generator 639 starts operation, it measures time by a timer for controlling the speed of acceleration / constant speed / deceleration of the pulse motor, and drives the pulse motor every predetermined timer time. Generate phase data. When the phase data is generated, the transfer unit 640 sequentially transfers the phase data to the data register 0, the data register 1, and the data register 2 according to the information of the transfer register 641.

When the phase data is set in the data register 0, the serial communication control section 631 transfers the data in the data register 0 to the shift register 633 via the transmission buffer 632, and applies a clock (CL) to the communication line.
K) and a pulse train. The phase data is transmitted to the slave communication IC 602 by communicating with the slave communication IC 602 in synchronization with the clock output. As a result, the phase data is output from the slave communication IC 602, and the motor driver 608 controls the driving of the motor 605 based on the phase data.

When the communication to the child communication IC 602 is completed,
The serial communication control unit 631 transmits data of the data register 1 in which phase data is set in advance to the transmission buffer 63.
The clock (CLK) and the pulse train are transmitted to the shift register 633 via the communication line 2 and transmitted to the communication line.
By communicating with the slave communication IC 603 in synchronization with the clock output, the phase data is similarly output from the slave communication IC 603, and the motor driver 60 is controlled based on the phase data.
9 controls the driving of the motor 606. Similarly, child communication IC
When the communication with the slave communication IC 603 is completed, the phase data is output from the slave communication IC 604 by communicating with the slave communication IC 604, and the motor driver 61
0 controls the drive of the motor 607.

As described above, the transfer section 640 transfers the phase data for driving the pulse motor to the data registers 0 to 7 based on the information of the transfer register 641, and the child communication IC corresponding to the data registers 0 to 7 By communicating with a plurality of slave communication ICs,
The same pulse motor having a plurality of characteristics can be driven at the same time.

While the phase data generator 639 is operating,
Whether phase data is transferred to each of data registers 0 to 7 by setting transfer register 641 /
It is also possible to select whether or not to perform the driving and to select whether or not to drive each of the plurality of pulse motors.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, phase data is transmitted to one child communication IC,
An example in which three pulse motors are driven simultaneously will be described.

FIG. 9 shows a schematic configuration of a serial communication system according to the present invention.

The present serial communication system can be configured as an electrophotographic image forming apparatus such as a copying machine. Hereinafter, in this example, an example in which the image forming apparatus is configured as an image forming apparatus will be described.

The control unit and the load unit are
It is built into the image forming apparatus. The control unit is configured as a control unit of the apparatus main body, and controls serial communication with the load unit. The load unit is provided with a slave communication IC 902 (address 0),... As slave communication means.

The child communication IC 902 includes buffers 903 to
905 are connected. Buffers 903 to 905 have pulse motors 906 to 906 disposed at appropriate positions in the apparatus, respectively.
Motor drivers 909 to 911 for driving the motor 908 are connected.

The output of the slave communication IC 902 is EN0 for enabling / disabling the gates (G) of the other buffers 903 to 905 for the A, B, A-, and B- signals for outputting the phase data of the motor. , EN1 and EN2 signals.

The control unit including the communication controller 901 and the load unit including the child communication IC 902 are connected by a pair of communication lines CLK and DATA and power supply lines of +5 V, GND, +24 V, and PGND. I have.

The internal configuration of the control unit according to the present invention is the same as that of the first embodiment, and the description is omitted.

FIG. 10 shows the configuration of the transfer register 941 in the communication controller 901. For example, it is assumed that the transfer register 941 in FIG. 10 is set to “00000001”. As a result, the phase data of the pulse motor generated in the phase data generator 939 is transferred to the data register 0. When the phase data is transferred to the data register 0, the phase data is transmitted to the slave communication IC 902, and the pulse motor operates by outputting the phase data from the slave communication IC 902.

Here, data registers 0 to 7 are 8 bits, and 3 bits other than bits corresponding to phase data are
Corresponding to the outputs EN0, EN1, and EN2 of the slave communication IC 902. By manipulating these three bits from the host CPU 900, the outputs of the buffers 903 to 905 are enabled / disabled.

Next, the operation of the communication controller 901 for operating the pulse motors 905 to 907 will be described.

First, the host CPU 900 sets a transmission flag in the communication controller 901 to enable transmission. Next, the host CPU 900 sets the transfer register 941 to “00000001”, and enables the phase data of the pulse motor generated in the phase data generator 939 to be transferred to the data register 0. Next, the child communication IC
The bits in the data register 0 corresponding to the outputs EN0, EN1, and EN2 of the 902 are enabled. Next, the host CPU 900 enables the operation flag in the phase data generator 939 to operate the phase data generator 939.

The host CPU 900 causes a child communication IC
When the bits in the data register 0 corresponding to the outputs EN0, EN1, and EN2 of the 902 are enabled, the data of the data register 0 is transferred to the child communication IC 902, and the outputs of the buffers 903 to 905 are enabled.

When the phase data generating section 939 starts operation, the phase data for driving the pulse motor each time the timer (not shown) detects the elapse of a predetermined timer time as in the first embodiment. generate. When the phase data is generated, the transfer unit 940 transfers the phase data to the data register 0 according to the information of the transfer register 941.

When the phase data is set in the data register 0, the data in the data register 0 is transmitted to the child communication IC 902. This allows the phase data to be
902, and via buffers 903-905, motor drivers 909-911 control driving of the motors 906-908, respectively.

As described above, the transfer section 940 transfers the phase data for driving the pulse motor to the data registers 0 to 7 based on the information of the transfer register 941, and the child communication IC corresponding to the data registers 0 to 7 And outputs phase data from the plurality of slave communication ICs, and
By serially transmitting gate signals of a plurality of buffers connected to C, it is possible to simultaneously drive a plurality of pulse motors having the same characteristics.

While the phase data generator 939 is operating,
By manipulating the bit corresponding to the gate signal of the buffer in the data register, it is possible to select whether to enable / disable the outputs of the plurality of buffers, and to select whether to drive or not drive each of the plurality of pulse motors. It is also possible to do.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, four child communication I divided into two units
An example will be described in which four pulse motors are simultaneously driven by transmitting the same phase data to C.

FIG. 11 shows a schematic configuration of a serial communication system according to the present invention.

The present serial communication system can be configured as an electrophotographic image forming apparatus such as a copying machine. Hereinafter, in this example, an example in which the image forming apparatus is configured as an image forming apparatus will be described.

Control unit, load unit A,
The load unit B is built in the image forming apparatus. The control unit is configured as a control unit of the apparatus main body, and controls serial communication between the load unit A and the load unit B. The load unit A includes a child communication IC 1102 (address 0), a child communication IC 1103 (address 1), and a child communication IC 1104 as child communication means.
(Address 2) and a child communication IC 1105 (address 3) are provided, and the load unit B has a child communication IC 1106 (address 4) and a child communication IC 1107 as child communication means.
(Address 5), child communication IC 1108 (address 6),
A child communication IC 1109 (address 7) is provided.

The slave communication ICs 1102 and 1103 include pulse motors 1110 and 1111 disposed at appropriate positions in the apparatus.
Are connected. In addition, the child communication ICs 1104 and 1105 include:
A plurality of sensors 1114, 11 located in place in the device
15 are connected. Child communication ICs 1106 and 1107
Has a pulse motor 111 disposed at an appropriate position in the apparatus.
Motor drivers 1118, 11 for driving 6, 1117
19 are connected. The child communication IC 1104 is connected to a driver 1121 for driving a plurality of solenoids 1120 arranged at appropriate places in the apparatus. Also,
A plurality of sensors 1122 arranged at appropriate places in the apparatus are connected to the slave communication IC 1109. The combination of motors, sensors, and the like connected to each of the slave communication ICs 1102 to 1109 is not limited to the configuration of the present example.

A control unit including a communication controller 1101 and child communication ICs 1102 to 1105
Unit A and child communication ICs 1106 to 11 including
09, communication lines 1150 and 1151 and power supply lines of +5 V and GN, respectively.
D, + 24V, and PGND. These two communication lines 1150 and 1151 are connected by a clock line (CLK) and a data line (DATA), respectively.

Here, the internal configuration of the control unit according to the present invention will be described. The control unit includes a host CPU 11 for controlling the image forming apparatus.
00 and a communication controller 1101 as communication control means for controlling serial communication for transmitting or receiving predetermined data in time series on a data line (DATA). The host CPU 1100 is connected to the communication controller 1101 via a bus, and exchanges communication commands and data with the communication controller 1101.

The communication controller 1101 is configured as shown in FIG.
, The serial communication unit 1130 and the transfer unit 114
0 and a phase data generator 1139.

The serial communication unit 1130 includes data registers 0 to 7, a serial communication control unit 1131, a transmission buffer 1132, a shift register 1133, a reception buffer 1134, a shift register 1135, a selector 1
137. Data registers 0 to 7 correspond to child communication IC 1102 (address 0) to child communication IC 1109
(Address 7).

The serial communication control section 1131 has a select register 1136 shown in FIG. In the select register 1136, information relating to the connection state of the communication lines 1150 and 1151 to which the child communication ICs 1102 to 1109 corresponding to the data registers 0 to 7 are set is set. The information set in the select register 1136 is determined by the number of child communication ICs and the load status connected to the child communication ICs, is programmed in the host CPU 1100 in advance, and is set by the host CPU 1100 at initial time.

Here, information on the connection state set in the select register 1136 will be described. When the number of child communication ICs connected to one set of communication lines is large, information for selecting all the child communication ICs connected to the one set of communication lines is set, and the information is set to one set of communication lines. When the number of connected child communication ICs is small, information for selecting the child communication IC connected to the multi-system communication line is set.

Then, based on the set information,
The communication lines 1150 and 1151 are selected by the selector 1137.
Is selected. Thereby, the communication controller 11
01 is a child communication IC corresponding to each data register 0-7
Transmission or reception communication is performed with respect to 1102 to 1109.

FIG. 13 shows the structure of the select register 1136 in the communication controller 1101. In the select register 1136, information about the end address of the child communication ICs 1102 to 1105 connected to the communication line 1150 is set. Therefore, the address of the slave communication IC contacting the communication line 1150 or 1151 is automatically determined according to the information content set in the select register 1136.

For example, the select register 113 shown in FIG.
6 is “00000011” (end address information = 3)
Is set to Thereby, the communication line 1
It can be seen that four child communication ICs 1102 to 1105 from address 0 to address 3 are connected to 150. Accordingly, the communication line 1151 includes four child communication ICs 1106 to 1 from address 4 to address 7.
It can be seen that 1109 is connected.

The transfer section 1140 has a transfer register 1141 shown in FIG. This transfer register 1141
Is set with information on transfer information to which data register the phase data of the pulse motor generated in the phase data generator 1139 is transferred. Information set in the transfer register 1141 includes the number of child communication ICs,
It is determined by the number of pulse motors connected to the slave communication IC, and is programmed in advance in the host CPU 1100.
Set by the PU 1100.

FIG. 13 shows the configuration of the transfer register 1141 in the communication controller 1101. For example, assume that the transfer register 1141 in FIG. 13 is set to “00110011”. Thereby, the phase data generation unit 11
The pulse motor phase data generated in step 39 is sequentially transferred to the data register 0, the data register 1, the data register 4, and the data register 5. When each of the phase data is transferred to the data register, the phase data is sequentially transmitted to each slave communication IC, and each pulse motor operates by outputting the phase data from the slave communication IC.

When the transfer register 1141 is set to “0001001” while the phase data generator 1139 is operating, the transfer of the phase data to the data register 5 is stopped. Thereby, the child communication IC 1107 (address 5)
Will also be stopped.

Next, the pulse motors 1110, 1111,
The operation of the communication controller 1101 for operating 1116 and 1117 will be described.

First, the host CPU 1100 sets a transmission flag in the communication controller 1101 so that transmission is possible. Next, the host CPU 1100 sets the transfer register 1141 to “00110011” so that the phase data of the pulse motor generated in the phase data generator 1139 can be transferred to the data registers 0 to 2. Next, the host CPU 1100 enables the operation flag in the phase data generator 1139 to operate the phase data generator 1139.

When the operation is started, phase data generating section 1139 generates phase data for driving the pulse motor every predetermined timer time. When phase data occurs,
The transfer unit 1140 sequentially transfers the phase data to the data register 0, the data register 1, the data register 4, and the data register 5 according to the information of the transfer register 1141.

When the phase data is set in the data register 0, the serial communication control unit 1131
The data register 0 corresponding to 02 is selected one-to-one.
At this time, in the select register 1136, information (terminal address information) indicating to which communication line the child communication IC 1102 corresponding to the data register 0 is connected is set.

Then, the serial communication control unit 1131 transfers the data in the data register 0 to the shift register 1133 via the transmission buffer 1132. At this time, the serial communication control unit 1131
Is read out, and the selector 11 is read in accordance with the read out information on the connection state.
At 37, the communication line 1150 is selected. A clock (CLK) and a pulse train are transmitted to the communication line 1150. The child communication IC 11 is synchronized with this clock output.
02 communicates with the slave communication IC 1
102. As a result, the phase data is
The motor driver 1112 controls the driving of the pulse motor 1110 based on the phase data output from the C1102. At this time, there is no clock and no pulse train output on the communication line 1151.

When the communication with the slave communication IC 1102 is completed, the data register 1 in which the phase data is set in advance
The communication line 1150 selects the data of the child communication IC 1
By communicating with 103, phase data is similarly output from the slave communication IC 1103, and the motor driver 1111 controls the drive of the pulse motor 1113 based on the phase data. At this time, there is no clock and no pulse train output on the communication line 1151.

Similarly, when the communication to the child communication IC 1103 is completed, the data in the data register 4 is transferred to the communication line 115.
By selecting 1 and communicating with the slave communication IC 1106, the phase data is similarly output from the slave communication IC 1106,
The motor driver 1118 controls the driving of the pulse motor 1116 based on the phase data. Similarly, when the communication to the slave communication IC 1106 is completed, the data of the data register 5 is selected by selecting the communication line 1151 and the slave communication IC 1106 is output.
By communicating with 1107, phase data is similarly output from the slave communication IC 1107, and the motor driver 1119 controls the drive of the pulse motor 1117 based on the phase data. At this time, the communication line 1150 includes:
There is no clock or pulse train output.

As described above, the transfer unit 1140 communicates with the child communication ICs corresponding to the data registers 0 to 7 based on the information of the transfer register 1141, and outputs the phase data from the plurality of child communication ICs. The same pulse motor having a plurality of characteristics can be driven at the same time. Also, it is executed in the serial communication control unit 1131.
The selection control process of the communication lines 1150 and 1151 based on the information set in the select register 1136 is performed by time division, and the child communication IC divided into two units
Can be driven at the same time.

Further, by setting the transfer register 1141 while the phase data generator 1139 is operating, the phase data is transferred to the data registers 0 to 7 /
It is also possible to select whether or not to perform the driving and to select whether or not to drive each of the plurality of pulse motors.

Further, even when a plurality of communication lines are provided,
Communication is possible by increasing the number of select registers having information on which communication line the child communication IC corresponding to each of the data registers 0 to 7 is connected to.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus. In this case, by reading a storage medium storing a program represented by software for achieving the present invention into the system or the apparatus, the system or the apparatus can enjoy the effects of the present invention.

[0092]

As described above, according to the first to eleventh aspects of the present invention, the same pulse motor phase data is transmitted to a plurality of slave communication ICs by serial communication according to the contents of the communication data set in the data register. By doing so, it is possible to provide a data transmission system in which a plurality of pulse motors having the same characteristics can be operated at the same time and an efficient image forming apparatus can be configured by reducing the number of bundles.

Further, a plurality of communication lines are prepared as in the invention of claim 5, and the communication lines are selected in a time-division manner according to the connection information content to which data register set in the first select register to transfer. In addition, since communication is performed with a predetermined slave communication IC, a plurality of pulse motors having the same characteristics and divided into multiple systems can be simultaneously operated, so that an efficient image forming apparatus can be configured. A data transmission system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a conventional serial communication system.

FIG. 2 is a block diagram illustrating a configuration example of a serial communication system in a conventional image forming apparatus.

FIG. 3 is an explanatory diagram showing a configuration example of a transmission pulse train.

FIG. 4 is an explanatory diagram showing a configuration example of a reception pulse train.

FIG. 5 is a block diagram illustrating a configuration example of a pulse motor drive circuit in a conventional image forming apparatus.

FIG. 6 is a block diagram illustrating a configuration example of a serial communication system in the image forming apparatus according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating a configuration example of a communication controller.

FIG. 8 is an explanatory diagram showing a configuration example of a transfer register.

FIG. 9 is a block diagram illustrating a configuration example of a serial communication system in an image forming apparatus according to a second embodiment of the present invention.

FIG. 10 is an explanatory diagram illustrating a configuration example of a transfer register.

FIG. 11 is a block diagram illustrating a configuration example of a serial communication system in an image forming apparatus according to a third embodiment of the present invention.

FIG. 12 is an explanatory diagram illustrating a configuration example of a communication controller.

FIG. 13 is an explanatory diagram showing a configuration example of a transfer register and a select register.

[Explanation of symbols]

 601 Communication control means 602 to 604 Child communication means 639 Phase data generation means 640 Phase data transfer means 641 First select register 901 Communication control means 902 Child communication means 939 Phase data generation means 940 Phase data transfer means 941 First select register 1101 Communication control means 1102 to 1109 Child communication means 1136 Second select register 1137 Selector 1139 Phase data generation means 1140 Phase data transfer means 1141 First select register

Claims (11)

[Claims] A communication control means for controlling serial communication for transmitting and receiving predetermined serial data in a time series on one communication line; and a communication control means connected to the communication control means, and A plurality of slave communication units for transmitting and receiving data, the communication control unit including a data register for storing communication data corresponding to the plurality of slave communication units on a one-to-one basis; and for driving a pulse motor. Phase data generating means for generating phase data of: a first select register in which information on which of the plurality of data registers the phase data generated by the phase data generating means is to be transferred is set; Phase data transfer means for transferring the phase data to the plurality of data registers based on the first select register, wherein the phase data transfer means By transferring the phase data to a plurality of data registers, serially transmitting the phase data by connecting to the predetermined slave communication means, and outputting the phase data from the plurality of slave communication means, a plurality of pulse motors A data transmission system characterized by driving the same under the same control. 2. The apparatus according to claim 1, wherein said phase data generating means includes a phase data storage means for storing said phase data,
Timer means for measuring time for performing constant speed / deceleration speed control, and when the timer means detects that a predetermined timer time has elapsed, the phase data in the phase data storage means is stored in the phase data storage means. 2. The data transmission system according to claim 1, wherein the data is transferred to the plurality of data registers based on one select register. 3. The transfer information set in the first select register is determined according to the number of the child communication units and a load state connected to the child communication unit. Item 2. The data transmission system according to Item 1. 4. An image forming apparatus for controlling image formation in an image forming unit by a plurality of control units, comprising: the data transmission system according to claim 1; A phase for controlling a pulse motor from the communication control means to the plurality of child communication means; incorporating the communication control means of the data transmission system into the control unit; An image forming apparatus wherein a plurality of pulse motors are driven under the same control by serially transmitting data. 5. A communication control means for controlling serial communication for transmitting and receiving predetermined serial data in a time series on one communication line; and said communication control means being connected to said communication control means, A plurality of slave communication units for transmitting and receiving data, the communication control unit including a data register for storing communication data corresponding to the plurality of slave communication units on a one-to-one basis; and for driving a pulse motor. Phase data generating means for generating phase data of: a first select register in which information on which of the plurality of data registers the phase data generated by the phase data generating means is to be transferred is set; Phase data transfer means for transferring the phase data to the plurality of data registers based on the first select register; the communication control means; A plurality of communication input / output units connected to the slave communication unit; and a communication selection unit provided in the communication control unit and selecting the plurality of communication input / output units in a time-division manner. The data transfer means transfers the phase data to a plurality of data registers, and the communication selection means selects the plurality of communication input / output means in a time-division manner to connect to predetermined child communication means and serially transmit the phase data. A data transmission system, wherein a plurality of pulse motors are driven by the same control by outputting the phase data from the plurality of slave communication units. 6. The phase data generating means includes: phase data storage means for storing the phase data;
Timer means for controlling the speed of constant speed / deceleration. When the timer detects that a predetermined timer time has elapsed, the phase data is stored in the plurality of data registers based on the first select register. The data transmission system according to claim 5, wherein the data is transferred. 7. The transfer information set in the first select register is determined according to the number of the child communication units and a load state connected to the child communication unit. Item 6. A data transmission system according to item 5. 8. The communication selecting means, wherein the plurality of child communication means corresponding to the data register have a second select register in which connection information as to which communication input / output means is connected is set. The data transmission system according to claim 5, wherein: 9. The connection information set in the second select register is determined according to the number of the child communication units and / or a load condition connected to the child communication unit. 9. The data transmission system according to claim 8, wherein: 10. The plurality of communication input / output means,
6. The data transmission system according to claim 5, wherein only the communication input / output unit selected by the communication input / output unit inputs / outputs a synchronization clock and a communication pulse train. 11. An image forming apparatus for controlling image formation in an image forming section by a plurality of control units, comprising: the data transmission system according to claim 5; Incorporating the child communication unit into the image forming unit, incorporating the communication control unit of the data transmission system into the control unit, and using the plurality of communication input / output units to communicate between the communication control unit and the child communication unit. Connected, the communication control means selects the plurality of communication input / output means in a time-division manner, and drives the plurality of pulse motors under the same control by serially transmitting phase data for controlling the pulse motor. Image forming apparatus.