JPH08125672A - Bus interface device - Google Patents

Abstract

PURPOSE: To arrange lots of stations on a bus and to connect the interface even to a bus having a termination structure adapted to AC. CONSTITUTION: Serial signals each 1-bit are sent to a couple of signal lines L1, L2 in a form of a 3-level current (high level, low level and medium level with respect to the 1-bit signal). Then an intermediate connecting point between 1st and 2nd variable current sources Q1, Q2 connected in series and one signal line L1 are connected and the other signal line L2 and a point of a reference potential are connected by a signal connection means. An operational amplifier U1 is provided to provide a control signal to increase/decrease differentially output currents of the 1st and 2nd variable current sources so that a signal voltage produced on one signal line and a signal voltage TXIN being an external command signal are coincident.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device suitable for a common transmission line bus having a transmission speed of about 31.25 kbps, which is widely used in process control and the like, and more particularly, a multi-station arrangement on the bus. And an easy improvement of an interface to an existing bus.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram of a conventional current output type bus interface device. In the figure,
The pair of signal lines L1 and L2 are common transmission line buses and transmit current signals. A plurality of communication stations ST are arranged on the bus to exchange signals on the bus. The transmitter TX and the receiver RX are provided.
have. The transmission unit TX inputs a serial 1-bit signal from a communication frame creation unit separately provided inside the communication station ST and outputs a current signal corresponding to the serial 1-bit signal. For example, H level is 19 mA, L The level is 1 mA, and the neutral level when not sending is 10 mA. If the impedance of the signal lines L1 and L2 is 100Ω, the voltage corresponding to this current signal 10 ± 9 mA is 0.5.
It becomes ± 0.45V.

According to such a current transmission type, there is an advantage that the bus condition can be maintained well. For example, even if a failure occurs in a certain communication station ST and H-level current continues to flow to the bus, this is equivalent to a temporary change in the neutral level for the entire bus. On the other hand, if a failure occurs in a certain communication station ST of the voltage transmission type and the H level voltage continues to flow to the bus, it is recognized as the H level voltage in the entire bus. Cannot be done. Therefore, according to the current transmission type, it is also possible to carry out remote search for a faulty station using the ringing / non-responsive bus usage.

On the other hand, a drawback of the current transmission type is that since the number of stations that can be arranged on the bus is limited by the current transmission capacity of each communication station, the current transmission capacity of each communication station can be changed according to the intended number of stations. It is necessary to strengthen. For example, when 10 communication stations having a neutral level of 10 mA are arranged on the bus, the neutral level currents are superposed on the bus, and a DC voltage of 5 V is resident on the bus. Therefore, each communication station has a problem of requiring the ability to overcome this resident voltage and supply current.

FIG. 14 is a circuit diagram of a common transmission line bus.
(A) shows a DC matching type termination structure, and (B) shows an AC matching type termination structure. The pair of signal lines L1 and L2 is a common transmission line bus of a type called a twisted pair.
In (A), two termination resistors RT and one ground capacitor C0 are provided at the end. RT 50 here
When Ω and C0 are 10 μF, the impedance is 100 Ω in the entire frequency band. On the other hand, FIG. 14 (B)
As described above, if a terminating resistor RT and a grounding capacitor C0 are paired in each signal line L1 and L2 to form an AC matching type terminating structure, an open impedance is obtained in the DC region and the low frequency region. As a third type, there is a type in which a DC voltage is supplied as a bias current to an AC matching type termination structure to reduce the current sending capability of each communication station.

The suitability of the bus interface device for the several types of common transmission path buses is as follows. First, the current transmission type bus interface device is suitable for a bus having a DC matching type termination structure and a bus having an AC matching type termination structure to which a bias current is applied, but a simple AC matching type termination structure. Not fit for buses with. This is because, in the simple AC matching type, the impedance in the DC region corresponds to an open circuit, so that the neutral level current of the communication station saturates and signal transmission becomes impossible.

[0007]

As described above,
Although the current transmission type bus interface device has an advantage that the bus condition can be maintained well, it is difficult to arrange a large number of stations on the bus due to the superposition of the neutral level currents, and the AC adaptable termination structure is also provided. There is a problem that it cannot be connected to a bus having The present invention solves the above problems, and provides a current transmission type bus interface device capable of arranging a large number of stations on a bus and being connectable to a bus having an AC adaptable termination structure. The purpose is to do.

[0008]

According to the present invention which achieves such an object, a serial 1-bit signal is supplied to a pair of signal lines L1 and L2 in a high level, a low level and a neutral level. A bus interface device for transmitting with three-level current values, comprising first and second variable current sources Q1 and Q2 connected in series, an intermediate connection point of the first and second variable current sources, and A signal deriving means 10 which is connected to one of the signal lines L1 and also connects the other of the signal lines L2 to a reference potential, a signal voltage generated on the one signal line, and a signal voltage TXIN commanded from the outside. And an operational amplifier U1 for outputting a control signal for differentially increasing / decreasing the output currents of the first and second variable current sources so that the input currents coincide with each other.

[0009]

In the first and second variable current sources Q1 and Q2, the other receives the current from one side, and the surplus current flows through the pair of signal lines L1 and L2 forming the bus. The operational amplifier matches the potential at the intermediate connection point of the first and second variable current sources with the signal voltage TXIN commanded from the outside, so that the operating point is adjusted regardless of whether or not the surplus current flowing through the bus is present. It is held at a constant value. This enables connection to a bus having an AC matching type termination structure.

Preferably, the neutral level current value is set to the first
It is preferable that the current values transmitted and received between the second variable current source and the second variable current source are equalized so that the current flowing through the pair of signal lines becomes zero and the signal voltage generated in one signal line becomes zero. Then, since the phenomenon of superimposing on the current value at the neutral level does not occur, many bus interface devices can be mounted on the bus.

[0011]

1 is a block diagram showing the construction of a bus interface device according to an embodiment of the present invention. In the figure, the first current source Q1 receives power from the constant voltage circuit E1,
The second current source Q2 is supplied with power from the constant voltage circuit E2, and both are connected in series. And the first
The current flowing through the current source Q1 is I _Q1, and the current flowing through the second current source Q2 is I _Q2 . The signal line L1 is the first current source Q1.
Connected to an intermediate connection point between the second current source Q2 and the second current source Q2, and its output current Iout is a surplus current (I _Q1 −I ₁₎ which is a difference between the current flowing from the first current source Q1 and the current flowing into the second current source Q2. It is equal to _Q2 ). The signal line L2 is grounded inside the transmitting station TX.

The operational amplifier U1 sends a control signal to the first current source Q1 and the second current source Q2 to control the output current Iout and the output voltage flowing through the signal line L1, and the plus terminal is an external μ processor. 1-bit signal T sent from
XIN is input, and the potential of the signal line L1 is input to the negative terminal via the feedback resistor R _FB . A feedback capacitor C _FB for integration is connected between the output terminal and the negative terminal of the operational amplifier U1, and the output current Iout is controlled so that the 1-bit signal TXIN and the potential of the signal line L1 match. . An AC component may be superimposed on the output current Iout flowing through the signal line L1, but in order to smooth this, attenuation is given by the impedance ratio of the feedback resistor R _FB and the feedback capacitor C _FB , and the control output of the operational amplifier U1 is provided. The influence of the feedback resistor R _FB is prevented from appearing. Further, the output terminal of the operational amplifier U1 and the control terminals of the first current source Q1 and the second current source Q2 are connected by a broken line.
This is because it is inherently considered to perform conversion so as to match the control input format of the current source Q1 and the second current source Q2.

FIG. 2 is an explanatory diagram of signals handled by the apparatus of FIG. There are three types of 1-bit signal TXIN: + 0.5V (high level), 0V (neutral level), and -0.5V (low level). Then, in the steady state, the output signal of the operational amplifier U1 becomes the same as the 1-bit signal TXIN, and the current IQ1 flowing through the first current source _Q1 is 10 /
The current I _Q2 flowing through the second current source _Q2 is 5/1 mA and 1/5/10 mA, respectively. Therefore, the output current Iout flowing through the signal line L1 becomes 9/0 / -9 mA. Assuming that the impedance of the bus is 100Ω, a voltage wave of 0 ± 0.45V will be generated on the bus. Since the voltage at the neutral level is 0 V, the DC voltage does not reside on the bus, and the multi-station arrangement on the bus becomes easy.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention in which the operating voltage inside the transmitting station TX and the operating voltage of the bus can be set independently. In the figure, the first current source 10 is intended to flow a current I _Q1 to resistor R1 connected to the emitter terminal of the transistor Q1, resistor DC power supply voltage Vcc and the resistor R3 to the base terminal R4 + R5
The voltage divided by is applied. The second current source 20 supplies a current _IQ2 to a resistor R2 connected to the emitter terminal of the transistor Q2, and a DC power supply voltage V
A voltage obtained by dividing cc by resistors R3 + R4 and resistor R5 is applied. The collector terminals of the transistors Q1 and Q2 are connected via the diodes D1 and D2, and the common connection point of the diodes D1 and D2 is connected to the signal line L1 via the output circuit 40. The diodes D1 and D2 have a low impedance due to a high collector voltage of the transistors Q1 and Q2, and the variable current value cannot be maintained.
It is provided for protection so that it does not affect 1.

The output circuit 40 is an insulating capacitor CL in consideration of the case where there is a DC potential difference between the transmitting station TX and the bus L1.
1 and a resistor RL1 inserted between the signal lines L1 and L2 for impedance matching. This resistance RL1 is
This is to prevent static electricity from being stored between the signal lines L1 and L2, and a resistance value that is high enough to be ignored with respect to the impedance of the bus is selected. The operation check point CP is provided between the output circuit 40 and the common connection point of the diodes D1 and D2.
Is provided.

The input circuit 50 connects the transmitter station TX and external equipment.
Considering the DC voltage difference, the 1-bit signal TXIN is
It is input via the sensor C21. Here, 1-bit signal
Signal TXIN is converted to DC power supply voltage Vcc to neutral level
Since I want to input to the plus terminal of operational amplifier U1,
Source voltage Vcc is divided by resistors R21 and R22 to neutral level
High level and low level are based on the neutral level
Appears as a rising and falling signal. Minus of operational amplifier U1
The potential at the operation check point CP is fed back to the terminal through the feedback resistor R _FBThrough
And the feedback terminal for integration with the output terminal.
Indexer C_FBIs installed.

The current value setting unit 30 is provided between the output terminal of the operational amplifier U1 and the first and second current sources, and has the emitter terminal of the transistor Q1 and the transistor Q1.
Resistors R11 to R14 connecting between the two emitter terminals
Are connected in series, the capacitor C11 is connected in parallel with the resistor R12, and the capacitor C12 is connected in parallel with the resistor R13. By connecting the capacitors C11 and C12 in parallel with the resistors R12 and R13, the DC consumption current is reduced and the impedance of the AC component is reduced. One of the currents flowing from the DC power supply voltage Vcc through the resistors R1 and R3 is R1 →
Transistor Q1 → diode D1 → diode D2 →
There is a path of transistor Q2 → R2, and as a shunt path, R1 → R11 → R12 + C11 → R13 + C12 →
There will be R14 → R2. The output terminal of the operational amplifier U1 is connected to the common connection point of the resistors R12 and R13.

The operation of the thus constructed apparatus will be described below. The input circuit 50 determines the neutral level by dividing the DC power supply voltage Vcc by. Therefore, set Vcc to 5V,
If the resistors R21 and R22 are selected with the same resistance value, this neutral level becomes 2.5V. Therefore, 1-bit signal TX
High level and low level sent as IN are 2.5 ±
Appears as a 0.5V signal. The output current Iout flowing through the signal line L1 is, for example, in the range of ± 0.375V to ± 0.5V on an arbitrary neutral level. That is, since an error of 25% is allowed as the accuracy of the voltage flowing through the bus, the accuracy of the current values of the first and second current sources can be about several%.

Specific numerical values of the first current source 10 and the second current source 20 will be described. Now, set Vcc to 5V and set the resistance R
If 3 to R5 have almost the same resistance value, the transistor Q
The base voltage of 1 is biased at 3.4V and the base voltage of transistor Q2 is biased at 1.6V. Due to this bias voltage, the transistors Q1 and Q2 are rendered conductive, and a current of, for example, 8.5 mA flows to the emitter resistors R1 and R2 (both have a resistance value of about 110Ω). This emitter current also flows through the current setting unit 30.

FIG. 4 is an explanatory diagram of the output voltage of the operational amplifier U1 and the current value in each part. 1-bit signal TXIN is + 0.5V (high level), 0V (neutral level) or-
There are three types of output voltage of the operational amplifier U1 of 3.0 / 2.5 / 2.0V depending on whether the output voltage is 0.5V (low level). Then, in the item indicated by I (R1 + R11) in the second column, the current flowing through the emitter resistor R1 and the current flowing through the resistor R11 are displayed, which are (8.3 + 1.7) / (8.5-1.7) / (8.9
-7.6) mA current flows. Also, in the third column, I (R2 +
In the item indicated by R14), the current flowing through the emitter resistor R2 and the current flowing through the resistor R14 are displayed, and a current of (8.9-7.6) / (8.5-1.7) / (8.3 + 1.7) mA flows respectively. . Therefore, the current I _{Q1 of the} resistor R1 and the current I _{Q2 of the} resistor R2
Are 10 / 5.3 / 1.3 mA and 1.3 / as shown in the fourth column.
It is 5.3 / 10mA.

According to the apparatus shown in FIG. 3, 100Ω
The voltage level of the output current Iout flowing through the signal line L1 of the system is ± 0.43V, and the characteristic substantially equal to ± 0.45V of the device of FIG. 1 is obtained, and the high level / neutral level / low level of the bus is obtained. Signals in three states can be transmitted. Also, since the potential is zero at the neutral level, even if many stations are connected to the bus, each transmitting station can output a signal to the bus and connect to the bus, as if a few stations were connected to the bus. Eliminating the need to determine the transmission capability of the transmitting station in consideration of the number of stations.

FIG. 5 is a waveform diagram of the current sent from the transmitting station TX to the 100Ω system bus, showing an example in which a DC voltage of 10 V is applied between the signal line L1 and the signal line L2. In the figure, (A) shows the output potential V _U1 of the operational amplifier _U1 ,
(B) is the current I _{BU S} flowing through the bus, and (C) is the signal line L.
1, the potential between L2 V _{L1, L2,} the potential V _CP at (D) the operation check point CP. The output potential V _U1 about initial 50μS the operational amplifier U1 is a 2.5V representing the neutral level,
After that, the high level 3V and the low level 2V are repeated at a cycle of about 15 μS. Correspondingly, the current I _BUS flowing through the bus is initially 0 mA, which indicates a neutral level of about 50 μS, but thereafter repeats a high level of 10 mA and a low level of −10 mA at a cycle of about 15 μS.
Next, the potentials V _{L1 and L2} between the signal lines L1 and L2 are 50
About μS is 10V that represents the neutral level, but then 1
High level 10.5V and low level 9.5 in a cycle of about 5μS
V is repeated. In addition, the potential V at the operation confirmation point CP
_CP indicates the same motion substantially the output potential V _U1 of the operational amplifier U1.

FIG. 6 is a waveform diagram of a current sent from the transmitting station TX to the 100Ω system bus, and shows an example in which a DC voltage of −10V is applied between the signal line L1 and the signal line L2.
Here, the output potential V _U1 of the operational amplifier U1, the waveform diagram of the current I _BUS flowing through the bus, and the potential V at the operation confirmation point CP are shown.
_CP is the same as in FIGS. 5A, 5B and 5D. Since the potential V _{L1, L2} between the signal lines L1, L2 is influenced by the applied DC voltage, but the order originally 50μS is -10V representing a neutral level, high level -9.5V and low in a period of subsequent approximately 15μS Repeated level-10.5V.

FIG. 7 is a waveform diagram when the bus end is removed from the 100Ω system bus shown in FIG. 5 and the bus is opened. The output potential V _U1 of the operational amplifier U1 is the same as FIG 5 (A). However, the bus has no direct current line and no alternating current line. Therefore, the current I _BUS flowing through the bus
Is almost zero, becomes thereto correspondingly signal line L1, the potential between L2 V _{L1, L2} the voltage waveform given by the saturation voltage values of the first and second current sources, the initial 50μS about neutral level The voltage is 10V, but thereafter, the high level 11.5V and the low level 7.5V are repeated in a cycle of about 15 μS. Then, the potential V _CP at the operation confirmation point _CP is 50 at the initial value.
About μS is 2.5V, which represents the neutral level, but then 1
The high level 4V and the low level 1V are repeated at a cycle of about 5 μS.

FIG. 8 is a waveform diagram when a sine wave of about 40 kHz is applied between the signal lines L1 and L2. In the figure, (A) is the output potential V _U1 of the operational amplifier U1, (D) is the potential V _CP at the operation confirmation point CP, and (E) is the potential V _BUS generated on the bus. Here, the sine wave is given as a potential V _BUS generated on the bus and has a voltage wave of ± 0.5V.
On the other hand, the output potential V _U1 of the operational amplifier U1 is 2.5 V,
Signal transmission to the bus is stopped. The potential V _CP at the operation check point CP inside the transmitter TX is ± 0.5 which is the same as the potential V _BUS.
It is a voltage wave of V.

That is, an external voltage is applied to the output circuit 40.
Voltage at the operation check point CP _CPIs the potential of the bus
Become equal. This is the power supplied from the first current source 10.
Current flows into the second current source 20, and this current value is external
It is not affected by the voltage and therefore the transmitter circuit T
Make sure that no current flows inside X.
It represents.

In FIG. 9, the signal lines L1 and L2 are connected to a DC voltage of 10V.
FIG. 3 is a waveform diagram showing a transient response when connected to a bus to which is applied. The connection, increase the potential V _{L1, L2} between the signal lines L1, L2 is increased to 10V equal to the applied DC voltage bus from 0V, the potential V _CP at the operation check point CP and associated from 0V to the 10V To do. Then, the operational amplifier U1 responds to the voltage imbalance with TXIN to turn off the first current source 10 and maintain the current of the second current source 20, so that the bus connected from the signal lines L1 and L2 to the bus. Of the current appears as the current I _BUS , and here, a current of about −7 mA flows for about 2.5 mS. The insulating capacitor CL1 is charged by the current I _BUS , and the potential V _CP at the operation confirmation point _CP also gradually decreases from 10V to around 3V.

Then, the OFF state of the first current source 10 is released, and the feedback control by the operational amplifier U1 is started. The output potential V _U1 of the operational amplifier U1 is the operation confirmation point CP.
_So that the potential V _{CP at} will be restored to the neutral level of 2.5V
Although it changes slowly at a voltage of about 2.3V, such a change occurs through the capacitor C12 and the resistor R13 to the second current source 2
Sent to 0 for fine adjustment. When the first current source 10 is turned off, the current flowing through the resistor R1 escapes to the base of the transistor Q1 and flows through the resistor R4.
2 works to increase the current. On the other hand, this resistance R4
The current flowing through the resistor R5 has the effect of reducing the current flowing through the resistor R5, so that the two cancel each other out and the first current source 10
Turning off does not significantly affect the current of the second current source 20.

FIG. 10 is a circuit diagram showing a third embodiment of the present invention, in which an overvoltage protection circuit 60 is added as compared with the circuit diagram of FIG. The overvoltage protection circuit 60 includes an operational amplifier U.
The overvoltage protection function is added to the functions of the feedback resistor R _FB and the feedback capacitor C _FB that connect 1 to the operation check point CP. That is, two feedback resistors R3 connected in series between the operation confirmation point CP and the negative terminal of the operational amplifier U1.
1, R32 are connected, and the feedback resistors R31 and R3 are connected.
Constant voltage type limiter diodes D31 and D32 are connected between the connection point 2 and the output terminal of the operational amplifier U1. A parallel circuit of a feedback capacitor C31 and a limiter resistor R33 is connected between the negative terminal and the output terminal of the operational amplifier U1. Here, the limiter resistance R33
Is a proportional limiter resistor that limits the output voltage of the operational amplifier U1.

The operation of the thus constructed device will be described below. The operational amplifier U1 outputs a 1-bit signal TXIN2.5 ± 0.5 V input to the plus terminal with a gain of 1. The limiter voltage of the limiter diodes D31 and D32 is ± 0.6 V, which is generally used for silicon diodes.
Use the degree. In this way, the overvoltage protection circuit 60 has almost no influence on the operation of the transmitter TX during the normal operation, and protects only when the overvoltage is applied. Specifically, the signal lines L1 and L2 as shown in FIG.
Is connected to a bus to which a DC voltage of 10 V is applied, the potential V _CP at the operation check point _CP becomes excessive and feedback resistance R _FB
This is the case when I join. At this time, the limiter diode D
32 conducts and prevents the output voltage V _U1 of the operational amplifier U1 from making an excessive transition. That is, the output voltage V _U1 of the operational amplifier U1 is because it is suppressed within the normal range of use, to facilitate subsequent to occur the level of recovery.

Next, the operation of the limiter resistor R33 will be described. 11 is a waveform diagram for explaining the operation of the device of FIG. 10 with the limiter resistor R33 removed.
(A) is the output potential V _U1 of the operational amplifier U1, and (D) is the potential V _CP at the operation confirmation point CP. Signal line L at time T0
1, L2 are connected to a bus to which a DC voltage of 10V is applied. Then, during the period from time T0 to T1, as described above, the first
The current source 10 is turned off, and the potential V _CP at the operation confirmation point CP gradually decreases. Then, at time T1, the first current source 10 is turned off, and the feedback control by the operational amplifier U1 is started. However, at time T2, the potential V _CP at the operation confirmation point CP exceeds 2.5 V, which is the neutral level, and drops and becomes an overshoot state. Then, at time T3, final settling is performed.

FIG. 12 is a waveform diagram for explaining the operation of the apparatus of FIG. 10. The operation of the limiter resistor R33 becomes clear by comparing with the waveform diagram of FIG. That is, at time T0, the signal line L
1, L2 are connected to a bus to which a DC voltage of 10V is applied. Then, during the period from time T0 to T1, as described above, the first
The current source 10 is turned off, and the potential V _CP at the operation confirmation point CP gradually decreases. Then, at time T1, the first current source 10 is turned off, and the feedback control by the operational amplifier U1 is started. Then, at time T2, the potential V _CP at the operation confirmation point _CP is settled at 2.5 V which is the neutral level.

[0033]

As described above, according to the present invention, the operational amplifier U1 outputs the current corresponding to the 1-bit input signal TXIN to the signal lines L1 and L2, so that the DC voltage does not reside on the bus. Even if a large number of transmitting stations are arranged on the same bus, the same transmitting station as when a small number of transmitting stations are arranged on the bus can be used, which has the effect of increasing versatility.

Further, according to the second embodiment shown in FIG. 3, since capacitors are serially attached to the output circuit 40 and the input circuit 50 to insulate the inside of the transmitter and the external signal line from each other by DC. There is an effect that it is possible to connect to a bus to which a DC voltage is applied and to an open bus whose impedance is not managed. Furthermore, the third shown in FIG.
According to this embodiment, since the overvoltage protection circuit 60 is provided, the effect on the bus when connected to the bus is reduced, and the adaptability at the time of installation in the field is increased.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of signals handled by the device of FIG.

FIG. 3 is a configuration block diagram showing a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of an output voltage of an operational amplifier U1 and a current value in each part.

FIG. 5 is a waveform diagram of a current sent from a transmitting station TX to a 100Ω system bus.

FIG. 6 is a waveform diagram of a current sent from a transmitting station TX to a 100Ω system bus.

FIG. 7 is a waveform diagram when the bus end is removed from the 100Ω system bus shown in FIG. 5 to open the bus.

FIG. 8 is a waveform diagram when a sine wave of about 40 kHz is applied between the signal lines L1 and L2.

FIG. 9 is a waveform diagram showing a transient response when the signal lines L1 and L2 are connected to a bus to which a DC voltage of 10V is applied.

FIG. 10 is a circuit diagram showing a third embodiment of the present invention.

11 is a waveform diagram for explaining the operation of the device of FIG. 10 with the limiter resistor R33 removed.

12 is a waveform chart explaining the operation of the apparatus of FIG.

FIG. 13 is a block diagram showing a configuration of a conventional current output type bus interface device.

FIG. 14 is a circuit diagram of a common transmission line bus.

[Explanation of symbols]

 10 First Current Source 20 Second Current Source 30 Current Value Setting Section 40 Output Circuit 50 Input Circuit U1 Operational Amplifier

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Yamaguchi 2-9-32 Nakamachi 2-chome, Musashino-shi, Tokyo Yokogawa Electric Co., Ltd.

Claims (2)

[Claims] 1. A bus interface device for transmitting a serial 1-bit signal to a pair of signal lines (L1, L2) according to the current values of the high-level, low-level, and neutral levels of the 1-bit signal. The first and second variable current sources (Q1, Q1) connected in series.
2), and a signal deriving means for connecting the intermediate connection point of the first and second variable current sources to one of the signal lines (L1) and connecting the other of the signal lines (L2) to the reference potential. And a signal voltage (TXIN) commanded from the outside by inputting the signal voltage generated in the one signal line, and the output currents of the first and second variable current sources are differentiated so that they match each other. Operational amplifier (U1) that outputs a control signal to increase / decrease
And a bus interface device. 2. The neutral level current values are the first and second current values.
2. The current values transmitted and received between the variable current sources are set to be equal to each other so that the current flowing through the pair of signal lines is zero and the signal voltage generated in one of the signal lines is also zero. Bus interface equipment.