JP3175139B2 - Two-wire pulse signal transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-wire type pulse signal transmission apparatus suitable for use in a common transmission line bus having a transmission speed of about 31.25 kbps widely used in process control and the like. In addition, the present invention relates to a structure for avoiding mutual interference between code and DC in a common transmission line of a type for transmitting DC.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional current sending type bus interface device. In the figure, a pair of signal lines L1 and L2 are a common transmission path bus for transmitting a current signal. A plurality of communication stations ST are arranged on the bus for transmitting and receiving signals on the bus, and include a transmitting unit TX and a receiving unit RX. The transmitter TX receives a serial 1-bit signal from a communication frame generator separately provided inside the communication station ST, and outputs a current pulse signal corresponding to the serial 1-bit signal in a predetermined carrier frequency band.

FIG. 8 is a diagram for explaining the relationship between the general structure of a common transmission path bus and a bus interface device. The pair of signal lines L1 and L2 is a common transmission line bus of a type called a twisted pair, and each terminal is provided with two pairs of signal lines L1 and L2, each including a terminating resistor RT and a ground capacitor C0. Then, one end of the ground capacitor C0
The other end of the ground capacitor C0 is not grounded. Here, the constant of the element used for the termination is, for example, 50Ω for RT and 10 μF for C0. The bus power supply PS1 is a circuit for supplying a current to the bus, and an output inductance Z1 of, for example, about 20 mH is inserted in series. The transmitting / receiving station ST outputs a 1-bit pulse train signal to the bus, and is provided with an operating station power supply PS2. For such a common transmission path bus, the voltage of the bus power supply PS1 is selected to be a constant voltage such as 20V, 10V or 0V. The transmitting / receiving station ST connected to such a bus is of a current type, and the current is transmitted at the voltage of the bus power supply PS1.

FIG. 9 shows that the transmitting / receiving station ST is connected to a 50-100Ω system bus.
In the transient response waveform diagram when connected, the signal line L1 and the signal line
A DC voltage of 20 V from the bus power supply PS1 is impressed during L2.
FIG. In the figure, (A)
Potential V between signal lines L1 and L2_{L1 , L2}, (B) flows to the bus
Current I_BUS, (C) show the output voltage V of the bus power supply PS1.
_PS1, (D) show the output current I of the bus power supply PS1._PS1In
You. From 0 ms to time T0 (0.1 ms), the transmitting / receiving station S
When T is not connected, the signal line potential V_{L1, L2}Is the power supply for the bus
It is equal to the DC voltage of 20 V by PS1. Also,
Current I_BUSAnd the output current I of the bus power supply PS1_PS1Is 5m
A, and is conventionally connected between the signal lines L1 and L2.
Power is being supplied to the connected device.

[0005] From time T0 to time T1 (0.4 ms),
In the transient state immediately after the connection of the transmitting / receiving station ST, the signal line potentials V _{L1 and L2} drop from the DC voltage of 20 V by the bus power supply PS1 to about 19.2 V, and then recover to 19.8 V which is lower by the station voltage drop ΔV _BUS. . On the other hand, the bus current I _BUS increases by the station connection current ΔI _BUS to 18 mA. The output current I _PS1 of the bus power supply PS1 is 18 m from the initial 5 mA.
A gradually increases to A.

After the lapse of time T1, transmission of a pulse signal to the bus by the transmitting / receiving station ST starts, and the signal line potentials V _{L1 and L2}
Is a pulse signal of 19.8 V ± 0.3 V corresponding to the H and L levels repeated at a period of approximately 30 μS. Corresponding to this, the bus current I _BUS also flows alternately at 18 ± 6 mA. Such transmission of the pulse signal to the bus by the transmitting / receiving station ST is performed by the station power supply P.
Since the power is supplied by S2, the output voltage V _PS1 of the bus power supply PS1 maintains a balanced value of 20 V, and the output current I _PS1 of the bus power supply _PS1 also maintains a balanced value of 18 mA.

FIG. 10 shows a bus power supply PS1 and signal lines L1 and L1.
It is a frequency characteristic figure of output inductance Z1 located between L2. From the viewpoint of supplying a DC current to the bus, the DC impedance Zf _DC is preferably as low as possible. On the other hand, the carrier frequency fcarry transmits a pulse train signal, considering the output impedance of the transmitting station ST, the impedance Zf _H output inductance Z1 should preferably be sufficiently high. Generally, the output inductance Z1 has a preferable property that the DC impedance Zf _DC is low and the impedance Zf increases in proportion to an increase in frequency.

[0008]

However, since the output inductance Z1 is intended to supply power to a bus having a DC load, it is difficult to manufacture the output inductance Z1 to a value that is negligibly small due to structural limitations. The problem arises. That is, the choke coil, which is an inductance, is formed by applying a winding to an iron core. Generally, when a direct current is passed, the iron core approaches saturation and the inductance L decreases. Structure is used. However, the combined structure of the iron core and the air core cannot provide a high magnetic permeability, so that the number of windings increases to obtain a required inductance. Then, there was a problem that the size of the choke coil was increased and the DC resistance was increased. This tendency becomes more remarkable as more DC current is allowed.

As a result, the DC voltage is applied to the bus power supply PS1.
Despite being stabilized at 20V, the signal line potential V
_{L1, L2}Station voltage drop ΔV_BUSOccurs. Also, the transmitting / receiving station S
The potential between the buses fluctuates or drops depending on the number of connected T
Is not desirable. The present invention solves the above problems.
Thus, even if the number of connected transceiver stations ST changes, the signal line potential V
_{L1, L2}Is regulated to the output voltage of the bus power supply.
It is an object to provide a pulse signal transmission device.

[0010]

In order to achieve the above object, the present invention provides a grounding capacitor C0 and a terminating resistor RT connected to an end of a signal line and a grounding capacitor connected via the grounding capacitor C0. and the pair of signal lines L1, L2 which are connected to the other signal line, a bus power supply PS1 supplies a DC current having a predetermined DC bus voltage V _bUS between the pair of signal lines, the pair of signal lines And a transmitting station ST connected through an output capacitor C _L1 to transmit a current pulse signal having a predetermined carrier frequency via the output capacitor. Output impedance and feedback frequency dependent impedance circuits Zfout, Zffb with low impedance and high impedance in the carrier frequency band transmitted by the transmitting station.
The bus power supply outputs a DC voltage to the signal line via an output frequency dependent impedance circuit Zfout, and outputs the output voltage V _BUS by feeding back the output voltage via a feedback frequency dependent impedance circuit Zffb. It is characterized in that voltage stabilization is performed.

[0011]

The bus power supply applies a bus voltage to the pair of signal lines L1 and L2.
A DC voltage is output to the signal line via fout. Here, since these output and feedback frequency dependent impedance circuits have high impedance in the carrier frequency band transmitted by the transmitting station, the influence of the bus power supply does not appear on the current pulse signal output to the bus by the transmitting station. . Further, since the output frequency dependent impedance circuit has a low impedance with respect to the direct current, it does not hinder the supply of the direct current to the signal line. Further, since the output voltage V _BUS is fed back via the feedback frequency dependent impedance circuit Zffb to stabilize the output voltage of the bus power supply, even if the number of power connections to the transmitting and receiving stations fluctuates, the bus voltage is increased. The inter-potential is kept stable.

Further, since the transmitting station is connected to the pair of signal lines L1 and L2 via the output capacitor C _L1 , the communication station does not substantially affect the DC current, and the current output to the bus is not affected. Only relevant for pulse signals. Therefore, there is no mutual interference between the DC and the carrier frequency band.

[0013]

FIG. 1 is a block diagram showing the configuration of a two-wire pulse signal transmission apparatus according to an embodiment of the present invention. In FIG. 1, components having the same functions as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted. In the figure, a bus power supply PS1 is
Outputs a DC current of the DC voltage V _BUS through the output inductor Zfout to the signal lines L1, L2, is stabilized feedback to the output voltage of the output voltage V _BUS of the output inductance via a feedback inductance Zffb. Therefore, the output voltage of the bus power supply PS1 to the output inductance Zfout is equal to the voltage drop Δ in the output inductance Zfout.
The voltage V _PS1 takes into account V _ZOUT . Transmitting station ST
Is intended to be connected through an output capacitor C _L1 and a pair of signal lines L1, L2, and a driver circuit for transmitting a current pulse signal of a predetermined carrier frequency through the output capacitor C _L1.

FIG. 2 shows the apparatus shown in FIG.
In transient response waveform diagram connected to Ω system bus, as in FIG. 9 (A) the signal line L1, the potential between L2 V _{L1, L2,}
(B) is the current I _BUS flowing through the bus, (C) is the output voltage V _PS1 of the bus power supply PS1, and (D) is the output current I _PS1 of the bus power supply PS1. From 0 mS to time T0 (0.1 mS), the signal line potential V
_{L1 and L2} have a DC voltage of 20V, and the bus power supply PS1 has a slightly higher voltage of 20.2V. Also, the bus current I _BUS
And the output current I _PS1 of the bus power supply PS1 is 5 mA, and is conventionally used as power for devices such as field instruments connected between the signal lines L1 and L2.

From time T0 to time T1 (0.4 ms),
In a transient state immediately after the transmission / reception station ST is connected, the signal line potentials V _{L1 and L2} are reduced from the DC voltage of 20 V by the bus power supply PS1 to about 19.3 V, and then recovered to 20 V. On the other hand, the bus current I _BUS increases by the station connection current ΔI _BUS to 1
8 mA. The output voltage V _PS1 of the bus power supply PS1 is
Since the voltage gradually increases from the initial 20.2V to 20.5V, the supply voltage increment ΔV _PS1 per communication station is about 0.3V.
Since the output current I _PS1 of the bus power supply PS1 gradually increases from the initial 5 mA to 20 mA, the supply current ΔI _PS1 per communication station becomes about 15 mA.

After the lapse of the time T1, transmission of the pulse signal to the bus by the transmitting / receiving station ST is started, and the signal line potentials V _{L1, L2}
The pulse signal of 20.0V ± 0.3V is repeated at a cycle of approximately 30 μS corresponding to the H and L levels. Corresponding to this, the bus current I _BUS also flows alternately at 18 ± 6 mA. Such transmission of the pulse signal to the bus by the transmitting / receiving station ST is performed by the station power supply P.
Since the power is supplied by S2, the output voltage V _PS1 of the bus power supply PS1 maintains the balanced value of 20.5 V, and the output current I _PS1 of the bus power supply _PS1 also maintains the balanced value of 20 mA.

Next, a detailed internal configuration of the transmitting / receiving station ST will be described. FIG. 3 shows a transmitting / receiving station S having an output capacitor C _L1 .
In the circuit diagram showing an example of T, only the transmission function TX is shown. In the figure, a first current source 10 is connected to the plus side PS2 + of the office power supply PS2, a second current source 20 is connected to a minus side PS2- of the office power supply PS2, and both are connected in series. Then, the first current source 10 increases or decreases the supply current _IQ1 according to the control signal, and the second current source 20 differentially supplies the supply current _IQ2 to the first current source 10 according to the control signal.
Increase or decrease. The intermediate connection point CP between the first current source 10 and the second current source 20 is connected to the signal line L1 via the output capacitor C _L1 . From the output capacitor C _L1 , the difference current (I _Q1 −I _Q2 ) between the current I _Q1 supplied from the first current source Q1 and the current I _Q2 drawn by the second current source Q2 is output current Iout to the signal line L1. Flows as

Here, the positive side PS2 of the station power supply PS2
+ Is connected to the signal line L2, the negative side PS2- station power PS2 is connected to the signal line L1 through the bias resistor R _L1. Here, since the reference potential of the bus power supply PS1 is selected for the signal line L2, PS2 + is the reference potential and PS2- is the DC power supply voltage -Vcc.

Next, the details of the first current source 10 and the second current source 20 will be described. The first current source 10 flows a current _IQ1 through a resistor R1 connected to the emitter terminal of the transistor Q1, and supplies a DC power supply voltage -Vcc to a current setting unit 3 at a base terminal.
A voltage V _Q1 divided by 0 is applied. Second current source 2
0 in which electric current I _Q2 to the resistor R2 connected to the emitter terminal of the transistor Q2, the voltage V _Q2 is applied obtained by dividing by the current setting unit 30 to the DC power source voltage -Vcc is the base terminal. The collector terminals of the transistors Q1 and Q2 are connected via diodes D1 and D2, and a common connection point CP of the diodes D1 and D2 is connected to a signal line L1 via an output capacitor _CL1 . . Diodes D1 and D2 are connected to transistors Q1 and Q2, respectively.
However, it is provided for protection so that even if the impedance becomes low due to a high collector voltage or the like and the variable current value cannot be maintained, the signal line L1 is not affected.

The input feedback circuit 40 inputs the 1-bit signal TXIN via the capacitor Cin in consideration of the DC voltage difference between the transmitting station ST and the external device. If the operating potential is set to -Vcc / 2, which is half the output voltage of the bus power supply PS1, the operation becomes symmetrical with respect to the neutral level.
(PS2-) is divided to connect between the input capacitor Cin and the buffer U1. Note that the voltage dividing resistors R7, R8
May be omitted. The potential of the intermediate connection point CP fed back via the feedback resistor R _FB, and sends to the buffer U1 adds the 1-bit signal TXIN input via a capacitor Cin. The current value setting unit 30 is provided between the input feedback circuit 40 and the first and second current sources, and includes a resistor R3 connecting between the emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2. R5, R6 and R4 are connected in series in this order.

The fact that feedback control is performed in the device configured as described above will be described. It is assumed that the output voltage of the buffer U1 has increased. Then, the control voltage V _Q1 of the current setting unit 30 increases. In response, the supply current _IQ1 of the first current source 10 decreases. On the other hand, since the control voltage V _Q2 of the current setting unit 30 also increases, the sink current I _Q2 of the second current source 20 decreases correspondingly. As a result, the equilibrium between the supply current I _Q1 and the sink current I _Q2 is lost, so that a current that compensates for this unbalanced state flows through the output capacitor C _L1, and the potential of the intermediate connection point CP decreases. Therefore,
The reduced potential is fed to the feedback resistor R _FB to the buffer U1, the output voltage of the buffer U1 is decreased. Thus, the output current Iout corresponding to the one-bit signal TXIN is supplied to the signal line L1.

FIG. 4 is an explanatory diagram of signals handled by the apparatus shown in FIG. There are three types of 1-bit signal TXIN: high level, neutral level, and low level, and a signal is input at [neutral level potential] ± 0.5V. Here, the transmitting station T
Feedback control works at X, the neutral level potential is -2.
5V, high level is -2.0V, low level is-
3.0V. Then, the output signal of the buffer U1 is in the steady state becomes the same as the 1-bit signal TXIN, it receives the control voltage V _Q1 of the current setting portion 30 -0.95 / -1.19 / -1.43
V, and the control voltage V _Q2 is −4.05 / −3.81 / −3.
It becomes 57V. Therefore, the current I supplied by the first current source Q1 is
_Q1 is 3.7 / 6.6 / 9.5 mA, and the current I _Q2 flowing to the second current source _Q2 is 9.5 / 6.6 / 3.7 mA, respectively. Therefore, the output current Iout flowing through the signal line L1 is 5.8 / 0.0 / −5.8
mA.

FIG. 5 is a circuit diagram showing another embodiment of the present invention. Here, the frequency-dependent impedance circuit Zfou
As t and Zffb, a time constant circuit using a capacitor and a resistor is used. In the figure, a bus power supply PS1
Is an AC-DC converter, which converts the detention power supply AC into a rough AC voltage according to the turns ratio with a power transformer PT,
Rectified by diodes D11 and D12, smoothing capacitor C
11, the DC voltage Vcc is obtained.

The operational amplifier U11 has a positive terminal connected to a resistor R1.
A reference voltage Vref using a series circuit of 1 and a constant voltage diode D13 is input, a feedback resistor R19 is connected to the minus terminal, and a feedback capacitor C12 for integration is connected between the minus terminal and the output terminal. The output frequency dependent impedance circuit includes a transistor Tr1 and a capacitor C
13 as a main component, and the transistor Tr1
Of the operational amplifier U11 via a resistor R13.
Output terminal is connected, the collector terminal connected to the DC voltage Vcc is connected via a resistor R14, the emitter terminal is connected to a signal line L1 via a resistor R15, and between the emitter terminal and the base terminal. Is the capacitor C1
3 is connected.

The feedback frequency dependent impedance circuit is
The main components are capacitors C12 and C14. The signal line potentials V _{L1 and L2} are divided by resistors R16 and R17 and integrated into the capacitor C14 via a resistor R18. The potential integrated by the capacitor C14 is applied to the resistor R19.
, And is fed back to the minus terminal of the operational amplifier U11. Since the negative feedback control loop is formed by using the CR time constant circuit as described above, its impedance curve is shown in FIG.
As shown by the dashed line 0, it is low at DC and high in the carrier frequency domain.

FIG. 6 shows the apparatus shown in FIG.
In transient response waveform diagram connected to Ω system bus, as in FIG. 9 (A) the signal line L1, the potential between L2 V _{L1, L2,}
(B) shows the current I _BUS flowing through the bus, (D) shows the output current I _PS1 of the bus power supply PS1, and (E) shows the base terminal voltage V _B of the transistor Tr1. From 0 mS to time T0 (0.1 mS), the transmission / reception station ST is not connected, the signal line potentials V _{L1 and L 2} are DC voltage 20 V, and the base terminal voltage V _B is 20.7 V slightly higher than that. . The bus current I _BUS and the output current I _PS1 of the bus power supply _PS1 are 5 mA.

From time T0 to time T1 (0.4 ms),
In a transient state immediately after the transmission / reception station ST is connected, the signal line potentials V _{L1 and L2} are reduced from the DC voltage of 20 V by the bus power supply PS1 to about 19.3 V, and then recovered to 20 V. On the other hand, the bus current I _BUS increases by the station connection current ΔI _BUS to 1
8 mA. After the base terminal voltage V _B has dropped to about 20.1 V, it gradually increases to 20.8 V, which is slightly higher than before, so that the control voltage increment ΔV _B per communication station is about 0.1 V. The output current I _PS1 of the bus power supply PS1 is 5
Since the current gradually increases from mA to 19 mA, the supply current ΔI _PS1 per communication station is about 14 mA.

After the elapse of time T1, transmission of the pulse signal to the bus by the transmitting / receiving station ST starts, and the signal line potentials V _{L1 and L2}
The pulse signal of 20.0V ± 0.3V is repeated at a cycle of approximately 30 μS corresponding to the H and L levels. Corresponding to this, the bus current I _BUS also flows alternately at 18 ± 6 mA. Such transmission of the pulse signal to the bus by the transmitting / receiving station ST also affects the base terminal voltage V _B and causes a voltage change in a pulse form. However, the time constant circuit works effectively, and the output of the bus power supply PS1 is output. The current I _PS1 maintains a balanced value of 20 mA, and operates substantially the same as the circuit of FIG.

[0029]

As described above, according to the present invention, in the bus power supply PS1 for supplying a direct current of a predetermined voltage to the signal lines L1 and L2, the bus is connected to the signal line via the output frequency dependent impedance circuit Zfout. Since the DC voltage is output and the output voltage V _BUS is fed back through the feedback frequency dependent impedance circuit Zffb to stabilize the output voltage, the DC voltage is transmitted while having low impedance. The current pulse signal output from the station to the bus is not affected, and the signal line potentials V _{L1 and L2} are stably maintained even when the number of connected transmission stations increases or decreases. Further, according to the third aspect of the present invention, since the time constant circuit using the capacitor and the resistor is used instead of the choke coil which tends to be large, there is also an effect that the device can be downsized.

Further, since the communication station ST is connected to the signal lines L1 and L2 via the output capacitor, it is connected to the communication line with low impedance in the carrier frequency band and has high impedance in the DC band. Therefore, there is also an effect that the problem of the current consumption in charge of the power supply and the problem of the pulse signal transmission can be considered independently without considering the interaction, thereby facilitating the construction of the bus system.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention.

FIG. 2 is a transient response waveform diagram when the transmitting station ST is connected to a 50-100Ω system bus.

FIG. 3 is a circuit diagram showing an example of a transmitting / receiving station ST having an output capacitor C _L1 .

FIG. 4 is an explanatory diagram of signals handled by the device of FIG. 3;

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a transient response waveform diagram when the transmitting station ST is connected to a 50-100Ω system bus.

FIG. 7 is a configuration block diagram of a conventional current transmission type bus interface device.

FIG. 8 is an explanatory diagram of a relationship between a general structure of a common transmission path bus and a two-wire pulse signal transmission device.

FIG. 9 is a waveform diagram of a transient current generated when the transmitting station ST is connected to a 50 to 100Ω system bus.

FIG. 10 is a frequency characteristic diagram of an output inductance Z1 located between a bus power supply PS1 and signal lines L1 and L2.

[Explanation of symbols]

 L1. L2 signal line PS1 Power supply for bus PS2 Power supply for station ST Transmission / reception station Zfout Output frequency dependent impedance circuit Zffb Feedback frequency dependent impedance circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-43648 (JP, A) JP-A-4-120930 (JP, A) JP-A-6-197457 (JP, A) JP-A 8- 125672 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 25/00

Claims (3)

(57) [Claims] 1. A terminating resistor (RT) grounded via a grounding capacitor (C0) and connected to an end of a signal line.
1), the pair of signal lines (L1, L2) connected to the other signal line via the ground capacitor, and a predetermined DC bus voltage (V _BUS ) between the pair of signal lines.
A bus power supply (PS1) for supplying a DC current of the above-mentioned type, and a transmission for transmitting a current pulse signal of a predetermined carrier frequency via the output capacitor, connected via the pair of signal lines and the output capacitor ( _CL1 ). And a feedback frequency dependent impedance circuit (Zfo) having a low impedance with respect to the station (ST) and a direct current and a high impedance in the carrier frequency band transmitted by the transmitting station.
ut, Zffb), and the bus power supply outputs a DC voltage to the signal line via an output frequency-dependent impedance circuit (Zfout), and outputs the output voltage (V _BUS ) to a feedback frequency-dependent impedance circuit. A two-wire pulse signal transmission device, wherein the output voltage is stabilized by feedback through (Zffb). 2. The frequency-dependent impedance circuit comprises an output inductance and a feedback inductance. The bus power supply outputs a DC voltage to the signal line via the output inductance and an output voltage (V _{BUS) of the} output inductance. 2. The two-wire pulse signal transmission device according to claim 1, wherein the output voltage is stabilized by feeding back the feedback signal via a feedback inductance. 3. An output frequency-dependent impedance circuit comprising: a voltage-current conversion element (Tr1) for outputting a current corresponding to a control voltage sent to a base terminal from an output terminal; a base terminal and an output terminal of the voltage-current conversion element. And the feedback frequency-dependent impedance circuit is a time constant circuit (C14) for integrating the output voltage of the voltage-current conversion element.
And an integrator (U11) for comparing the voltage of the time constant circuit with a reference voltage (Vref) to integrate the error signal, and using the output voltage of the integrator as the control voltage of the base terminal. 2. The two-wire pulse signal transmission device according to claim 1, wherein: