JPH0341841A - Transmission/reception circuit - Google Patents

Abstract

PURPOSE:To obtain a reception circuit not limited by the protocol system by providing a differential amplifier capable of offset control, a comparing means comparing the output of the differential amplifier with a prescribed threshold level, an integration means and rectifying means. CONSTITUTION:When the output current IDIF of a differential amplifier 1 is negative, the relevant current -IDIF passes through a diode D2, amplified by a current amplifier 3 as the multiple of K and the result is added to an integration circuit 5. Consequently, the output of the circuit is decreased and the current -IDIF of the amplifier 1 is rapidly decreased attended therewith and approaches 0 and stopped in the equilibrium, that is, when the input of the circuit 5 reaches 0. When the current IDIF of the amplifier 1 is positive, the current IDIF flows to the amplifier 1 from a power supply +VCC via a resistor R and the diode D1. Thus, the circuit 5 is gradually charged by a minute bias current IB. Thus, the offset of the amplifier 1 is gradually changed and the current IDIF is decreased nearly linearly as shown in figure attended therewith and the sign of the current IDIF is inverted to obtain the equilibrium state.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a receiving circuit used in a balanced transmission system, and particularly to a transmission receiving circuit used in an automotive transmission system that requires high reliability. Regarding.

(Conventional technology and problems to be solved) In data communication in a car, data may be incorrectly transmitted,
If data transmission is not possible, it may have serious consequences depending on the nature of the failure. Moreover, the environment inside a car is harsher than that of a typical consumer car, and there is a high possibility that various types of failures will occur. For this reason, transmission devices mounted on vehicles are required to have high reliability.

Therefore, in the multiplex transmission system in a car, a balanced transmission system, that is, a system in which the twisted pair wires are driven by signals having mutually opposite signs, is adopted.
While trying to reduce noise from the outside or noise to the outside,
Even if one of the transmission lines is short-circuited to ground or has a failure such as an open circuit, the two lines form a kind of duplex system, and the remaining transmission line performs unbalanced transmission.

For example, a method uses a plurality of receiving steps connected to each differential transmission line, detects a bit sequence specific to a protocol, and selects the correctly detected step (Japanese Patent Laid-Open No. 12633/1983). ) has been proposed. However, in this method, the detection of the bit sequence differs depending on the transmission method, so the reception circuit and the logic circuit that detects the sequence and extracts the signal cannot be separated.

On the other hand, there is also a coupling method using a capacitor (Japanese Patent Application No. 63-90100) as shown in FIG. this is,
Each input terminal of the differential amplifier 21 is connected to the transmission lines A and B via the coupling capacitor 20, and the differential amplifier 2
1 through a level shift circuit 22 to a comparator 2 to which a threshold voltage VTR is applied to one input terminal.
This configuration is connected to the other input terminal of No. 3. According to this AC coupling method using a capacitor, the coupling capacitor 20 cuts the DC component, so even if one side of the transmission line is fixed at a constant potential, the DC component can be cut and received by the differential amplifier 21. . Moreover,
Regardless of the protocol, transmission is possible even if there is a failure on either side of the transmission line, and the interface circuit between the logic circuit and the transmission line can be separated.

However, such a method has a coupling capacitor 2
Since the differential amplifier 21 is used after 0, and the differential amplifier 21 is a high-speed operational amplifier, it is technically difficult to operate it with a single power supply of a low voltage, for example, 5V. Further, the level shift circuit 22 uses AC coupling using the coupling capacitor 20, and it is difficult to form it into a monolithic IC.

In addition, as shown in FIG. 6, the 10 input terminal and the - input terminal of the differential amplifier 25 are connected to the transmission line A on the + side and the transmission line B on the - side via coupling capacitors C1 and C2, respectively. There is also a transmission/reception circuit with a simple circuit configuration in which a diode D is connected between the terminals, the - input terminal side is connected to the power supply +Vcc via a resistor R1, and the - input terminal side is grounded via a resistor R2.

However, since this receiver circuit uses the forward voltage of diode D inserted between the buses as the threshold voltage, it is susceptible to temperature changes and can only be applied at a specific voltage threshold level. Can not. Furthermore, if this circuit is made into a monolithic IC, the voltage within the circuit may become lower than ground (GND) or higher than the power supply voltage +Vcc.
(2) There are problems such as parasitic effects occurring within the C and junction isolation not being completed completely.

The present invention has been made in view of the above points, and allows transmission even if an abnormality, such as an open or short circuit, occurs on one side of the transmission line. The level (threshold) can be set freely,
A further object of the present invention is to provide a transmission/reception circuit suitable for monolithic IC implementation.

(Means for Solving the Problems) In order to achieve the above object, according to the present invention, each input terminal are connected to the two transmission lines separately and are capable of offset control; a comparison means for comparing the outputs of the differential amplifiers with a certain threshold value; The apparatus is configured to include an integrating means for controlling the offset of the differential amplifier, and a rectifying means for applying manual power to the integrating means in accordance with the output of the differential amplifier.

(Function) When the output current of the differential amplifier is negative, a relatively large current is applied to the integrating means via the rectifying means, and as a result, the output of the integrating means rapidly decreases and the output current approaches 0. It stops at the equilibrium state, ie, when the input to the integrating means reaches zero. Also, when the output current of the differential amplifier is positive, the integrating means is gradually charged by the bias current, and the offset of the differential amplifier changes accordingly, and the output current gradually decreases until it reaches an equilibrium state. Stop. That is, the offset of the differential amplifier is adjusted so that the output current is a predetermined value no matter how the human power is fixed.

(Example) An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows the basic configuration of the receiving circuit of the present invention. Each input terminal of a differential amplifier 1 is connected to two transmission lines A and B, respectively, and the output terminal is connected to the cathode of a rectifying means 2, for example, a diode DI. It is connected to the connection point with the anode of the diode D2, and the anode of the diode DI is connected to the power supply +V through the resistor R.
cc, and the cathode of the diode D2 is connected to the summing point 4 via the current amplifier 3.

The connection point between the diode DI and the resistor R1 is connected to the input terminal of the comparator 5 at the next stage. A reference voltage (threshold value') Vt- is applied to one input terminal of the comparator 5. A bias power supply +VB is connected to the summing point 4, and a minute current 3 is supplied thereto. The output of this summing point 4 is connected to the input terminal of an integrating circuit 5, and the output terminal of the integrating circuit 5 is connected to the offset input terminal of the differential amplifier l.

The differential amplifier l is preferably a current output type, and the output direction of the current IDIF is defined as the direction in which the current IDIF flows into the differential amplifier l.

When the output current I DIF of the differential amplifier 1 is positive, a current proportional to the differential voltage flows through the diode Di and the resistor R
generate a voltage. On the other hand, the output current of differential amplifier l■
, 1. When is negative, the integrating circuit 5, which is charged with a minute current for a certain period of time, is charged with a relatively large current, that is, the output current IDIF of the differential amplifier 1 amplified by the current amplifier 3, K (K is the current amplifier's output current IDIF). The current output multiplied by the amplification factor) is fed back to the offset voltage control of the differential amplifier l.

The action will be explained below.

When there is no signal, that is, when the input terminal of the differential amplifier 1 is fixed at a constant voltage, the differential amplifier 1 operates differently depending on whether the output current IDIF is positive or negative. .

When the output current IDIF of the differential amplifier l is negative, the current -IDIF passes through the diode D2, is amplified twice by the current amplifier 3, and is added to the integrator 5 as a relatively large current. As a result, the output of the integrating circuit 5 decreases, and as a result, the output current of the differential amplifier l -IDIF rapidly decreases and approaches 0 as shown in FIG. 2, resulting in an equilibrium state (IDIF=IB/K ) That is, it stops when the input of the integrating circuit 5 reaches O.

Further, when the output current IDIF of the differential amplifier 1 is positive, the output current IDIF flows from the power supply +Vcc to the resistor R,
It flows into the differential amplifier 1 through the diode Di. Therefore, the integrating circuit 5 is gradually charged by the minute bias current Is. As a result, the offset of the differential amplifier l gradually changes, and as a result, the output current roar decreases approximately linearly as shown in FIG. 2, and finally the output current I.

1. The sign of is reversed, and (I o+p = I a /
When K) is reached, an equilibrium state is reached.

That is, no matter how the value of the differential input of the differential amplifier I is fixed, its output current IDIF is (Io+y
= IB /K), the differential amplifier l
offset is adjusted.

By the way, the current fed back to the integrating circuit 5 is the output current of the differential amplifier 1, 1. There is a large difference between positive and negative cases, and as a result, the time taken to reach the equilibrium state differs greatly. However, the output current IDIF (= In/K) of the differential amplifier l in the balanced state
is an extremely small value, and is very small considering the difference in input voltage, so it can be set to approximately 0.

When the differential amplifier 1 has reached a balanced state, the state shown in FIG.
), when a positive pulse is input to the positive input terminal of differential amplifier 1, and when a negative pulse is input to the negative terminal, positive and negative pulses are input to the positive and negative input terminals, respectively. The relationship between the input voltage and the voltage V across the resistor R is shown in FIG. 3(b). That is, as shown in FIG. 3(b), when a pulse is applied to increase the output current 1o+y of the differential amplifier 1 in the positive direction from the balanced state, a voltage V corresponding to the pulse voltage appears across the resistor R. .

Therefore, the reference voltage (threshold value) of comparator 5 ■7. ．．
By setting Vg to a low value as shown by the dotted line, Vg > V
, , and the comparator 6 determines whether a pulse is applied to both transmission lines A and B, a pulse is applied only to transmission line A, or a pulse is applied only to transmission line B. However, it becomes possible to regenerate the pulse.

Furthermore, while the pulse is being applied, the bias current In is supplied to the integrating circuit 5, but the pulse width is narrow;
It is not large enough to change the offset of the differential amplifier 1. Therefore, the differential amplifier l that fluctuated slightly during pulse application
As shown in FIG. 3(C), the offset voltage vF quickly returns to an equilibrium state due to the large current when the pulse is turned off. Therefore, even if the duty ratio of the pulse increases (the ratio of when the pulse is on compared to when it is off), the offset value hardly changes.

This allows reception even if either transmission line A or B is fixed at a constant voltage or is open. Moreover, the reference voltage V of the comparator 6
, 1 can also be freely set, which increases the degree of freedom in designing the transmission amplitude. Further, since the offset of the differential amplifier 1 is fed back and the balanced state is always constant, variations in the differential amplifier 1 itself are also absorbed, improving productivity.

In this way, the receiving circuit is controlled by the fact that the offset of the differential amplifier is fed back by the integrating means, and the time required for the feedback of the output of the differential amplifier to the integrating means to reach the equilibrium time depending on the sign of the output of the differential amplifier. It is possible to perform the same operation by making the circuit configuration different and having a comparison means for comparing the output of the differential amplifier with a constant voltage.

FIG. 3 shows a specific circuit configuration of the basic circuit shown in FIG.
4, each emitter is connected to a transistor Q5.
, Q6, the bases of which are transistors Q9, Q
10 emitters, and a resistor R is connected between each emitter.
1 is connected. Each emitter of transistors Q5, Q6 is connected to line 11, and the base of each is connected to transistor Q7.
, Q8 are connected to each base.

Each emitter of transistor Q3.4 is connected to line 12, the bases are connected to each other, the collector of transistor Q3 is connected to the base, and the collector of transistor Q4 is connected to the base of transistor Q19. The collectors of transistors Q9 and QIO are connected to line 12, and the bases of transistors Q9 and QIO are connected to the -input terminal and the -input terminal, respectively.

Line 11 is connected to the power supply +Vcc, and line 12 is connected to ground.

The emitters of transistors Q7, Q8 are connected to line 11, the collectors of transistors QIL Q12 to each collector and to the bases of transistors QIL Q12. A current mirror circuit is formed by transistors Q5 and Q6, and Q7 and Q8.

Each emitter of transistor QIL Q12 is connected to a constant current source S
l, S2 to line 12, each base connected to a transistor Q
13, is connected to the emitter of Q14, and a resistor R2 is connected between each emitter of QILQ12.
13 and Q14 are connected to the line 11, a predetermined fixed potential, for example, 1/2 of the power supply voltage +Vcc (+Vcc/2), is applied to the base of the transistor Q13, and the base of the transistor Q14 is connected to the capacitor C. connected to one end of the

These transistors Q1 to Q14, resistors R1, R2, constant current source S1.82, etc. form a differential amplifier circuit 15 with a current output controllable by a voltage corresponding to the differential amplifier l shown in FIG. The bases of Q9 and QIO are connected to the transmission line B on one side and the transmission line A on the + side as a - input terminal and a ten input terminal, respectively.

The collector of transistor Q15 is connected to line 1 through resistor R3.
1, the emitter is connected to the base of the transistor Q19, the base to the base of the transistor Q16, the collector of the transistor Q16 is connected to the output terminal of the constant current source S3, and the emitter is connected to the base of the transistor Q18. The emitter of transistor Q17 is transistor Q
15, Q16, and the collector is connected to the wire 11.
The base is connected to the output terminal of the constant current source S3.

The collector of the transistor Q18 is connected to the output terminal of the constant current #S3, the emitter is connected to the line 12, and the input terminal of the constant current source S3 is connected to the line 11. and,
A connection point between resistor R3 and transistor Q15 is connected to one input terminal of comparator 6. The input terminal of this comparator 6 has a reference voltage ■18. is applied. These resistor R2, transistors Q15 to Q18, constant current source S3, etc. form a rectifier circuit 16 corresponding to the rectifier circuit 2 of the resistor R and diode Di shown in FIG.

The collector of transistor Q19 is connected to the input terminal of constant current source S4, the emitter is connected to line 12, and the input terminal of constant current source S4 is connected to line 11.

This transistor Q19 corresponds to the diode D2 and current amplifier 3 in FIG.

One end of capacitor C is connected to transistor Q19 and constant current source S.
4 and the transistor Q1
4 and the other end is connected to line 12. These constant 2tta S4, transistor Q19, capacitor C, etc. form an integrating circuit 17 corresponding to the bias power supply and integrating circuit 5 shown in FIG.

The receiving circuit having such a configuration is manufactured as one monolithic IC. Note that the capacitor C of the integrating circuit 17 is externally connected.

Next, the effect will be explained.

The differential amplifier circuit consisting of transistors Qll to Q14, constant current sources St and S2, resistor R3, etc. of the differential amplifier 15 is as follows:
The base of transistor Q13 is at a fixed potential (Vcc/2)
The voltage input from the capacitor C of the integrating circuit I7 to the base of the transistor Q14 is equal to the voltage difference between the base of the transistor Q13 and the base of the transistor Q14.
The current i flowing through 8 is given as the current difference between 12. Furthermore,
These currents 1t-, L are connected to transistors Q7 and Q5,
The current flows to the emitters of transistors Ql and Q2 forming a differential amplifier circuit by current mirror circuits Q6 and Q8. The current difference between transistors Q5 and Q6 is added as an offset voltage of differential amplifier 15.

Furthermore, the current mirror circuit allows the transistor Q4 to
A positive or negative current ID□ is output to the output terminal a of the collector.

The capacitor C of the integrating circuit I7 is supplied with a minute bias current I by the constant current source S4, and the current output I
When DIF is negative, that is, the voltage mIDI from the differential amplifier 15
When F is in the flowing direction, the transistor Q7 causes the current IDIF to increase to the current amplification factor h1.F of the transistor Q7.
The current is multiplied and flows, discharging the capacitor C of the integrating circuit 17.

When the output current IDIF of the differential amplifier 15 is positive, that is,
The current sucked by the differential amplifier 15 is converted into a voltage by passing the current through the transistor Q15 and flowing into the resistor R2. This voltage is applied to comparator 6. Constant current source S
1. Transistors Q16 to Q18 are transistors Q15
is the bias value given to the base of , preferably 53=
34. The output current I of the differential amplifier 15 is determined by substantially matching the characteristics of the transistors Q15 and Q16, and Q17 and Q18. 1. When is 0, the current leaking from the emitter of the transistor Q15, flowing through the base of the transistor Q19, and discharging the capacitor C from the collector of the transistor Q19 becomes equal to the bias current In from the constant current source S4, and exactly IDIF= When the temperature reaches 0, an equilibrium state is reached.

(Effects of the Invention) As explained above, according to the present invention, in a transmission/reception circuit of a balanced transmission system in which signals with different signs are transmitted through two transmission lines, each input terminal is connected to one of the two transmission lines. A differential amplifier connected to each line and capable of offset control, a comparison means for comparing the output of the differential amplifier with a fixed threshold value, and a fixed bias current input and the output of the differential amplifier. Since the configuration includes an integrating means for controlling the offset and a rectifying means for supplying an input to the integrating means according to the output of the differential amplifier, it is not limited to the protocol method, and is open on one side of the transmission line. A receiving circuit that can transmit data even if a short circuit occurs can be easily configured using a monolithic IC. Furthermore, the threshold voltage of the comparator connected after the differential amplifier can be freely set, which has the effect of facilitating the design of the receiving circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the transmission/reception circuit according to the present invention, FIG. 2 is a diagram showing changes in the output current of the differential amplifier shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing a specific circuit example of the transmission/reception circuit shown in FIG. 1, and FIGS. 5 and 6 are block diagrams showing conventional transmission/reception circuits. be. 1.15... Differential amplifier, 2.16... Rectifier,
3...Current amplifier, 5.17...Integrator circuit, 6...
・Comparator, Ql-Ql9...transistor, 5l-3
4... Constant current source.

Claims (1)

[Claims] In a transmission/reception circuit for a balanced transmission system in which signals of different signs are transmitted through two transmission lines, each input terminal is separately connected to the two transmission lines, and the differential amplifier is capable of offset control. , a comparison means for comparing the output of the differential amplifier with a fixed threshold value, an integrating means for receiving a fixed bias current and controlling the offset of the differential amplifier according to the output thereof, and a comparator according to the output of the differential amplifier. and rectifying means for supplying an input to the integrating means.