JPH08125463A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To surely adjust an offset voltage of MOS transistors (TRs) with simple circuit configuration in an amplifier circuit comprising the MOS TRs. CONSTITUTION: Before a signal to be amplified is received from input sections 1, 2, a MOS TR 6 is conductive to connect gates G1, G2 of MOS TRs 2, 3 and a voltage applied to outputs Out1, Out2 to be given to an operational amplifier 9 by making MOS TRs 7, 8 conductive. The voltage is outputted from the operational amplifier 9 and charged to a capacitor 10. When an amplifier circuit 1 is in amplifier operation, MOS TRs 6-8 are nonconductive and the charge stored in the capacitor 10 is given to a base bias section KB1 of the MOS TR 3 of an SOI structure to adjust an offset voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to adjustment of an offset voltage in an amplifier circuit using a MOS transistor.

[0002]

2. Description of the Related Art According to a study made by the present inventor, in a semiconductor integrated circuit device, for example, in a circuit using MOS transistors, various circuit configurations have been adopted in order to absorb variations in characteristics of individual MOS transistors. Ingenuity is being made.

For example, in a differential amplifier circuit using a MOS transistor, by connecting a charge cancel transistor of about half the size of the MOS transistor to the output side of the MOS transistor, variations in the threshold voltage of the MOS transistor, An offset compensation circuit for adjusting the so-called offset voltage value is provided.

As an example of describing the offset voltage in the differential amplifier circuit using the MOS transistor, Ohm Co., Ltd. "LSI Handbook", published November 30, 1984, edited by the Institute of Electronics and Communication Engineers,
There are P135 and P136.

[0005]

However, the present inventor has found that the offset compensation circuit in the semiconductor integrated circuit device as described above has the following problems.

That is, in addition to the MOS transistor for amplification, a MOS transistor for offset compensation is required, which increases the layout area of the semiconductor element and reduces the degree of integration of the semiconductor element.

Further, as the layout area increases, changes in temperature distribution and unnecessary radiation noise also increase, and the electrical characteristics of the semiconductor integrated circuit device itself may vary.

Furthermore, since the number of MOS transistors to be configured increases, the variation in individual MOS transistors also increases, and the amplification efficiency decreases.

An object of the present invention is to provide a semiconductor integrated circuit device capable of reliably adjusting the offset voltage of a MOS transistor with a simple circuit configuration in an amplifier circuit composed of MOS transistors.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is provided with the offset voltage adjusting means for applying the offset adjusting voltage for adjusting the offset voltage to the substrate bias portion of the predetermined MOS transistor in the amplifying circuit using the MOS transistor. It is a thing.

Also, in the semiconductor integrated circuit device of the present invention, the offset voltage adjusting means is an MO to which an amplified signal is input.
First switching means for short-circuiting the gate portion of the S-transistor, second switching means, one of which is connected to a plurality of output portions for outputting the amplified signal to a predetermined circuit, and the other of the second switching means. Is connected to the input section and the output voltage is output to the substrate bias section of the predetermined MOS transistor, and one connection section is connected to the substrate bias section of the predetermined MOS transistor and the other connection section is set to the ground potential. It is composed of a connected capacitive element.

Further, the semiconductor integrated circuit device of the present invention is
The predetermined MOS transistor forms a silicon single crystal thin film on the insulating layer and forms a semiconductor element on the thin film.
It has an OI structure.

In the semiconductor integrated circuit device of the present invention, the first switching means and the second switching means are MOS transistors.

[0016]

According to the above-described semiconductor integrated circuit device of the present invention, the MOS transistor used in the amplifier circuit by the offset voltage adjusting means for applying the offset adjusting voltage for adjusting the offset voltage to the substrate bias portion of the predetermined MOS transistor. Even if the threshold voltages of the above are varied, the offset voltage can be easily adjusted in a short time.

Further, according to the above semiconductor integrated circuit device of the present invention, the gate portion of the MOS transistor to which the amplified signal is input is short-circuited by the first switching means, and the voltage output from the plurality of output portions is changed. The second switching means is short-circuited to be input to the operational amplification means, and the potential difference output from the operational amplification means is charged by the electrostatic capacitance element, and the first switching means and the second switching means during the amplification operation. And the electric charge accumulated in the capacitance element is applied to the substrate bias portion of the predetermined MOS transistor as an offset adjustment voltage before the amplification operation is easily performed in a short time. Can be surely adjusted.

Further, according to the above-described semiconductor integrated circuit device of the present invention, the predetermined MOS transistor has an SOI structure in which a silicon single crystal thin film is formed on an insulating layer and a semiconductor element is formed thereon. Since a complete element isolation structure can be realized, the parasitic capacitance can be reduced and the threshold voltage of the MOS transistor can be adjusted more accurately.

Further, according to the above-described semiconductor integrated circuit device of the present invention, the first switching means and the second switching means are MOS transistors, and ON / OFF control of the MOS transistors is controlled by the semiconductor integrated circuit device. By being controlled by the controlling CPU, the offset voltage can be automatically adjusted with a low-cost and simple circuit configuration.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a main part of a differential amplifier circuit provided with an offset voltage adjusting circuit in a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a differential circuit according to an embodiment of the present invention. It is a structure sectional view of a MOS transistor used for an amplifier circuit.

In the present embodiment, the amplifier circuit 1 in the semiconductor integrated circuit device is provided with MOS transistors 2 and 3, and the drain D1 of the MOS transistor 2 has one end of the resistor 4 for current limiting. It is connected. A power supply Vcc, which is a power supply voltage, is connected to the other end of the resistor 4.

Further, the drain D2 of the MOS transistor 3 is also connected to one end of the resistor 5, and the other end of the resistor 5 is connected to the power supply Vcc like the resistor 4. .

The sources S1 and S2 of the MOS transistors 2 and 3 are connected to the ground potential Vss, respectively.

Further, the gate G of the MOS transistor 2
1 and the gate G2 of the MOS transistor 3 serve as input portions In1 and In2 for the signals to be amplified, respectively.

Further, the amplifier circuit 1 is provided with an offset voltage adjusting circuit (offset voltage adjusting means) OC1,
The gate G1 of the MOS transistor 2 is connected to the source S3 (or also the drain) of the MOS transistor (first switching means) 6, and the gate G2 of the MOS transistor 3 is connected to the drain D3 (or source) of the MOS transistor 6. Be connected).

Further, a control signal output from a CPU (not shown) that controls the semiconductor integrated circuit device is input to the gate G3 of the MOS transistor 6, and the MOS transistor is output based on the control signal output from the CPU. 6
Is controlled.

Further, the amplified signals to be amplified are input to the gates G1 and G2 of the MOS transistors 2 and 3, and the signals amplified by the amplifier circuit 1 are output from the output units Out1 and Out2, respectively.

Further, the MOS transistor 3 is an SOI
It is molded by the structure. As shown in FIG. 2, in the MOS transistor 3 having the SOI structure, for example, an insulating layer 3b such as a silicon oxide film is formed on a semiconductor substrate 3a made of silicon, and a well (silicon single crystal thin film) 3c is formed thereon. Is forming.

Insulating layers 3d and 3e for element isolation are formed on both sides of the well 3c.
A source S2 and a drain D2 are formed on c.

Further, an insulating layer 3f for insulating the gate G2 is formed at predetermined positions on the source S2 and the drain D2.

An insulating layer 3g for isolating elements is formed on the side surface of the drain D2, and the well 3c between the insulating layer 3e and the insulating layer 3g becomes a substrate bias portion KB1 to which a substrate bias is applied. .

Further, an insulating layer 3i for insulating a predetermined wiring 3h made of aluminum or the like is formed at predetermined positions of the source S2, the gate G2, the drain D2 and the substrate bias portion KB1 and is formed on the wiring 3h. Also, the insulating layer 3j is formed.

Next, the drain D4 of the MOS transistor (second switching means) 7 is connected to the output section Out1, and the drain D5 of the MOS transistor (second switching means) 8 is provided after the output section Out2. Are connected.

Further, the MOS transistors 7 and 8 are also provided with operational amplifiers (operational amplification means) 9 to provide the MOS transistors.
The source S4 of the transistor 7 is connected to one input section of the operational amplifier 9, and the source S5 of the MOS transistor 8 is connected to the other input section of the operational amplifier 9.

Further, the control signals output from the CPU are also input to the gates G4 and G5 of the MOS transistors 7 and 8, and the MOS transistors 7 and 8 are controlled based on the control signals.

The output section of the operational amplifier 9 is M
It is connected to the substrate bias portion KB1 of the OS transistor 3. Further, one connection portion of the capacitor (electrostatic capacitance element) 10 is connected to the output portion of the operational amplifier 9, and the other connection portion is connected to the ground potential Vss.

Next, the operation of this embodiment will be described.

First, the CPU outputs a control signal to the gate G3 of the MOS transistor 6 before the amplified signal is input from the input units In1 and In2. The MOS transistor 6 whose control signal is input to the gate G3 is turned on, and the gates G1 and G2 of the MOS transistors 2 and 3 are short-circuited.

When a control signal is input from the CPU to the gate G3, the gate G of the MOS transistors 7 and 8 is
The control signal output from the CPU is also input to 4 and G5, and the MOS transistors 7 and 8 are also turned on.

At this time, if the threshold voltages of the MOS transistor 2 and the MOS transistor 3 are the same, the potential difference input to both input parts of the operational amplifier 9 is "0".
V ”, but if a potential difference occurs due to the variation of the threshold voltage, the difference between the voltage input to one input section of the operational amplifier 9 and the voltage input to the other input section of the operational amplifier 9 becomes Is output from.

Then, the voltage output from the output part of the operational amplifier 9 is applied to the capacitor 10 connected to the output part of the operational amplifier 9, and the electric charge is accumulated.

Next, the CPU includes the MOS transistors 6 and 6.
The control signals output to the gates G3, G4, G5 of the transistors 7, 8 are stopped, and the MOS transistors 6, 7, 8 are turned off.

As a result, the output of the operational amplifier 9 is 0V.
Then, the electric charge accumulated in the capacitor 10 is discharged, and the voltage is applied to the substrate bias portion KB1 of the MOS transistor 3 connected to the capacitor 10.

The voltage applied to the substrate bias portion KB1 of the MOS transistor 3 adjusts the variation in threshold voltage between the MOS transistor 2 and the MOS transistor 3, that is, the offset voltage.

Further, this MOS transistor 3 is SOI
Since it is molded by the structure, it is possible to realize a complete element isolation structure and reduce the parasitic capacitance.
The threshold voltage of the S transistor can be adjusted.

Therefore, in this embodiment, before the amplification operation, the variation in the threshold voltage of the individual MOS transistors 2 and 3 is detected, and the substrate bias portion KB1 of the MOS transistor 3 is supplied with the offset adjustment voltage. Since it is input, the amplifier circuit 1 having an extremely small offset voltage can be configured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0049]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, in the amplifier circuit using the MOS transistor, the threshold voltage of each MOS transistor can be easily adjusted by the offset voltage adjusting means, and the offset voltage is extremely small. it can.

(2) Further, in the present invention, the offset adjusting means is constituted by the first switching means, the second switching means, the operational amplifying means and the electrostatic capacitance element, so that the amplifying operation can be performed with a simple circuit configuration. Before this, the threshold voltage of each MOS transistor can be easily adjusted in a short time, and the offset voltage can be made very small.

(3) Further, in the present invention, since the MOS transistor to which the offset adjusting voltage is applied to the substrate bias portion is formed by the SOI structure, the threshold voltage of the MOS transistor is adjusted more accurately. be able to.

(4) According to the present invention, the offset adjusting means can be constructed at a low cost by using the MOS transistors as the first switching means and the second switching means, and the layout area of the semiconductor element can be reduced. .

(5) Further, in the present invention, the above (1) to
By (4), the common mode rejection ratio (CMRR) caused by the offset voltage of the amplifier circuit can be significantly improved, and the amplifier circuit with low distortion can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a differential amplifier circuit provided with an offset voltage adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a structural cross-sectional view of a MOS transistor used in a differential amplifier circuit according to an embodiment of the present invention.

[Explanation of symbols]

1 Amplifier Circuit 2 MOS Transistor 3 MOS Transistor 3a Semiconductor Substrate 3b Insulating Layer 3c Well (Silicon Single Crystal Thin Film) 3d to 3g Insulating Layer 3h Wiring 3i, 3j Insulating Layer 4 Resistor 5 Resistor 6 MOS Transistor (First Switching Means) 7 MOS transistor (second switching means) 8 MOS transistor (second switching means) 9 Operational amplifier (operational amplification means) 10 Capacitor (capacitance element) OC1 Offset voltage adjustment circuit (offset voltage adjustment means) KB1 Substrate bias section Vcc Power supply Vss Ground potential In1 input part In2 input part Out1 output part Out2 output part G1 to G5 gates D1 to D5 drains S1 to S5 sources

Claims (4)

[Claims] 1. A semiconductor integrated circuit device in which an amplification circuit is configured using MOS transistors, wherein an offset adjustment voltage for adjusting an offset voltage is applied to a substrate bias portion of a predetermined MOS transistor in the amplification circuit. A semiconductor integrated circuit device comprising an offset voltage adjusting means. 2. The offset voltage adjusting means includes first switching means for short-circuiting the gate portions of the plurality of MOS transistors to which amplified signals are input, and the MOS transistor for outputting the signals amplified by the amplifier circuit. Of the second switching means and the other connecting portion of the second switching means are connected to the input portion, and the output portion is connected to the substrate bias portion of the predetermined MOS transistor. It is characterized by comprising a connected operational amplification means and a capacitance element in which one connection portion is connected to the substrate bias portion of the predetermined MOS transistor and the other connection portion is connected to the ground potential. Item 2. The semiconductor integrated circuit device according to item 1. 3. The semiconductor integrated device according to claim 1, wherein the predetermined MOS transistor has an SOI structure in which a silicon single crystal thin film is formed on an insulating layer and a semiconductor element is formed thereon. Circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the first switching means and the second switching means are MOS transistors.