JPH08124873A - Contact hole forming method - Google Patents

Abstract

PURPOSE: To avoid overcutting the surface of a lower conductive layer or impurity-diffused layer by ion implantation of an impurity so as to reach the bottom of a first contact hole, thereby speeding up the etching of an antireflective film located at the bottom of this hole. CONSTITUTION: A diffusion layer is formed on the surface of a base substrate, facing at a second contact hole 20 which pierces an antireflective film 12. While this film still remains at the bottom of a first contact hole 18 formed on a conductive layer such as gate electrode 10, the ion implantation is made and then wet etching such as dilute hydrofluoric acid treatment is applied to suppress etching of the surface of the base substrate and make the hole 18 piercing. The ion implantation has an effect to increase the etching rate of the antireflective film made of SixOyNz, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole used in the process of manufacturing a semiconductor device, and can be used, for example, in manufacturing an integrated semiconductor circuit such as a memory device highly integrated in a fine pattern. The present invention relates to a method for forming a contact hole.

[0002]

2. Description of the Related Art Currently, in the research and development of semiconductor integrated circuits, design rule devices in the sub-half micron region are being researched and developed. The most advanced stepper (reduction projection exposure machine) used in the photolithography technology used in the development of these devices uses KrF excimer laser light (248 nm) as a light source, and
A lens having an NA (numerical aperture) of about 7 to 0.50 is mounted.

A stepper uses light of a single wavelength as an exposure light source. It is widely known that a phenomenon called a standing wave effect occurs when exposure is performed with a single wavelength.
As a result, the amount of light absorbed by the resist changes depending on the resist film thickness. This absorbed light amount becomes energy for photoreacting the resist. Further, the degree of change in the amount of absorbed light varies depending on the type of the base substrate. That is, the degree of change in the absorbed light amount is determined by the complex amplitude reflectance (R) considering the multiple interference determined by the optical constants (n, k) of the base and the optical constants (n, k) of the resist (R is the real part). And indicates that the vector quantity has an imaginary part).

In order to suppress the change in the amount of absorbed light due to the standing wave effect, Si _X is formed on the base material to be processed.
O _Y N _Z film (compound film containing nitrogen, oxygen and silicon)
Alternatively, an antireflection film such as a Si _X N _Y film (a compound film containing nitrogen and silicon) is formed, and on the antireflection film,
A resist patterning technique is used in which a photoresist is spin-coated and exposed by an excimer stepper to form a resist pattern.

By using this resist patterning technique, it is possible to pattern the wiring design rule in the sub-half micron region. A case where a Si _X O _Y N _Z film is used as an antireflection film, a gate electrode is processed, and a contact hole is formed in an interlayer insulating film laminated thereon will be described with reference to FIG. As shown in FIG. 2A, an element isolation region (LOCOS) 4 is formed in a predetermined pattern on the surface of the semiconductor substrate 2, and L
The gate insulating film 8 is formed on the surface of the semiconductor substrate not covered with OCOS by a thermal oxidation method or the like.

After that, the gate insulating film 8 and the LOCOS are formed.
A conductive layer such as a polysilicon layer to be the gate electrode 10 is formed on the substrate 4 by CVD, and a Si _X O _Y N _Z film which is the antireflection film 12 is formed thereon. Then, a resist film is formed by coating on the antireflection film, and the resist film is processed into a pattern of the gate electrode by a photolithography method. At that time, since the standing wave effect is suppressed by the antireflection film 12, fine processing is possible. Then, the conductive layer is etched using the resist film as a mask to obtain the gate electrode 10.

After that, ion implantation for forming the impurity diffusion layers 14 for the source / drain regions is performed on the surface of the semiconductor substrate. Although the resist film may remain on the gate electrode, it may be removed. By this ion implantation, the source / drain region impurity diffusion layers 14 are formed in the surface layer of the semiconductor substrate 2 which is not covered with the gate electrode 10 and the LOCOS 4.

After removing the resist film, the antireflection film 12 is formed.
On the semiconductor substrate on which the gate electrode 10 in which the silicon oxide remains is formed, an interlayer insulating film 16 made of silicon oxide or the like is formed.
Are deposited by CVD or the like. After that, the contact with the specific impurity diffusion layer 14 is made and the specific gate electrode 1 is formed.
In order to make contact with 0, the interlayer insulating film 16 is
First contact hole 18 and second contact hole 20
To form. In order to form these contact holes 18 and 20, first, as shown in FIG. 2A, the impurity diffusion layer 14 is formed at the bottom of the second contact hole 20.
The etching is controlled so that the etching is stopped when the surface of the substrate is exposed. At that stage, the antireflection film 12 remains on the bottom of the first contact hole 18. This is because Si _X O _Y N forming the antireflection film 12
_This is because the etching rate of the _Z film is lower than the etching rate of the interlayer insulating film 16 made of silicon oxide or the like.

If the antireflection film 12 remains on the bottom of the first contact hole, the gate electrode 10 cannot be connected to the upper wiring through the first contact hole 18. Therefore, it is conceivable to carry out etching for forming the contact holes 18 and 20 until the surface of the gate electrode 10 is exposed.

[0010]

However, the contact holes 18 and 20 are formed until the surface of the gate electrode 10 is exposed.
When the etching process for forming the
As shown in, the surface of the semiconductor substrate 2 located on the surface layer of the semiconductor substrate 2 (the surface of the diffusion layer 14) is dug, and in some cases, the surface may be dug deeper than the thickness of the diffusion layer 14. If the surface of the diffusion layer 14 is dug,
The function as the impurity diffusion layer may be deteriorated, and the electrical connection with the upper conductive layer through the contact hole may be insufficient.

The present invention has been made in view of the above circumstances, and provides a method for forming a contact hole which does not overdue the surface of the lower conductive layer or the impurity diffusion layer and which has good electrical connection through the contact hole. The purpose is to provide.

[0012]

In order to achieve the above object, a method of forming a contact hole according to the present invention comprises a step of depositing a conductive layer on the surface of a base substrate, and a step of reflecting a conductive layer on the conductive layer. A step of depositing an anti-reflection film, a resist film is formed on the anti-reflection film, the resist film is photolithographically processed into a predetermined pattern, and the conductive film is subjected to a predetermined pattern using the resist film having the predetermined pattern as a mask. And the process of etching to remove the resist film,
On the surface of the base substrate on which the conductive layer of a predetermined pattern is formed,
The step of depositing the interlayer insulating film, and the depth of partially removing the antireflection film remaining on the conductive layer, the first contact hole is formed in the interlayer insulating film, and the depth of exposing the surface of the base substrate at the same time. A step of forming a second contact hole in the interlayer insulating film, and a step of forming a second contact hole in the first contact hole in order to increase the etching rate of the antireflection film located in the bottom of the first contact hole. The method includes a step of implanting impurities, and a step of removing the antireflection film on the inner bottom of the first contact hole.

The base substrate is, for example, a semiconductor substrate. The conductive layer is formed on the surface of the semiconductor substrate via a gate insulating film, the conductive layer is etched into a predetermined pattern to form a gate electrode, and ion implantation is performed in self-alignment with the gate electrode. By doing
An impurity diffusion layer is preferably formed on the surface layer of the semiconductor substrate.

It is preferable to use an impurity of the same conductivity type as the impurity contained in the impurity diffusion layer formed on the surface of the semiconductor substrate as an impurity species for ion implantation for increasing the etching rate of the antireflection film. As the antireflection film, a compound including at least film nitrogen and oxygen and silicon (Si _x O _y N _z, if further containing _{hydrogen, Si x O y N z:} H film) is preferably used. As the other antireflection film, Si _x N _y (Si _x N _y : H film when hydrogen is contained) or the like can be used.

In order to remove the antireflection film, it is preferable to use a wet etching process such as a dilute hydrofluoric acid process. In the present invention, the base substrate is not limited to a semiconductor substrate on which a diffusion layer is formed, but refers to all substrates on which a lower conductive layer or a diffusion layer for forming some electrical connection with an upper wiring layer is formed. To do.

[0016]

In the method of forming a contact hole according to the present invention, the second surface facing the surface of the underlying substrate on which the diffusion layer is formed.
Although the contact hole penetrates, ion implantation is performed in a state where the antireflection film remains at the bottom of the first contact hole formed on the conductive layer such as the gate electrode. Next, wet etching such as dilute hydrofluoric acid treatment is performed to suppress etching of the surface of the underlying substrate on which the diffusion layer and the like are formed, and also to penetrate the first contact hole on the conductive layer such as the gate electrode. be able to. The ion implantation brings about an effect of increasing the etching rate of the antireflection film made of Si _x O _y N _z or the like.

In the wet etching, the surface of a base substrate (for example, a semiconductor substrate) on which a diffusion layer is formed is hardly etched, and an antireflection film made of Si _x O _y N _z or SiO ₂ is used. The interlayer insulating film to be etched can be etched. Since the interlayer insulating film itself is also etched while removing the antireflection film remaining on the conductive layer such as the gate electrode by wet etching, it is necessary to increase the etching rate of the antireflection film as much as possible. Therefore, ion implantation is effective. In addition, the ion implantation at this time also serves to expand the margin of the diffusion layer region by using an ion species capable of forming a layer of the same type as the impurity diffusion layer.

According to the present invention, gate electrode patterning
Si as an antireflection film for_xO_yN _zDevice using
In the structure, contact holes on the gate electrode and on the diffusion
In the process of forming the contact hole, the diffusion layer
Suppression of contact and contact with the gate electrode
Holes can also be formed. 0.25 μm generation and later
It has an effect on the formation of integrated circuits of the next generation.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. 1 (A) to 1 (C) are schematic cross-sectional views of a main part showing a method of forming a contact hole according to an embodiment of the present invention.

In the present embodiment, a case will be described in which an N-channel MOS transistor is formed on the surface of a semiconductor substrate as a base substrate, and a contact hole facing the gate electrode of the MOS transistor and the diffusion layer of the semiconductor substrate is formed. To do. First, as shown in FIG. 1A, an element isolation region (LOC) is formed in a predetermined pattern on the surface of the semiconductor substrate 2.
OS) 4 is formed, and the gate insulating film 8 is formed on the surface of the semiconductor substrate which is not covered with LOCOS. As the semiconductor substrate, a P-type single crystal silicon wafer or an N-type single crystal silicon wafer having a P well formed on the surface thereof is used. The LOCOS 4 is formed by a selective oxidation method using a silicon nitride film as an oxidation prevention film. The gate insulating film 8 is formed by thermally oxidizing the surface of the semiconductor substrate, and is made of a silicon oxide film or the like.

After that, the gate insulating film 8 and the LOCOS are formed.
A conductive layer to be the gate electrode 10 is deposited on the surface of the electrode 4. As the conductive layer, a polysilicon layer, or a polysilicon layer and a silicide layer (for example, tungsten silicide)
And a polycide film which is a laminated film of
It is deposited by means such as. The polysilicon layer is preferably doped with impurities such as phosphorus in order to enhance conductivity.

Next, a Si _X O _Y N _Z film which is the antireflection film 12 is formed on the conductive layer. Si _X O _Y N at this time
_When the conductive layer is a polycide film containing WSi _x , the _Z film has a refractive index n = 2.1 so that an antireflection effect (suppressing the standing wave effect) can be obtained for this WSi _x .
2, the absorption coefficient k = 0.60, and the film thickness d = 29 nm may be used under the formation conditions shown in Table 1 below.

[0023]

[Table 1] Device: Single plate parallel plate plasma CVD SiH ₄ ; 50 sccm N ₂ O; 50 sccm pressure; 333 Pa (2.5 Torr) RF power; 190 W electrode spacing; 1 cm Next, on the antireflection film 12, a resist film is formed. To form K
The resist film is patterned with the pattern of the gate electrode by the photolithography technique using the rF excimer laser. At that time, since the standing wave effect is suppressed by the antireflection film 12, fine processing is possible. Then, using the resist film as a mask, the conductive layer is etched by means such as RIE (reactive ion etching),
The gate electrode 10 is obtained.

Next, ion implantation is performed on the surface of the semiconductor substrate 2 to form the source / drain region impurity diffusion layers 14. The resist film may remain on the gate electrode 10 or may be removed. By this ion implantation and the subsequent activation annealing treatment, the gate electrode 1
The source / drain region impurity diffusion layers 14 are formed in the surface layer of the semiconductor substrate 2 which is not covered with 0 and LOCOS 4.

After removing the resist film, the antireflection film 12 is formed.
On the semiconductor substrate 2 on which the gate electrode 10 on which the silicon oxide remains is formed, the interlayer insulating film 1 made of silicon oxide or the like.
6 is deposited by CVD or the like. After that, a first contact hole 18 and a second contact hole 20 are formed in the interlayer insulating film 16 in order to make a contact with the specific impurity diffusion layer 14 and a contact with the specific gate electrode 10. . These contact holes 18, 20
1A, first, as shown in FIG. 1A, etching is performed so that the etching is stopped at the stage where the surface of the impurity diffusion layer 14 is exposed at the bottom of the second contact hole 20. . At that stage, the antireflection film 12 remains on the bottom of the first contact hole 18. This is because Si _X O forming the antireflection film 12
The etching rate of the _Y N _Z film is smaller than the etching rate of the interlayer insulating film 16 made of such as silicon oxide.

Next, as shown in FIG.
The entire surface of the interlayer insulating film 16 on which the through holes 18 and 20 are formed
Ion implantation is performed. Where n⁺Conductivity type impurities
As an ion species of the same type as the diffusion layer 14, P (re
The dose is 5 × 10 ^Fifteen/ Cm² , Energy
Inject at 60 keV. Of the same conductivity type as this diffusion layer 14.
By performing impurity ion implantation, the second contact hole
At the bottom of the module 20, the same conductivity type as the impurity diffusion layer 14 is formed.
The impurities will be driven in again. As a result, the second
The diffusion layer 14 located at the bottom of the contact hole 20
The impurity concentration of the contact portion 22 increases,
The resistance can be lowered and the margin of the diffusion layer area can be reduced.
It can also be expanded. Note that p⁺When you want to form a diffusion layer
Is BF ₂ The dose amount is 5 × 10^Fifteen/ Cm² , Energy
It may be injected at -60 keV.

Next, as shown in FIG. 1C, HF: H
Wet etching is performed using dilute hydrofluoric acid of ₂ O = 1: 200 until the antireflection film 12 on the gate electrode 10 located at the bottom of the first contact hole 18 is removed.
Dilute hydrofluoric acid is Si (silicon) on the surface of the semiconductor substrate.
Is not etched, the diffusion layer 14 is not etched.

As described above, both the second contact hole on the diffusion layer 14 and the first contact hole on the gate electrode 10 can be favorably formed simultaneously without etching the diffusion layer 14. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways within the scope of the present invention.

For example, in the above embodiment, the case where the contact hole facing the surface of the semiconductor substrate and the contact hole facing the surface of the gate electrode are formed at the same time has been described, but the present invention is not limited to this. For example,
The method of the present invention is also applied to the case where the contact holes are simultaneously formed on the surface of the lower conductive layer (concept including the conductive region) and the upper conductive layer located above the lower conductive layer. can do.

[0030]

As described above, according to the present invention, when patterning a conductive layer such as a gate electrode, Si
_A device structure using an antireflection film such as _x O _y N _z ,
In the process of forming contact holes on a conductive layer such as a gate electrode and contact holes on a base substrate such as a semiconductor substrate on which a diffusion layer is formed, the etching of the surface of the base substrate on which the diffusion layer is formed is suppressed. In addition, a contact hole can be formed for achieving good connection with a conductive layer such as a gate electrode. Use of the method of the present invention is effective in forming integrated circuits of the 0.25 μm generation and the subsequent generations.

[Brief description of drawings]

1A to 1C are schematic cross-sectional views of a method of forming a contact hole according to an embodiment of the present invention.

FIGS. 2A and 2B are schematic cross-sectional views showing a method of forming a contact hole according to a conventional example.

[Explanation of symbols]

 2 ... Semiconductor substrate 4 ... LOCOS 8 ... Gate insulating film 10 ... Gate electrode 12 ... Antireflection film 14 ... Impurity diffusion layer 16 ... Interlayer insulating film 18 ... First contact hole 20 ... Second contact hole

Claims (5)

[Claims] 1. A step of depositing a conductive layer on the surface of a base substrate, a step of depositing an antireflection film on the conductive layer, and a step of forming a resist film on the antireflection film. The resist film is photolithographically processed into a predetermined pattern, the conductive film is etched into a predetermined pattern using the resist film having the predetermined pattern as a mask, and the resist film is removed to form a conductive layer having a predetermined pattern. A step of depositing an interlayer insulating film on the surface of the base substrate, and a step of forming a first contact hole in the interlayer insulating film to a depth at which the antireflection film remaining on the conductive layer is partially removed, Forming a second contact hole in the interlayer insulating film to a depth at which the surface is exposed; and increasing the etching rate of the antireflection film located at the bottom of the first contact hole. In order to achieve this, a method of forming a contact hole, including a step of ion-implanting impurities so as to enter the bottom of the first contact hole, and then removing the antireflection film at the bottom of the first contact hole. . 2. The base substrate is a semiconductor substrate, and the conductive layer is formed on the surface of the semiconductor substrate via a gate insulating film, and the conductive layer is etched into a predetermined pattern to form a gate electrode. The method of forming a contact hole according to claim 1, wherein the impurity diffusion layer is formed in the surface layer of the semiconductor substrate by performing ion implantation in self-alignment with respect to the gate electrode. 3. An impurity of the same conductivity type as an impurity contained in an impurity diffusion layer formed on the surface of the semiconductor substrate is used as an impurity species of ion implantation for increasing the etching rate of the antireflection film. 2. The method for forming a contact hole according to 2. 4. The method of forming a contact hole according to claim 1, wherein a compound film containing at least nitrogen, oxygen and silicon is used as the antireflection film. 5. The method for forming a contact hole according to claim 1, wherein a dilute hydrofluoric acid treatment is used to remove the antireflection film.