JPH08123943A - Signal processor - Google Patents

Abstract

PURPOSE: To share a single memory among various processings by performing the optimum address control adapted to the processing form in each processing block at the time of access to the single memory from plural processing blocks. CONSTITUTION: A picture data input/output block 1, an audio processing block 2, an encoding/decoding block 3, an error correction block 4, and an encoded data input/output block 5 transmit and receive data to and from an external memory 8 through an address conversion circuit 6 and a memory interface 7. Each port of an address generation circuit generates and outputs the address corresponding to unit data in the form most suitable for the data form handled in each processing block and the address space of the memory 7 based on data for address generation supplied from each block. The address conversion circuit 6 switches the reset timing of a counter or the like based on parameter data to adaptively assign the addresses in accordance with the classification of an input picture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for performing processing such as coding and decoding of various data, especially image data.

[0002]

2. Description of the Related Art Conventionally, various devices have been developed for encoding a huge amount of various data so as to reduce the data amount so that data can be transmitted at a relatively low transmission rate.

For example, even a digital VTR for recording image data on a recording medium such as a magnetic tape has a capacity of 124 MBp.
A standard has been established for compressing input image data of about s to about 1/5 of 25 MBps, recording it on a magnetic tape, and reproducing it.

In a digital VTR based on such a standard, input data is DCT-converted and then quantized,
Data is compressed by variable-length coding this quantized data, and the quantization step when quantizing is changed based on various parameters, or the amount of data after variable-length coding The rate is controlled so that is constant.

Also, the input image data is compressed by using predictive coding with inter-frame (field) motion compensation, and this predictive image data is further compressed by using the above DCT, quantization and variable length coding. Is being established, and a CD-ROM compatible with this standard is being established.
Various types of devices have also been developed.

[0006]

In the encoding / decoding device in each of the above-mentioned various devices, a plurality of independent memories are used.

That is, for example, in the case of a digital VTR,
A video memory for temporarily storing the input image data and a track memory for storing the encoded data after the encoding process before recording are required. Conventionally, these memories are individually provided. It was

Further, in the apparatus based on the MPEG standard, a plurality of independent memories such as an input buffer and a reference buffer for motion compensation are provided.

However, in the case where a plurality of memories are individually provided and controlled independently of each other, the cost is increased as a whole.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a signal processing device capable of cost reduction.

In order to achieve such an object, the present invention provides a plurality of processing means for performing various kinds of processing different from each other, a memory means provided in common to each processing means, each processing means and a memory means. And a control means for performing access control between the control means and the control means, the control means performing address control in different units according to the processing means.

Further, in order to achieve the above-mentioned object, the present invention provides a plurality of processing means for performing various processings different from each other, a memory means commonly provided for each processing means, and each processing means. And a memory means for controlling access between the memory means and the memory means, wherein the control means prioritizes access to data having a high processing priority and executes each processing in a time division manner. , Is provided.

Further, according to the present invention, in order to achieve the above-mentioned object, a plurality of processing means for performing various kinds of processing different from each other, a memory means provided in common to each processing means, and a plurality of types of processing means. The control means includes means for setting parameters according to the data to be processed, and control means for performing address control between the processing means and the memory means. The control means is based on the parameters according to the data. A signal processing device characterized by different address control.

According to the above-mentioned invention, the control means for controlling access between each processing means and the memory means is provided, and the address control is performed by this control means in different units according to each processing means. With this, it is possible to deal with various processes with a single memory.

Further, according to the above-mentioned invention, there is provided a control means for controlling access between each processing means and the memory means, and this control means gives priority to access of data having a high processing priority. By executing the processing in a time-divisional manner, it is possible to perform a speedy processing even when the single memory means is also used for various processing.

Further, according to the above-mentioned invention, there are provided means for setting parameters corresponding to a plurality of types of data to be processed, and control means for performing address control between each processing means and the memory means. The control means can easily cope with various types of data by changing the address control based on the parameters corresponding to the respective data.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of this embodiment. This embodiment applies the present invention to a processing circuit for an LSI codec used in a digital VTR.

(Overall Structure) In this embodiment, as shown in FIG. 1, two systems of processing units A and B arranged in parallel and predetermined data according to the kind of input data are time-divided into the above processing units. Each of the processing units is composed of the above-mentioned LSI.
Each of them is composed of a computerized processing circuit and a memory.

Further, each processing unit in this embodiment can perform real-time processing of SD-compatible image data and audio data. In this embodiment, such processing units are arranged in parallel and each processing circuit is connected to each other. By supplying image data and audio data in a divided manner for processing, it is possible to process in real time HD-compatible image data and audio data whose data amount per frame is double that of the SD image data. It is configured.

Each processing circuit in the above processing unit is
As shown in FIG. 1, the image data input / output block 1, the audio processing block 2, the encoding / decoding block 3, the error correction block 4, and the encoded data input / output block 5 are roughly configured, and each of these blocks is an address. Data is exchanged with the external memory 8 via the conversion circuit 6 and the memory interface 7.

The operation of these processing circuits is controlled by supplying predetermined commands from the external microcomputer 10 to the above blocks through the CPU interface 9 and the internal system bus SB1 and the external microcomputer 10 controls the external system bus SB2. The data interface is controlled via the above to cause the processing units arranged in parallel to perform time division processing.

As the memory 8 in this embodiment, an SDRAM (Synchronous-DRAM) capable of performing burst transfer of data and address in synchronization with the rising edge of a clock is used, and this SDRAM is shown in FIG. 2 (A). As described above, the memory arrays M1 and M2 of two systems, the clock buffer 81 which is selectively supplied with one of the reference clocks CL1, CL2, CL3 and CL4, and outputs a clock based on a control signal from a memory controller described later. Mode controller 82 for alternately setting the read / write mode of each memory array, and the address conversion circuit 6
It comprises an address controller 83 for designating an address in the memory array based on address data supplied from, a shift register 84 for performing serial-parallel conversion, and an input / output buffer memory 85.

Further, each of the memory arrays M1 and M2 in the memory 8 is a memory cell (DRAM) 86.
A, 86B and sense amplifiers 87A, 87B provided independently of these memory cells, respectively,
By performing a burst transfer of a predetermined amount of data held in these sense amplifiers in synchronization with a clock, the transfer rate with the outside of the memory and the operating speed within the internal bank can be set independently, and overall high-speed read / write Is possible.

Further, the sense amplifiers 87A and 87B in this embodiment are 8 × 64 as shown in FIG. 2 (B).
It has a capacity of (8 × 8) pixels and is capable of burst transfer in units of 8 pixels.

Each memory space of the memory cells 86A and 86B in the memory 8 has a capacity for storing one frame of coded data like a video memory (VM) area having a capacity of one frame. The memory cells in each area are alternately set to a write mode and a read mode for each frame, and each processing block described above depends on its processing mode. The above sense amplifier 8
Data is exchanged with the VM area or the TM area via 7A and 87B.

That is, as shown in FIG. 3, the image data input / output block 1 exclusively exchanges data with the VM area, and the encoding / decoding block 3 receives data both in the VM area and the TM area. By transmitting and receiving, the data is read from the VM area during the encoding operation, encoded and then written into the TM area, and the data is read from the TM area and decoded and then written into the VM area during the decoding operation.

Similarly, the audio processing block 2,
Error correction block 4 and coded data input / output block 5
Exchanges data exclusively with the TM area.

The address space in each of the above areas is constructed as shown in FIG.

That is, the image data (Y, Cr, Cb) before being encoded is written in the VM area in pixel units, and this image data (horizontal 720 pixels × vertical 4 pixels per frame) is written.
(80 pixels) are distributed to 50 super macro blocks (SMB) of 5 blocks in the horizontal direction × 10 blocks in the vertical direction, and each super macro block is composed of a luminance data 4 DCT block and a color difference data 1 DCT block. ) Are collected in 27 blocks.

Each DCT block is composed of 8 × 8 pixels.

Further, the image data of one frame having the number of pixels as described above is recorded over 10 tracks on the magnetic tape after being encoded, but the image data before encoding is as described above. The data of 5 super macro blocks aligned in the horizontal direction correspond to one track.

Therefore, as an address for accessing this VM area, h and v corresponding to the horizontal and vertical directions of each pixel, track number Tr, and super macro block number (SMB) in each track are used. , The macroblock number (M
B), DCT block number (D
It is preferable to use CT).

On the other hand, in the TM area, the coded image data, audio data, error correction code, etc. are distributed and stored in the above-mentioned 10 tracks, and 148 are stored in the area corresponding to each track. Sync block (S
B) is stored.

Each sync block is composed of sync data (sync), ID data (ID), audio data, image data and parity, and the image data and audio data of each sync block correspond to a symbol.

Therefore, it is preferable to use the track number Tr, the sync block number (SB) in each track, and the symbol number (Symbol) in each sync block as an address when accessing the TM area.

The access of each processing block to the memory 8 as described above is arbitrated and controlled by the memory controller 11, and the address control is controlled by the address conversion circuit 6.

That is, a command for designating the type of various operation modes such as the reproduction mode or the recording mode from the external microcomputer (CPU) 10 connected to the memory controller 11 via the CPU interface 9 via the bus SB3. Is transmitted to the memory controller 11
Performs scheduling related to the priority of data transfer in accordance with this command, and arbitrates data transfer between each processing block and the memory 8 in response to a request transmitted from each processing block via the bus SB3. To do.

The command is output by the CPU 10 reading the operation mode set by the operation switch SW. For example, the encoding (recording) mode, the decoding (reproduction) mode, or the special reproduction in the VTR. It corresponds to various operation modes such as modes.

The operation mode designated by the above command is not limited to the above, but includes various operations such as editing such as image composition and dubbing.

The address generating circuit 6 generates a predetermined address, which will be described later, for each processing block so that addressing can be performed in an optimum data unit according to the processing mode in each processing block and the address space of the memory 8. A predetermined address is generated on the basis of various address data transmitted from each of the processing blocks and having an optimal address form according to the form of processing.

Further, the address generating operation in the address generating circuit 12 is variably set based on the parameter corresponding to the image type transmitted from the CPU 10, and for example, the image to be processed is SD or HD.
Or a different address is generated depending on the image type (size) such as NTSC or PAL.

On the other hand, each unit of each processing circuit operates in synchronization with four kinds of clocks output from the clock generator 12.

The clock generator 12 is supplied to the image data input / output block 1 on the basis of the synchronizing signals H.sync, V.sync and the internal reference clock extracted from the input signal and synchronized with the input signal. The first clock CL1 (13.5 MHz in this embodiment), the audio processing block 2
Second for processing audio data supplied to the
Clock CL2 (48 KHz in the present embodiment), which is supplied to the encoding / decoding block 3, the error correction block 4 and the memory 7 to perform the encoding / decoding process, the error correction process and the read / write to the memory. High-speed third clock CL3 (67.5 MHz in this embodiment), and a fourth clock CL4 (in this embodiment, which is supplied to the encoded data input / output block 5 to perform recording / reproduction on a recording medium. 41.85
MHz) is generated and supplied to each block, and each processing block performs a processing operation at a speed according to the supplied clock.

Each circuit of the above processing circuit will be described in detail below.

(Processing Block Configuration) The configuration of each block will be described below.

First, the image data input / output block 1
Is an A / D converter 101, a D / A converter 102, a video interface 103, a finder interface 10
4, character generator 105, reference signal generator 1
06 and address data and an address generation circuit 107 for generating various data relating to address control.

The A / D converter 101 digitizes the SD compatible luminance signal Y and color difference signals Cr, Cb or the HD compatible luminance signal Y and color difference signals Cr, Cb. The luminance signal is 13.5 MHz. Alternatively, the color difference signals Cr and Cb are digitized at a predetermined cycle synchronized with 40.5 MHz, and the color difference signals Cr and Cb are digitized at a cycle of 1/4 and output as 8-bit data.

These frequencies are variably set according to the type of input signal.

The reference signal generator 106 extracts and outputs the synchronizing signals H.sync and V.sync in the input video signal.

The address generation circuit 107 has a 1/8 frequency divider 1071 connected in series with each other as shown in FIG.
1/720 frequency divider 1072, 1/480 frequency divider 1073
And a 1/2 divider 1074, which divides the clock CL1 supplied from the clock generating circuit 12 by these dividers to generate horizontal and vertical address generation data h, v, and outputs the signal Fr indicating the switching timing of the write mode / read mode for each one frame to the address generation circuit 6.

Although the address generation circuit 107 outputs the address data for the luminance data, the address generation circuit for the color data in this embodiment which handles the 4: 1: 1 component signals is the same as the address generation circuit 107. The above clock CL is placed before the similar frequency divider.
It is configured by including a 1/4 frequency divider that divides 1 by 1/4.

Further, the video interface 103 outputs the data Y, Pr, Pb indicating the luminance signal and the two color difference signals which are input / output in a time division manner to the address generation circuit 10.
7

Further, the output of the ⅛ frequency divider 1071 is supplied to the request generator 1075, and the request req1 synchronized with this frequency division output is output.

As described above, the image data input / output block 1 receives the input video signal and outputs predetermined video data, and at the same time, outputs the address data h, v and the related data Y, Pb, Pr, Fr. The request req1 that requests access to the memory 8 is output to the memory controller 11 while being output to the address conversion circuit 6.

Next, the audio processing block 2 will be described.

This audio processing block 2 is an A / D
It is composed of a converter 201, a D / A converter 202, an audio digital processor (DSP) 203, and an address generating circuit 204. The A / D converter 201 receives an input audio signal according to a predetermined mode. 48K
Hz or 32 KHz sampled and digitized with 16 bits to obtain 2 ch of digital audio data, or 32 KHz sampled with 12 bits to be digitized (non-linear) to obtain 4 ch of digital audio data, and The digital processor 203 performs emphasis processing and converts the digitized sample data into byte (symbol) units.

The audio data thus obtained is transferred to and written in the memory 7 at a predetermined timing via the data bus.

Further, in this embodiment, the symbol (A-Sy) generated by the address generating circuit 204 is generated.
(mbol) is output to the address conversion circuit 6 as address data in the audio data, and the request req5 is output to the memory controller 11.

As described above, the audio processing block 2 converts the input audio signal into digital audio data in a symbol unit according to a predetermined mode, and the symbol is supplied to the address generating circuit 6 as address generating data. Then, the request req5 requesting access to the memory 8 is output to the memory controller 11.

Next, the encoding / decoding block 3 will be described.

This encoding / decoding block 3 is a DCT
The conversion circuit 301 performs conversion or inverse DCT conversion, the quantization circuit 302 performs quantization or inverse quantization, the encoding / decoding circuit 303 performs variable length encoding or variable length decoding, and the address generating circuit 304. In addition, a motion detection circuit 305 for determining the DCT conversion mode (8 × 8 pixel conversion mode or 8 × 4 × 2 pixel conversion mode) in the conversion circuit 301, and an activity calculation circuit for determining the class of the quantization step. 306 and the quantization circuit 30
A code amount control circuit 307 for determining the quantization step in 2 and controlling the code amount is provided.

Here, in the encoding / decoding block 3 as described above, when performing the processing in each of the above circuits, D
The unit of processing is a unit such as a CT block, a macro block, or a super block.

Therefore, the address generation circuit 304 in the encoding / decoding block 3 outputs the unit data as address data.

In the digital VTR, NTS
In the case of the C method, image data for one frame is recorded on 10 tracks (12 tracks in the case of PAL), and data for 5 super blocks is assigned to each track.

Therefore, the address generation circuit 304 of the encoding / decoding block 3 in this embodiment also supplies the super block number Trk in each track to the address generation circuit as address generation data.

The address generation circuit 304 for outputting each data is 1/64 frequency divider 304 as shown in FIG.
It is roughly composed of a 1/4 divider 3042, a 1/5 divider 3043, a 1/27 divider 3044 and a 1/10 divider 3045, and these dividers generate the clock. The clock CL3 supplied from the circuit 12 is frequency-divided and data indicating the unit of such processing is supplied to the address conversion circuit 6 as address data in the encoding / decoding block 3.

The output of the 1/64 frequency divider 3041 is supplied to the request generator 3046, and the request req4 synchronized with this frequency division output is output.

The encoding / decoding block 3 is
Data indicating whether the encoding operation (recording operation) or the decoding operation (reproduction operation) is performed is output as address generation data.

Encoding / decoding block 3 as described above
Encodes or decodes the processed image data supplied via the memory 8 and outputs the processed image data, supplies the above-mentioned various address generation data to the address conversion circuit 6, and stores the memory at a predetermined timing. A request req4 requesting access to the memory 8 is output to the controller 11.

Next, the structure of the error correction block 4 will be described.

This error correction block 4 is an error correction circuit 4
01, a syndrome memory 402, and an address generation circuit 403. The error correction block 4 adds an error correction code to the coded data generated in the preceding encoding / decoding block 3 and audio processing block 2. Then, while returning to the memory 8, the error correction code in the reproduced data is detected and error correction is performed.

Further, the address generation circuit 403 in the error correction block 4 has a 1/8 frequency divider 4031, a 1/10 frequency divider 4032, a 1/148 frequency divider 4033 and a 1/10 as shown in FIG. The clock generator circuit 12 is roughly composed of a frequency divider 4034.
The clock CL3 supplied from the above is divided, and the symbol data indicating the symbol number in each track, the macroblock number SB in the super macroblock and the superblock number Trk in the track are supplied to the address generation circuit 6. , 1/8 frequency divider 40
The output of 31 is supplied to the request generator 4035, and the request req3 for requesting the memory controller 8 to access the memory 8 is generated and output.

The error correction circuit 401 can be connected to an external device through the dubbing interface 404, and supplies, for example, error-corrected data or error-corrected interpolated data to an external device. It is like this.

Next, the structure of the encoded data input / output block 5 will be described.

The coded data input / output block 5 includes an A / D converter 502 for digitizing an analog signal supplied via a recording / reproducing processing circuit 501, an analog processing section 503 such as a recording / reproducing amplifier, and address data. The address generating circuit 504 outputs

The recording / reproducing processing circuit 501 has a modulating circuit for suppressing the direct current component of the encoded data so as to have a form suitable for magnetic recording, and a modulating circuit for modulating so as to obtain a spectrum component for tracking, and a waveform at the time of reproducing. It is configured to include various functional circuits such as an equivalent circuit, a PLL circuit, a digital demodulation circuit, a tracking control circuit, and an address generation circuit 504. The clock CL4 is output as the output of the PLL circuit to output the A / D converter. 502 is supplied.

The address generation circuit 504 of the encoded data input / output block 5 has a 1/8 frequency divider 5041, a 1/10 frequency divider 5042, a 1/148 frequency divider 5043 and 1 as shown in FIG. / 10 frequency divider 5044, which divides the clock CL4 by these frequency dividers and uses it as the address generation data as the above-mentioned error correction block 4 such as the symbol data and sync block number. And the track number Trk are supplied to the address conversion circuit 6, and the output of the 1/8 frequency divider 5041 is supplied to the request generator 5045 to request the memory controller 11 to access the memory 8. req2 is generated and output.

Each block of the signal processing circuit as described above selectively performs a predetermined recording operation, reproduction operation or special reproduction operation in response to a command from the external CPU 10 transmitted via the CPU interface 9.

Further, the CPU interface 9 sends and receives subcode data to and from the memory 8 via the subcode buffer 13, and the data relating to the subcode is sent to the address conversion circuit 6 as address data. A request req2 that is supplied and requests access to the memory 8 is output to the memory controller 11 at a predetermined timing.

(Address Control) The address control in this embodiment is for converting the address data supplied from the address generating circuit of each processing block into a predetermined address corresponding to each memory area in the above-mentioned memory 8. This is performed by the address conversion circuit 6.

As shown in FIG. 9, the address conversion circuit 6 receives the address data from each processing block and the parameter data, command, etc. supplied from the CPU interface 9, and accesses the data and each processing block. A plurality of conversion ports 121, 1 for outputting data for each predetermined data unit based on the address space of the memory 8 and addresses for the data.
22, 123, 124, 125, 126 and the data Data and the address Address output from each port.
Is provided with a multiplexer 127 and a latch circuit 128 for selectively supplying to the memory 8 and each conversion port has a buffer memory BM for outputting input data at a predetermined timing.

Further, each of the conversion ports is provided with a counter Count for counting the address data transferred from each of the processing blocks, and these counters count each of the supplied address data to optimize each processing block. Convert to form address and output.

That is, the conversion port 121 that handles the data from the image data input / output block 1 receives the address data h, Y, Pb, Pr for each of the Y, Pb, and Pr based on the supplied control data.
Counting v, allocating an address for every 8 pixels in the horizontal direction, updating this in frame units designated by Fr, and writing mode and reading of two memory cells for each frame designated by Fr. Set mode and alternately.

The memory 8 has the above-mentioned conversion port 1
The image data and the address output by 21 are received via the multiplexer 127, and this image data is written into a predetermined memory cell on the memory 8 designated by the address.

When the image data is read / written to / from the memory 8, the conversion port 121 transmits / receives data in units of 8 pixels which is a unit capable of burst transfer by the sense amplifier 82 of the memory 8. In this embodiment, the sense amplifier 82 can perform high-speed read / write by performing addressing in units of 8 pixels capable of burst transfer.

Further, in the present embodiment, the capacity of the sense amplifier 82 is set to 8 × 8 × 8 pixels, so that not only the horizontal 8 pixels but also the vertical 8 pixels in the processing of the DCT block unit of 8 × 8 pixels. High-speed read / write is possible.

Similarly, the address generation circuit 6 counts the address generation data transmitted from each block according to the data unit exchanged between the other processing block and the memory 8 and corresponds to each block. Specify the address.

That is, when data is exchanged between the audio processing block and the memory 8, the number of symbols is counted to generate an address in symbol unit, and the encoding / decoding block 3 and the memory 8 are connected to each other. When data is exchanged between the memory 8 and the memory 8, the address is generated based on the macro block, the super macro block, and the track number, and the error correction block 4 or the coded data input / output block 5 and the memory 8 are exchanged. When data is exchanged, an address is generated based on the symbol, super macro block and track number.

Specifically, the conversion port 122 corresponding to the audio processing block 2 has the address generation data Symbol output from the audio processing block 2.
And parameter data, and outputs audio data based on the data in symbol units, writes the data in the memory 8, and exchanges audio data with the memory 8 in symbol units.

Also, the encoding / decoding block 3 is
The macro block number SMB in the super block, the DCT block number MB in each macro block, the super block number Trk in each track, and the encoding operation (recording operation) that are encoding / decoding processing are decoded. The operation data R / P indicating whether the data conversion operation (operation during reproduction) is being performed is output, and the codec port 123 exchanges data in data units based on the address generation data and the parameter data.

Similarly, the above subcode port 12
4. Error correction port 125 and recording / reproducing port 126
Generates predetermined address data based on the address generation data and the parameter data supplied from the error correction block 4, the coded data input / output block 5 and the subcode buffer.

As described above, each port of this address generation circuit is optimal for the format of the data handled by each processing block and the address space of the memory 7, based on each address generation data supplied from each block. An address corresponding to the form unit data is generated and output.

The address conversion circuit 6 adaptively allocates addresses according to the type of the input image by switching the reset timing of the counter Count based on the parameter data.

That is, the parameter data specifies the type (system) of the input video signal, and the address generation circuit determines whether the input video signal is SD compatible or HD compatible.
Alternatively, the control of the counter is switched so as to adapt to the image size and frame period of each system depending on the NTSC signal or the PAL signal.

As a result, the address conversion circuit 6 can perform addressing suitable for the type of the input video signal by designating the parameter data.

(Arbitration by Memory Controller 8) Arbitration and scheduling in this embodiment are performed by the memory controller 11.

The memory controller 11 has a function of arbitrating the access sequence to the memory 8 for each of the above-mentioned processing blocks and further scheduling access priorities according to the operation mode.
These will be described below.

First, an external microcomputer (CP) connected to the memory controller 11 through the CPU interface 9 and a request is transmitted from the blocks through the request bus SB3 to the memory controller 11.
U) Various commands and parameter data are transmitted from U) to arbitrate access between each block and the memory 8.

The arbitration operation by the memory controller 11 assigns the access to the memory 8 of each block according to a predetermined priority and adjusts the waiting time in the buffer memory BF in each processing block in the address conversion circuit 6. This is done by preventing collisions on the bus by doing so.

The case of recording such an arbitration operation will be described below.

As described above, the arbitration operation during recording has the memory 8 for writing the input data into the memory 8 and recording the coded data which has been coded as the above-mentioned priority in the coding (recording) mode. Read out, access to the memory 8 during error correction, access to the memory 8 during encoding processing, writing and reading of audio data to the memory 8, and access to the memory 8 during subcode data processing. Has been done.

Therefore, as shown in FIG. 10, the input data is written in the memory 8 by the request req from the image data input / output block 1 to the memory controller 11.
In response to 1, the permission signal ack is returned, and the memory 8 of the input data transmits the image data of a predetermined unit according to the permission signal, and the memory controller 11 designates a predetermined address to the memory 8 of the image data. Write.

Subsequently, the encoded data for which the encoding processing has been completed is requested by the request re from the encoded data input / output block.
It is read from the memory 8 according to the permission signal corresponding to q2, and the permission signal is output after the reading of the image data into the memory 8 is completed.

In the periods other than the access to the memory 8 by reading the image data and reading the encoded data as described above (the period shown by the arrow in FIG. 10C), the access for error correction is given priority. To be done.

The error correction block 4 sends the request req3 at a predetermined timing to the memory controller 1.
In response to this request, the memory controller 11 returns a permission signal at an appropriate timing within the period t1 to permit access to the memory 8 and execute error correction.

Further, the encoding block 3 always sends out the request req4 at the timing when a predetermined amount of data required for encoding is accumulated in the memory 8, and the memory controller 11
Allows the access of the coding block 3 to the memory 8 by sending a permission signal at an appropriate timing during the period t2 shown in FIG.

Similarly, the request req5 for writing the audio signal is also constantly transmitted, and the memory controller 11 sends the audio block 2 to the audio block 2 at a predetermined timing within the remaining period (period t3 shown in FIG. 10G). Access is allowed.

The access for processing the subcode signal is the same as the access for processing the audio signal, but since the audio signal processing is prioritized, the access is permitted during the remaining remaining period t4.

As described above, the memory controller 11 in this embodiment arbitrates the memory bus so as to allow access to the memory 8 in accordance with the priority order of each process.

(Scheduling Operation by Memory Controller 11) The memory controller 11 schedules the priority of access to the memory 8 of each processing block according to the command.

Next, the scheduling operation by the memory controller 11 will be described.

In the present embodiment, the memory controller 11 has a recording mode set by the operation switch,
Access to the memory 8 of each block is arbitrated in a predetermined priority order according to each mode of the reproduction mode or the special reproduction mode.

That is, in the recording mode, the input image data to the memory 8 is given the highest priority, followed by the reading of the encoded data for recording, the error correction access, the compression access, and the audio data input / output. Set the priority in the order of access for data, access for subcode data,
The arbitration described above is performed based on this priority.

Similarly, regarding the priority order at the time of reproduction, the acquisition of the reproduction coded data into the memory 8 is given the highest priority, and then the access for output data output, the access for error correction,
Priorities are set in the order of access for subcode data processing, access for decoding, and access for audio signal processing, and these priorities are switched according to instructions of recording operation and reproduction operation.

Furthermore, the priority order during special reproduction is basically the same as the priority order during reproduction, but access for subcode data processing is prioritized.

The above-described embodiment applies the present invention to a digital V
Although the present invention is applied to the signal processing circuit for TR, the present invention is not limited to this, and it is needless to say that the present invention can also be applied to a transmission device or the like that performs encoding / decoding based on the MPEG standard.

In this case, a processing block for motion compensation and a processing block for local decoding are newly added as the processing blocks in FIG. 1, and the encoding and decoding processing is performed as the arbitration operation in the memory controller 11. Prior to this, processing for motion compensation may be prioritized.

Further, in order to perform the real-time processing, it is necessary to perform the processing at a higher speed than that of the above-mentioned embodiment.
It is necessary to set to about Hz.

[0120]

As is apparent from the above description, according to the present invention, when a plurality of processing blocks are accessed in a single memory, the optimum address control according to the processing form in each processing block is performed. A single memory can be shared for various processes.

Further, according to the present invention, the access to the memory of each processing block is arbitrated and controlled according to the priority of the processing, so that the predetermined processing is performed at high speed in spite of sharing a single memory. be able to.

As a result, the timing control between the processes can be facilitated and the cost can be reduced as compared with the case where the memory has an independent memory.

Further, according to the present invention, the operation of the address conversion means is switched and controlled based on the parameter data corresponding to the type of data to be processed, so that a plurality of types of video signals can be obtained without adding a special configuration. Can respond.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration of a processing apparatus of the present invention.

2 is a diagram for conceptually explaining the configuration of the memory in FIG. 1, and FIG. 2A is a diagram showing the overall configuration;
(B) is a diagram schematically showing a sense amplifier.

FIG. 3 is a diagram for explaining an access correspondence relationship of each processing block with respect to the memory in FIG.

FIG. 4 is a diagram for explaining a configuration of a processing circuit in FIG.

FIG. 5 is a diagram showing a configuration of a frequency dividing circuit.

FIG. 6 is a diagram showing a configuration of a frequency dividing circuit.

FIG. 7 is a diagram showing a configuration of a frequency dividing circuit.

FIG. 8 is a diagram showing a configuration of a frequency dividing circuit.

FIG. 9 is a diagram showing a configuration of an address generation circuit.

FIG. 10 is a time chart for explaining an arbitration operation of the memory controller.

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Claims (3)

[Claims] 1. A plurality of processing means for performing various different processes, a memory means provided in common to each processing means, and a control means for controlling access between each processing means and the memory means. The signal processing device, wherein the control means controls the address in different units according to the processing means. 2. A plurality of processing means for performing various different processes, a memory means provided in common to each processing means, and a control means for controlling access between each processing means and the memory means. The signal processing device, wherein the control means gives priority to access of data having a high processing priority and executes each processing in a time-division manner. 3. A plurality of processing means for performing various different processings, a memory means provided in common to each processing means, and a means for setting parameters according to a plurality of types of data to be processed. A signal processing apparatus comprising: a control unit for performing address control between each processing unit and a memory unit, wherein the control unit varies the address control based on a parameter corresponding to each data.