JP3523477B2 - Shuffling device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a digital VTR for recording a digital video signal, and more particularly, to rearranging data by using a memory when compressing a digital signal (hereinafter, referred to as a VTR). , Which is referred to as shuffling). 2. Description of the Related Art When a video signal is compressed and recorded as a digital signal, an error generated during reproduction is generally dispersed to make the error inconspicuous, and a discrete cosine transform (hereinafter, referred to as "recording") performed at the time of recording is performed. Shuffling processing is performed in order to reduce the variation in the amount of information when performing post-DCT quantization and improve image compression efficiency. In the shuffling process, two memories capable of storing one frame of image data are used, and while one is performing writing, the other is storing data one frame before in a different order from the writing. A method of reading (hereinafter, referred to as a bank method) is used. [0004] However, 2
Since a memory for a frame has a large capacity and a poor cost performance, a method of performing shuffling processing using a memory for one frame as a means for solving the problem is as follows.
It is disclosed in JP-A-6-133291. Hereinafter, a conventional shuffling apparatus using a memory for one frame will be described. FIG. 4 shows an example of the configuration of the conventional shuffling device. 4, reference numeral 201 denotes an image data input unit;
Reference numeral 202 denotes a one-frame memory for storing the image data input from the memory 201; 203, an output unit for the image data output from the memory 202; and 204, the address of the image data input to the memory 202. An input address generation unit, 205 is an output address generation unit that controls the address of the image data output from the memory 202, 206 is a delay circuit that controls the input / output timing of data in the memory 202, and 207 is the output address generation unit Switches 205 and 209 for switching signals supplied to the section 205 and the delay circuit 206; and an address memory 21 for storing signals for controlling the input address generation section 204 and the output address generation section 205.
Reference numeral 0 denotes an address conversion unit that generates a signal for controlling the address memory 208 and the address memory 209. [0007] The image data of the (n-1) th frame recorded in the memory 202 is output in an order according to a predetermined shuffling rule. The control signal of the memory 202 for that purpose is given by the output address generation unit 205.
Is given through the address memory 208 or the address memory 209 according to the address generated by Also,
The output address generation unit 205 adds a lower address to the upper address of the generated address. Next, after the image data of the memory 202 is output, the image data of the n-th frame is input from the image input unit 201 to the same address. As for the higher order of the input address, the higher order of the output address of the previously output image data of the (n-1) th frame is output after being delayed by the delay circuit 206 for a predetermined time. The lower part of the input address is generated by the input address generator 204. In this way, when using the memory for one frame and successively reading out the image data which is continuously input, the image data is read out in an order different from the input order, and By writing the next input image data, the shuffling process can be performed with the memory for one frame. The above is the principle of the related art. Next, a case where the shuffling process of the digital VTR is performed by the related art will be specifically described with reference to FIGS. Since a digital VTR has two different data rates, it is hereinafter referred to as a standard mode and a high compression mode, respectively. In FIGS. 5 to 7, (a) is the standard mode, and (b) is the high mode. It indicates the compression mode. First, the structure of image data will be described with reference to FIGS. FIG. 5 shows the number of samplings of the image data for one frame in the standard mode and the high compression mode and the DC number.
This shows the number of T blocks. That is, in FIG. 5A, the sampling number of the luminance signal (hereinafter, referred to as Y signal) is 48 in the vertical direction.
0, 720 in the horizontal direction, and the number of DCT blocks is 60 DCT in the vertical direction and 90 DCT in the horizontal direction.
The sampling numbers of the color difference signal (hereinafter, referred to as Cr signal) and the second color difference signal (hereinafter, referred to as Cb signal) are 480 in the vertical direction and 180 in the horizontal direction, respectively. Direction 22.5
It becomes DCT. Similarly, in FIG. 5B, the sampling number of the Y signal is 480 in the vertical direction and 540 in the horizontal direction, the number of DCT blocks is 60 DCT in the vertical direction and 67.5 DCT in the horizontal direction. , And Cb signals are 240 in the vertical direction and 1 in the horizontal direction, respectively.
80, and the number of DCT blocks is 30 in the vertical direction.
DCT and 22.5 DCT in the horizontal direction. The DCT block, which is a basic unit of DCT, is composed of eight vertical sampling numbers and eight horizontal sampling numbers.
The number of DCT blocks of each signal of r and Cb becomes the number shown above by dividing the sampling number by 8. Next, FIG. 6 shows macroblock division for each mode. In FIG. 6, 3 is a macro block, 4 is the Y signal DCT block, 5 is the Cr signal DCT block, and 6 is the Cb signal DCT block. Here, when the macro block 3 is in the standard mode, as shown in FIG.
4 blocks 4 (Y0, Y1, Y2, Y3)
One DCT block 5 for r signal and one DCT block 6 for Cb signal, the number of DCT blocks for one macroblock is 1 DCT in the vertical direction and 6 DCT in the horizontal direction. The number of DCT blocks of the image data is 60 DCT in the vertical direction and 135 DCT in the horizontal direction (90 DCT (Y signal) + 22.5D
CT (Cr signal) +22.5 DCT (Cb signal)), and therefore the number of macroblocks of image data for one frame is 60 (60 DCT / 1 DCT) in the vertical direction and 22.5 (135 DCT / 6 DCT) in the horizontal direction. When the macro block 3 is in the high compression mode, as shown in FIG.
Six blocks 4 (Y0, Y1, Y2, Y3, Y4, Y
5) One CrT DCT block 5 and one Cb
The signal DCT block 6 consists of one, and therefore, the number of DCT blocks for one macro block is 2DC in the vertical direction.
T, 4DCT in the horizontal direction, and the number of DCT blocks of image data for one frame is 60 in the vertical direction from FIG.
DCT, 90 DCT in the horizontal direction (67.5 DCT (Y signal) +22.5 DCT (Cr signal or Cb signal)). Therefore, the number of macroblocks of image data for one frame is 30 (60 DCT / 2DCT) in the vertical direction and horizontal direction. 22.5 (90DCT / 4DCT). FIG. 7 shows the super block division for each mode. In FIG. 7, 2 is a super block, 3
Is the macroblock. The super block 2 is a unit in which 27 (0 to 26) macro blocks 3 are put together, and the reading and writing of image data to and from the memory by the shuffling device is performed as follows.
This is performed for each super block. The superblock 2 indicated by oblique lines in FIG. 7 is a superblock that is read first according to a predetermined shuffling rule, and thereafter, the lower superblock is sequentially read. The shuffling process performed using the memory for one frame in the case of the standard mode will be described below. FIG. 8 shows image data of one frame. The image data of the first frame input to the shuffling device is written in the memory in the horizontal direction from the upper left as shown in FIG. When image data is read from the memory, the superblock indicated by hatching in FIG. 7A is read first. Thereafter, reading from and writing to the memory are performed simultaneously. That is, the image data of the second frame is written into the memory block (superblock shown by oblique lines in FIG. 7A) after the image data of the first frame is read, and at the same time, (A) The super block immediately below the super block indicated by hatching is read out. Here, at the timing of writing and reading, in order to perform the shuffling process with the memory for one frame, the following two conditions must be satisfied. That is, the first condition is that the image data to be read first (FIG. 7A) before the first reading starts
The second condition is that the writing of the image data to be read first (FIG. 8) must be completed before the writing of the image data of the next frame starts. 7 (a) (readout of the super block indicated by oblique lines) must be completed. In the case of the standard mode, as shown in FIG. 7A, after the writing to the ninth super block from the top is completed, the writing is performed to the next super block of the tenth stage from the top. 7A, if the super block indicated by hatching in FIG. 7A is read, the two conditions can be satisfied and the shuffling process can be performed. In the high compression mode shown in FIG. 7B, image data to be read first (FIG.
Since the super block 2) indicated by diagonal lines in (b) is at the lowest level, there is no time to read image data from the memory, and in the high compression mode, the shuffling process is performed in the memory for one frame. I can't. However, there is a problem that cost performance is poor in the bank system. FIG. 5 shows that the number of samplings in the standard mode of the Y signal and that in the high compression mode are compared.
In both the high compression mode, the number of samplings in the vertical direction is the same, but the number of samplings in the horizontal direction is 1.5 times that of the high compression mode in the standard mode, and the number of samplings differs in each mode. For this reason, the same memory cannot be shared between the standard mode and the high compression mode, and there is a problem that cost performance is poor. An object of the present invention is to solve the problems of the above-described conventional shuffling device, and to provide a shuffling device that solves the problem. [0036] To achieve the above object,
Therefore, the present invention has taken the following measures. That is, the present invention
The shuffling device according to the first and second data
Shuffling device in digital VTR corresponding to
And converted to the first data rate for one frame
Memory with a data capacity of
When writing data, the encoded data is
Data rearranging means for rearranging according to the memory, and the memory
Memory system that controls writing and reading of data to and from
Control means, wherein the encoded data is DCT encoded
And a predetermined number of coded blocks
Put together the macro block and this macro block
Super bros arranged in a predetermined number by arranging them in two dimensions of flat and vertical
In the case of the first data rate,
The super block arranged in two dimensions of
Writing into the memory under the control of the control means;
In the case of a data rate, the data sorting means
The super block arranged in two dimensions
Control by the memory control means after rearrangement in one direction
Writing to the memory in accordance with
You. FIG. 1 is a block diagram of an embodiment of a shuffling device according to the present invention. In FIG. 1, reference numeral 101 denotes an image data input unit; 102, a memory having a capacity of one frame in standard mode conversion for storing the image data input from 101;
Reference numeral 103 denotes an output unit for image data output from the memory 102; 104, a switch for switching a write address control signal input to the memory 102;
05 is a changeover switch for switching a read address control signal input to the memory 102; 106 is an input address generator for generating a signal for controlling a write address of image data input to the memory 102 in the standard mode; 107 is The memory 102 in the high compression mode
An input address generator for generating a signal for controlling a write address of image data input to the memory; an output address generator for generating a signal for controlling a read address of image data output from the memory in a standard mode; , 109 are output address generation units for generating a signal for controlling the read address of the image data output from the memory 102 in the high compression mode.
0 is a delay circuit for controlling the input / output timing of the data of the memory 102, and 111 is a changeover switch for switching a signal given to the standard mode output address generator 108, the high compression mode output address generator 109, and the delay circuit 110. , 112 and 113 are address memories for storing signals for controlling the write address and read address of the memory 102, 114 is a switch for switching control signals for controlling the address memories 112 and 113, and 115 is the address in the standard mode. An address converter 116 generates a signal for controlling the memory 112 and the address memory 113, and an address converter 116 generates a signal for controlling the address memory 112 and the address memory 113 in the high compression mode. The (n-1) th frame of image data recorded in the memory 102 is output in an order according to a predetermined shuffling rule. For this purpose, the higher order of the address of the read control signal of the memory 102 is generated by the standard mode address converter 115 in the case of the standard mode, and is generated by the high compression mode address converter 116 in the case of the high compression mode. In the case of the standard mode via the address memory 112 or the address memory 113, the standard mode output address is generated.
Also, in the case of the high compression mode, it is provided to the high compression mode output address generation unit 109. After the lower order of the address of the read control signal of the memory 102 is added by the standard mode output address generator 108 or the high compression mode output address generator 109, the read control signal is supplied to the memory 102 as a read control signal of the memory 102. Next, after the image data in the memory 102 is output, the image data of the n-th frame is input from the image input unit 101 to the same address. As for the higher order of the input address, the higher order of the output address of the previously output image data of the (n-1) th frame is output after being delayed by the delay circuit 110 for a predetermined time. The lower order of the input address is added by the standard mode input address generator 106 in the case of the standard mode, and is added by the high compression mode input address generator 107 in the case of the high compression mode. Memory 10 as signal
2 given. As described above, in each of the standard mode and the high compression mode, when one frame of memory is converted into the standard mode and the image data that is continuously input is read continuously, the input order is The shuffling process can be performed by writing the next input image data to the memory block that has been read and output in a different order from that of the memory block. The above is the outline of the operation of the embodiment according to the present invention. Hereinafter, in each of the standard mode and the high compression mode as described above, 1 is calculated in terms of the standard mode.
A method for sharing a memory for a frame will be described in detail. First, FIG. 2 shows a memory space in the high compression mode. In FIG. 2, reference numeral 1 denotes an increase in memory, and 2 denotes the super block. The memory capacity of the remaining portion excluding the increase in memory 1 is one frame in high compression mode conversion. Here, the super block 2 indicated by oblique lines in FIG. 2 is a super block that is first read out according to a predetermined shuffling rule as in FIG. The memory increment 1 is a capacity equivalent to the image data read from the memory before the image data of the next frame is input to the memory (the superblock 2 indicated by oblique lines in FIG. 2). , Which is the capacity of one stage of the super block, which is 0.2 in high compression mode conversion.
This is the capacity for the frame. When the memory size is increased by one super block in the vertical direction, when the writing of the super block at the fifth stage from the top is completed, the increased amount is increased by six.
Since the memory block of the second stage is empty, when the writing of the first stage of the next frame starts, it becomes empty.
The first stage memory block is written, and the first read is performed during the writing. Then, before the writing of the data in the second stage of the next frame is started, the reading of the super block to be read (the hatched portion in FIG. 2) is completed. The data in the row is the memory block from which reading has been completed (the shaded portion in FIG. 2).
And shuffling processing can be performed. FIG. 3 shows a method of allocating the image data of 1.2 frames in the high compression mode as described above to the memory of one frame in the standard mode. In FIG. 3, (1) shows the arrangement of the image data in the high compression mode, and (2) shows the arrangement of the image data in the high compression mode in order to share the memory in the standard mode and the high compression mode, and allocates them to the memory. This is an array of image data. Also, 1 indicated by a dotted line is an increase in memory for 0.2 frames in high compression mode conversion in FIG.
2 is the super block, 3 is the macro block, and A, B, C, and C of the super block 2 in FIG.
D and E respectively correspond to A, B, C, D and E of the super block 2 in FIG. Further, the size of the image data in FIG.
There are 0 macroblocks (60 DCT) and 22.5 macroblocks in the horizontal direction (90 DCT). ). Here, the capacities of the memories in the standard mode and the high compression mode will be compared. In the case of the present embodiment, the memory in the high compression mode has a capacity of 1.2 times in the vertical direction. However, in the standard mode, the capacity of image data for one frame is Y, Cr, Cb in FIG.
When the signals are combined, the vertical direction is 60 DC as described above.
T, 135DCT in the horizontal direction. In the high compression mode,
From FIG. 5B, since the vertical direction is 60 DCT and the horizontal direction is 90 DCT as described above, the capacity of image data for one frame in the standard mode is 1.5 times that in the high compression mode.
Double. Therefore, the memory capacity for 1.2 frames obtained by adding the memory capacity for 0.2 frames in the high compression mode does not exceed the memory capacity for one frame in the standard mode. It is possible to share the memory in the high compression mode. Here, the capacity of image data for 1.2 frames in the high compression mode is 72D in the vertical direction from FIG.
CT, 90 DCT in the horizontal direction. In this case, since the capacity of the memory used in the standard mode is 60 DCT in the vertical direction and 135 DCT in the horizontal direction, the image data for 1.2 frames in the high compression mode is stored in the memory so as to fit in the size of the memory used in the standard mode. Reorder. In the case of this embodiment, image data arranged as shown in FIG. 3A is divided into super blocks 2 indicated by A, B, C, D, and E, and these are 3
As shown in (2), the 27 blocks (0 to 2) arranged in a line in the vertical direction and
The macroblock 3 of 6) is divided and arranged in one row in the horizontal direction. By rearranging the data as described above, the capacity of the image data in the high compression mode is reduced by 60 in the vertical direction.
The DCT is 108 DCT in the horizontal direction, and the vertical direction of the memory used in the standard mode is 60 DCT and the horizontal direction is 135 DCT.
Since it fits in the CT, the memory can be shared. [0063] As described above, according to the present invention, according to the present onset Akira,
For a plurality of data rate of the signal, it is possible to perform the shuffling process, and in accordance with this onset bright, by sequentially inputting the next data to the output address of the data, the memory capacity reduction can be, and in accordance with this onset bright, when handling data in blocks, such as DCT, for a plurality of data rate of the signal, while the reduction of the memory capacity, performs shuffling process it can, also, according to this onset bright, with additional minimum memory capacity can shuffling process corresponding to a plurality of data rates, also according to the invention of claim 5, the digital V
In TR, it is possible to perform the shuffling process with 1.2 frames of the memory at a high compression mode, and in accordance with this onset bright, in a digital VTR, high in memory capacity of one frame in the standard mode in terms of 1 in compressed mode conversion.
Two frames of image data can be recorded, and therefore the same memory can be shared in the standard mode and the high compression mode. This allows the shuffling device to be used in both the standard mode and the high compression mode with a smaller memory capacity than the bank system. Can be realized. [0064] Further, the present onset bright above, it is possible to reduce the circuit scale of the shuffling apparatus, thus it is possible to reduce the cost further, by using such a shuffling process in a digital VTR, In addition to the effects described above, it is possible to improve the image quality.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a shuffling device according to the present invention. FIG. 2 is a diagram showing an example of a memory capacity of a memory for 1.2 frames used for shuffling processing in a high compression mode according to the present invention. FIG. 3 is a diagram showing an embodiment of a method of rearranging image data for sharing a memory in a standard mode and a high compression mode according to the present invention. FIG. 4 is a block diagram showing a conventional shuffling device. FIG. 5 is a diagram showing the number of samples of image data and the number of DCT blocks in the standard mode and the high compression mode. FIG. 6 is a diagram illustrating macroblock division of image data in a standard mode and a high compression mode. FIG. 7 is a diagram illustrating superblock division of image data in a standard mode and a high compression mode. FIG. 8 is a diagram illustrating an input order of first image data to a memory; [Description of Signs] 1 Memory increase 2 Super block 3 Macro block 4 Y signal DCT block 5 Cr signal DCT block 6 Cb signal DCT block 101 Image input unit 102 Memory 103 Image output unit 104 Switch 105 Switch 106 Standard mode input Address generator 107 High compression mode input address generator 108 Standard mode output address generator 109 High compression mode output address generator 110 Delay circuit 111 Switch 112 Address memory 113 Address memory 114 Switch 115 Standard mode address converter 116 High compression Mode address conversion unit 201 Image input unit 202 Memory 203 Image output unit 204 Input address generation unit 205 Output address generation unit 206 Delay circuit 207 Switching switch 208 address memory 209 address memory 210 address converter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 7/24

Claims (1)

(57) [Claim 1] Corresponding to the first and second data rates
In a shuffling device in a digital VTR, the data volume of one frame is converted into a first data rate.
Memory having a sufficient amount of data, and when writing the encoded data to the memory,
Data sorting to sort data according to the data rate
Control means for controlling writing and reading of data to and from the memory.
Memory control means , wherein the encoded data is encoded by DCT encoding.
And a macro block in which a predetermined number of
And this macroblock is converted to horizontal and vertical two dimensions.
And super blocks arranged in a predetermined number and arranged. In the case of the first data rate , the super blocks are arranged in two dimensions.
The super block is controlled by the memory control means.
Write to the memory and store the data at the second data rate.
In this case, the data is rearranged two-dimensionally by the data rearranging means.
Sort the placed super blocks into one dimension in the horizontal direction
The memory is then stored in the memory under the control of the memory control means.
A shuffling device for writing.