JPH08123356A - Display device - Google Patents

Abstract

PURPOSE: To provide a display device capable of easily performing control for display and surely performing the display even when the number of horizontal dots of a character font in a character mode is smaller than that of bits of each address of a display RAM. CONSTITUTION: The output of a first detection circuit 9 which detects the fact that the n-th bit of display data is held with a shift register 21, and the output of a second detection circuit 10 which detects the fact that the m-th bit of the display data is held with the shift register 21 are applied to an address counter 4 selectively by switch control output outputted from a mode control circuit 3, and the content of the address counter 4 is increased by one. In this way, the display on a liquid crystal display panel 23 can easily and surely be performed even when the number of bits read out of each address of the display RAM 2 in a graphic mode and the character mode is different from each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device suitable for performing a dot display in a graphic mode, a character mode, etc. on a display panel such as a liquid crystal display.

[0002]

2. Description of the Related Art A dot display on a display panel such as a liquid crystal display is realized by using a microcomputer.
Display data for dot display is stored in a display RAM built in the microcomputer, and the display data is rewritten whenever necessary. Here, each bit of the n-bit display data stored in each address of the display RAM corresponds to each dot for display, and when the bit of the display data is “1”, it corresponds to lighting of the dot. , The display data bit is "0"
In case of, the dot is turned off.

There are two types of modes in which the dot display is performed using the display data of the display RAM, that is, the graphic mode and the character mode. The former graphic mode has no concept of character fonts,
In this mode, n-bit display data read from each address of AM is continuously displayed as it is as dot information to display an arbitrary pattern or the like. The latter character mode has a character font of vertical 1 × m horizontal dots for one character, and m corresponding to the horizontal m dots.
This is a mode in which bit display data is continuously stored in each address of the display RAM.

Then, dot display is performed by switching between the two modes as needed.

[0005]

By the way, when the display data of m bits corresponding to the horizontal m dots in the character mode is equal to the number of bits of each address of the display RAM, the display for the graphic mode and the character mode is performed. Control is easy, but m-bit display data corresponding to horizontal m dots in character mode is
If the number of bits is smaller than the number of bits of each address of the display RAM, horizontal m bits of a plurality of display data or part of the information will be included in each address of the display RAM. There is a problem that the control from reading the display data to performing dot display on the display panel becomes complicated.

Therefore, according to the present invention, even when the number of horizontal dots of a character font in the character mode is smaller than the number of bits of each address of the display RAM, the display device can be easily controlled for reliable display. The purpose is to provide.

[0007]

The present invention has been made to solve the above problems, and is characterized in that each address is composed of n bits and a dot display is made on a display panel. Display RA for storing display data for performing
M, an address counter that can access all the addresses given to the display RAM, and all n bits of the display data stored at each address of the display RAM are used to perform horizontal display of n dots for each address. The first display mode to be performed and the upper n-th display data stored in each address of the display RAM having a predetermined character font in which the number of display dots in the horizontal direction is m dots (less than n dots).
A mode control circuit for switching and controlling a second display mode which does not require m bits in horizontal display, and display data read from the display RAM by access by the address counter in synchronization with a shift clock. A serial input shift register, a first detection circuit that detects that the nth bit of the display data is held in the shift register in synchronization with the shift clock, and the display data in synchronization with the shift clock. A second detecting that the m-th bit of the
And a switching circuit for switching the output of the first or second detection circuit according to the output of the mode control circuit and applying it to the address counter to increment the content of the address counter. The point is to cause the display panel to perform dot display according to the first and second display modes based on the content held in the shift register.

[0008]

According to the present invention, the output of the first detection circuit for detecting that the n-th bit of the display data is held in the shift register and the output of the second detection circuit for detecting the m-th bit of the display data are detected. Output and selectively apply to the address counter by the switching control output from the mode control circuit,
The content of the address counter is incremented. Thus, even when the number of bits read from each address of the display RAM is different between the first display mode and the second display mode, it is possible to easily and surely perform display on the display panel.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a display device of the present invention. FIG.
In the above, it is assumed that all the configurations except the liquid crystal display panel described later are built in the microcomputer.

In FIG. 1, (1) is a CPU, which controls various operations of the microcomputer. Particularly, in this embodiment, the CPU (1) outputs 10-bit address data to access a display RAM described later, and the address of the display RAM accessed by the 10-bit address data is 8 bits. Or write the display data of
The stored display data is read and checked from the address of M for the purpose of confirming the data. (2) is the display RAM described above, and each address has an 8-bit configuration and has a storage capacity of 1 Kbyte. Display RA
The memory contents of M (2) are stored in the CPU depending on the necessity of display.
It is rewritten each time according to the instruction from (1).
(3) is a mode control circuit, which outputs a control signal according to the graphic mode (first display mode) and the character mode (second display mode). Specifically, when selecting the graphic mode, "1" is output from the mode control circuit (3), and when selecting the character mode, "0" is output from the mode control circuit (3). The character font in the character mode is, for example, horizontal 5 dots × vertical 7 dots. (4) is an address counter, which applies 10-bit address data to the display RAM (2) to access the address of the display RAM (2). Where display RAM
(2) is a dual port, CPU
It is assumed that the accesses from (1) and the address counter (4) are independently and asynchronously performed. The AND gates (5) and (6) and the OR gate (7) form a switching circuit, and the output of the mode control circuit (3) is directly applied to one input terminal of the AND gate (5), A mode control circuit (3) is provided at one input terminal of (6).
Is inverted and applied, and the output of the OR gate (7) is connected to the input for incrementing the content of the address counter (4). Reference numeral (8) is a shift register (previous stage shift register), which holds the 8-bit display data read from the display RAM (2) in parallel and then serially outputs in synchronization with the clock CK1 for data shift. It is a thing. Reference numeral (9) is a first detection circuit, which outputs a high level pulse when the 8-bit display data is serially output from the shift register (8) in the graphic mode, and its output is an AND gate. It is connected to the other input terminal of (5). (10) is a second detection circuit, which outputs a high level pulse when the display data for 5 bits is serially output from the shift register (8) in the character mode, and the output is an AND gate. It is connected to the other input terminal of (6). (11) is a 3-bit counter, and clocks CK1 and C
A waveform for outputting a high level pulse from the first and second detection circuits (9) and (10) is formed based on K2,
Each bit output is output to the first and second detection circuits (9) (10).
Is to be applied to. Hereinafter, a specific configuration of the counter (11) will be described with reference to FIG.

In FIG. 2, the transmission gate (101) is opened by the high level of the clock CK1, and the inverters (102) (103) and the transmission gate (104) form a closed loop for holding the passing output of the transmission gate (101). The transmission gate (104) is opened by the low level of the clock CK1 via the inverter (12). Similarly, the transmission gate (105) allows the output of the inverter (102) to pass therethrough, and the gate is opened by the high level of the clock CK2. The inverters (106) (107) and the transmission gate (108) form a closed loop for holding the passing output of the transmission gate (105), and the transmission gate (108) is at a low level of the clock CK2 via the inverter (13). Opens the gate. An inverter (109) and a transmission gate (110) are provided between the output of the inverter (106) and the input of the transmission gate (101).
Are connected in series, and the output of the inverter (106) is inverted and applied to the input of the transmission gate (101). The transmission gate (110) is an inverter (14) whose input is grounded.
The output keeps the gate open all the time. N
The drain and source of the channel type MOS transistor (111) are connected between the transmission gate (104) and the ground, and the output of the second detection circuit (10) is applied to the gate. The above is the counter (1
It has a structure for the lower 1 bit of 1). Regarding the same constituent element as the lower 1 bit in the remaining 2 bits of the counter (11), the numbers in which 100s are changed to 2s and 3s are described and the description thereof is omitted. Between the configuration of the lower 1 and 2 bits of the counter (11), a NAN
A D gate (15) and an inverter (16) are provided so that one input of the NAND gate (15) is connected to the output of the inverter (14) and the other input is connected to the output of the inverter (106). Further, its output is connected to the control terminal of the transmission gate (210) via the inverter (16). Further, an inverter (17) and a NOR gate (18) are provided between the configuration of the lower 2 bits and the most significant bit of the counter (11). One input of the NOR gate (18) is connected to the output of the NAND gate (15) and the other input is connected to the inverter (20) via the inverter (17).
6) and the output is connected to the control terminal of the transmission gate (310). Regarding the operation of the counter (11) configured as described above, FIG.
This will be described using the time chart of.

First, the counter (11) is reset. That is, N-channel type MOS transistors (111) (21) provided for each bit of the counter (11)
1) It is assumed that (311) are all turned on in a pulsed manner. First, the inverter (102) in the configuration of the lower 1 bit
The output Q1A of the inverter and the output Q1B of the inverter (106) will be described. First, when the N-channel type MOS transistor (111) is turned on, Q1A is at high level and Q1B is at low level. If the clock CK1 rises to high level from this state,
Transmission gate (101) opens the gate,
Q1A falls to the low level in synchronization with the rising of the clock CK1. Then, when the clock CK2 rises, the transmission gate (105) opens the gate, and Q1B rises to the high level in synchronization with the rising of the clock CK2. When the clock CK1 falls at the same time as the rising of the clock CK2, the transmission gate (104) opens the gate, Q1A holds the low level, and while the clock CK1 is at the low level, Q1B is at the high level regardless of the change of the clock CK2. Hold. After that, when the clock CK1 rises again,
Transmission gate (101) opens the gate,
Based on the high level output of the inverter (106), Q1
A rises to a high level in synchronization with the rising edge of the clock CK1. After that, when the clock CK2 rises,
The transmission gate (105) opens the gate,
Q1B falls to the low level in synchronization with the rising edge of the clock CK2. When the clock CK1 falls at the same time that the clock CK2 rises, the transmission gate (104) opens the gate, Q1A holds a high level, and Q1B is low level regardless of the change of the clock CK2 while the clock CK1 is low level. Hold. Hereinafter, the waveforms of Q1A and Q1B are this repetition.

Next, Q2A and Q2B which are the outputs of the inverters (202) (206) of the lower 2 bits of the counter (11) will be described. The transmission gate (210) is opened only when the lower 1 bit Q1B is at a high level. First, N channel type M
After the OS transistor (211) is turned on, Q
2A is high level and Q2B is low level.
Clock CK1 while Q1B is high level
When it starts up, the transmission gate (201)
Opens the gate, and Q2A falls to the low level in synchronization with the clock CK1. After that, when the clock CK2 rises, the transmission gate (205) opens the gate, and Q2B rises to the high level in synchronization with the rising of the clock CK2. After that, when the clock CK1 rises again while Q1B is at the high level,
The transmission gate (201) opens the gate,
Q2A rises to a high level in synchronization with the rising edge of the clock CK1. After that, when the clock CK2 rises, Q2B falls in synchronization with the rise of the clock CK2. Q2A and Q2B change by repeating the above operation.

Next, the most significant bit inverter (30
2) The waveforms of Q3A and Q3B which are the outputs of (306) will be described. In addition, the transmission gate (31
In 0), the gate is opened when both Q1B and Q2B are at the high level. First, after the N-channel type MOS transistor (311) is turned on, Q3A is at high level and Q3B is at low level. Q1B and Q2
When the clock CK1 rises to the high level when both B are at the high level, the transmission gate (301) opens the gate, Q3A falls to the low level in synchronization with the rise of the clock CK1, and then the clock CK2 rises. Then, the transmission gate (305) opens the gate, and Q3B is the clock CK.
It rises to a high level in synchronization with the rising edge of 2. Q
The low level of 3B is held because the transmission gate (304) opens the gate when the clock CK1 falls, and during the low level period of the clock CK1, Q3B remains high level no matter how much the clock CK2 changes. . After that, when the clock CK1 rises again while both Q1B and Q2B are at the high level, Q3A rises in synchronization with the rising edge of the clock CK1, and when the clock CK2 rises thereafter, Q3B synchronizes with the rising edge of the clock CK2. Fall to low level.

3 of the counter (11) changing as described above
Bit outputs Q1B, Q2B, Q3B are applied to the first and second detection circuits (9), (10), respectively. Hereinafter, specific examples of the first and second detection circuits (9) and (10) will be described with reference to FIG.
And FIG. 5 will be described. Q1B is a waveform that changes in synchronization with the clock CK1. That is, Q1B is a waveform that changes every time the display data is serially output in synchronization with the clock CK1. Therefore, in order to detect that the fifth-bit display data is output from the shift register (8), the second detection circuit (10) performs a logical operation on Q1B, Q2B, Q3B and the clock CK1 in the period X. The high level should be output from. The specific circuit is shown in FIG. In the period X, Q1B and Q2B are low level, and Q3B is high level. Therefore, as shown in FIG. 4, the AND gate (19) may be configured to inversely apply Q1B and Q2B and apply Q3B and the clock CK1 as they are to perform a logical product operation. Accordingly, in the period X, the second detection signal (high-level pulse) is output. Further, in order to detect that the display data of the 8th bit is output from the shift register (8), Q1B and Q2 in the period Y are detected.
B, Q3B and the clock CK1 may be logically operated so that a high level is output from the first detection circuit (9). The specific circuit is shown in FIG. In the period Y, Q1B, Q2B, and Q3B are all at the high level. Therefore, as shown in FIG. 5, the AND gate (20) has Q1B, Q2B, Q3B and a clock CK1.
May be applied as it is to perform a logical product operation. Thus, in the period Y, the first detection signal (high-level pulse) is output.

Returning to FIG. 1 again, when the character mode is selected, all the bits of the counter (11) are reset by the output pulse of the second detection circuit output from the AND gate (27) (N). The gates of the channel type MOS transistors (111) (211) (311) become high level and are turned on. Reference numeral (21) is a shift register, which has the same number of bits as the maximum number of dots that can be displayed in one horizontal row of the display panel described later, and the display data serially output from the shift register (8) is used as the clock CK1. The configuration is such that serial input is performed in synchronization. For example, since the character font in the character mode is horizontal 5 dots × vertical 7 dots, the number of bits of the shift register (21) is a common multiple of 8 bits of the graphic mode display data and 5 bits of the character mode display data. Good (eg 40 bits). (2
2) is a display data latch circuit, which has a latch clock C
The contents held in the shift register (21) are latched in synchronization with K3. Reference numeral (23) denotes a liquid crystal display panel, which is composed of, for example, a dot matrix of horizontal 40 dots × vertical 7 dots. Reference numeral (24) is a segment drive circuit for driving any of the 40 vertical segment electrodes of the liquid crystal display panel (23) based on the latch data of the display data latch circuit (22). Reference numeral (25) is a common drive circuit for driving any of the seven common electrodes in the horizontal direction of the liquid crystal display panel (23) based on the control output from the control circuit (26).

The operation of FIG. 1 configured as described above will be described for each of the graphic mode and the character mode. First, when the graphic mode is selected, "1" is output from the mode control circuit (3) and the output of the first detection circuit (9) is OR gate (7).
Connected to increment the address contents of the address counter (4) output from the. Then, when a predetermined address of the display RAM (2) is accessed according to the address data output from the address counter (4), 8-bit display data is read from the display RAM (2) and the shift register (8) is read. Applied in parallel. The 8-bit display data once held in the shift register (8) is serially input to the subsequent shift register (21) in synchronization with the clock CK1. When the serial input of 8-bit display data to the shift register (21) is completed, all the 3-bit contents of the counter (11) become "0" and a high level pulse is output from the first detection circuit (9). Is output, and the address counter (4) is +1
Incremented. Since the AND gate (27) is closed, the counter (11) is not reset by the output of the second detection circuit (10). Then, the above-described operation is repeated, and the shift register (21) is operated at 40
When the display data for one bit is held, the control circuit (2
The display data latch circuit (22) latches the 40-bit display data of the shift register (21) by the clock CK3 output from 6), and then the segment drive circuit (24) and the common drive circuit (25) are driven. Thus, dot display for one horizontal line is performed on the liquid crystal display panel (23). In this way, the graphic mode is realized by performing dot display up to 7 columns.

When the character mode is selected, "0" is output from the mode control circuit (3), and the second
The output of the detection circuit (10) is output from the OR gate (7) and is connected to increment the address content of the address counter (4). Then, the display RA is performed according to the address data output from the address counter (4).
When the predetermined address of M (2) is accessed, the display R
8-bit display data (the upper 3 bits are invalid data regardless of display) is read from AM (2) and applied in parallel to the shift register (8). The 8-bit display data once held in the shift register (8) is serially input to the subsequent shift register (21) in synchronization with the clock CK1. When the serial input of the lower 5 bits of display data to the shift register (21) is completed, all the 3 bits of the counter (11) are AND gates by the high level pulse output from the second detection circuit (10). The address counter (4) is incremented by +1 while being reset via (27). Then, the above-described operation is repeated, and the shift register (21) is operated at 40
When the display data for one bit is held, the control circuit (2
The display data latch circuit (22) latches the 40-bit display data of the shift register (21) by the clock CK3 output from 6), and then the segment drive circuit (24) and the common drive circuit (25) are driven. Thus, dot display for one horizontal line is performed on the liquid crystal display panel (23). In this way, by performing dot display for up to 7 columns, a character mode for 8 characters is realized.

As described above, even if the number of horizontal dots of the character font is less than 8 dots (for example, 5 dots) even though the number of bits of each address of the display RAM (2) is 8 bits, the graphic mode is set. Also, the character mode can be easily realized.

[0020]

According to the present invention, when the number of bits of each address of the display RAM is n bits, even if the horizontal dot number of the character font is m dots which is less than n, the first display mode (graphic Mode and the second display mode (character mode) can be realized with simple control.

[Brief description of drawings]

FIG. 1 is a diagram showing a display device of the present invention.

FIG. 2 is a diagram showing a specific circuit of the counter shown in FIG.

FIG. 3 is a time chart showing the operation of the counter shown in FIG.

FIG. 4 is a diagram showing a specific circuit of a second detection circuit.

FIG. 5 is a diagram showing a specific circuit of a first detection circuit.

[Explanation of symbols]

 (2) Display RAM (3) Mode control circuit (4) Address counter (5) (6) AND gate (7) OR gate (9) First detection circuit (10) Second detection circuit (21) Shift register (23) Liquid crystal display panel

Claims (3)

[Claims] 1. A display RAM in which each address is composed of n bits, and display data for performing dot display on a display panel is stored, and an address counter capable of accessing all the addresses given to the display RAM. A first display mode in which a horizontal display of n dots for each address is performed using all n bits of the display data stored in each address of the display RAM, and the number of display dots in the horizontal direction is m dots (n Mode control for switching control of a second display mode in which upper mn bits of the display data stored in each address of the display RAM having a predetermined character font (less than dots) are unnecessary in horizontal display. Circuit and the display R by access by the address counter
A shift register for serially inputting the display data read from the AM in synchronization with a shift clock; and a detection unit for detecting that the nth bit of the display data is held in the shift register in synchronization with the shift clock. 1 detection circuit, a second detection circuit that detects that the m-th bit of the display data is held in the shift register in synchronization with the shift clock, and the second detection circuit according to the output of the mode control circuit. A switching circuit for switching the output of the first or second detection circuit and applying it to the address counter to increment the content of the address counter; and based on the content held in the shift register, the display panel displays A display device for performing dot display according to the first and second display modes. 2. The display device according to claim 1, wherein the shift register can serially hold a plurality of pieces of display data having a bit number equal to the number of dots that can be displayed in one horizontal line of the display panel. 3. An n-bit pre-stage shift register for serially holding each display data read from each address of the display RAM in parallel and serially inputting to the shift register in synchronization with the shift clock is provided. The display device according to claim 2, wherein the display device is a display device.