JPH08116259A - Digital/analog converter - Google Patents

Abstract

PURPOSE: To realize the D/A converter being an inexpensive D/A converter on market with higher resolution than that of the D/A converter on market with a simple circuit configuration. CONSTITUTION: In the case of D/A converting a 10-bit digital signal, for example, by using an 8-bit D/A converter on market, a period T used for providing an output of 10-bit data is divided equally into four and a value Dh of high- order 8 bits of the 10-bit data or Dh+1 is D/A-converted by the 8-bit D/A converter 22 for each period division divided equally. In this case, number of times of output of the Dh+1 is selected so that the sum of the low-order 2-bits of the 10-bit data and the 8-bit data outputted for the period T is equal to the 10-bit data. Thus, when a voltage signal outputted from the 8-bit D/A converter 22 is integrated by an integration circuit 24, a signal outputted from the integration circuit 24 is equal to the D/A-converted 10-bit digital signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to a D / A converter using pulse width modulation.

[0002]

2. Description of the Related Art Conventionally, pulse width modulation (PWM) for converting a digital signal into an analog signal by modulating the pulse width of a 1-bit high level (H level) and low level (L level) pulse signal is performed. The D / A converter used is known. Figure 5 shows D / using this pulse width modulation.
It is a circuit diagram showing a circuit configuration of an A converter.

As shown in FIG. 1, first, the pulse output circuit 1
0 outputs a pulse signal having a pulse width proportional to the magnitude of the digital signal from the terminal. This pulse signal is the resistance R2
The signal is integrated and averaged by an integrating circuit including a capacitor C2 and a capacitor C2, and the integrated and averaged signal is output from the terminal via a buffer circuit using the OP amplifier A2.

For example, if the signal output from the terminal of the pulse output circuit 10 is a pulse train whose pulse width gradually decreases as shown in FIG. 3A, the waveform output from the terminal is The resulting analog waveform is as shown in (B). As described above, D / using pulse width modulation
The A converter has a simple circuit configuration, is small in size, and is inexpensive, but has a drawback that the output accuracy is low and the conversion time becomes long when the resolution is increased.

[0005]

On the other hand, a parallel type D
The / A converter is a pulse width modulation (serial type) D
Compared with the / A converter, the output accuracy is good and the conversion time is fast. By the way, the (parallel type) D / A converters that are often used for general purposes are 8-bit and 12-bit ones, but these are many types and cheap in price.
On the other hand, for example, a 10-bit one is not general and is expensive. However, there are cases where a D / A converter with such an uncommon resolution is required.

The present invention has been made in view of the above circumstances, and utilizes a commercially available inexpensive D / A converter and has a resolution of several bits higher than that of the D / A converter. The purpose is to provide a converter.

[0007]

SUMMARY OF THE INVENTION The present invention, in order to achieve the above object, decomposing the M-bit data so that the sum of 2 ^MN pieces of N-bit data, sequentially the 2 ^MN pieces of N-bit data Processing means for outputting in time series, and N for D / A converting N-bit data sequentially output from the processing means
A bit D / A converter and an integrating means for integrating and averaging the voltage signals sequentially output from the N-bit D / A converter are provided.

[0008]

According to the present invention, by the processing means, decomposing the M-bit data so that the sum of 2 ^MN pieces of N-bit data and the 2 ^MN pieces of N-bit data sequence chronologically output To do. Next, the N-bit data sequentially output from the processing means is D / A converted by the N-bit D / A converter, and the voltage signal sequentially output from the N-bit D / A converter is integrated and averaged by the integrating means. To do.

For example, the processing means decomposes 10-bit data into a sum of four 8-bit data,
The four 8-bit data are sequentially D / A converted by the D / A converter. Since the voltage signal output from the D / A converter is obtained by decomposing 10-bit data into four 8-bit data, the voltage signal is integrated and averaged by the integrating means to obtain the original 10-bit data. Is converted into a voltage signal representing.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a D / A converter according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a D / A converter according to the present invention. In the figure, a 10-bit D / A converter using a commercially available 8-bit D / A converter is shown.

The D / A converter shown in FIG.
It is composed of a 0-bit and 8-bit D / A converter 22, an integrating circuit 24, and a buffer circuit 26. The digital signal input terminals D0 to D7 and the write control terminal WR of the D / A converter 22 are connected to the CPU 20.
When 20-bit 8-bit data is output to the digital signal input terminals D0 to D7 of the D / A converter 22 and a write pulse signal is output to the write control terminal WR, the D / A converter 22 is output from the CPU 20. The 8-bit data is D / A converted and an analog signal is output from the output terminal OUT.

The output terminal of the D / A converter 22 is connected to an integrating circuit 24 composed of a resistor R1 and a capacitor C1 so that the signal output from the output terminal of the D / A converter 22 is integrated. It has become. And
The signal integrated by the integrating circuit 24 is output from the output terminal via the buffer circuit 26 including the OP amplifier A1.

Now, the principle of converting a 10-bit digital signal into an analog signal by using the 8-bit D / A converter as shown in FIG. 1 will be described. The CPU 20 generates a 10-bit digital signal, but has an 8-bit D / A converter 22 having only an 8-bit data input terminal.
It is not possible to output 10-bit data as it is. Therefore, the following measures are taken.

[0014] 10 bits of data in order from the upper bit _{D 9, D 8, D 7} , D 6, ···, and D _1, D _0, which is represented by decimal number, D = D ^₉ × 2 ₉ + D ₈ × 2 ⁸ + ... + D ₁ × 2 + D ₀ (1) This equation (1) can be rewritten as the following equation.

D = (D ₉ × 2 ⁷ + D ₈ × 2 ⁶ + ... + D ₂ ) × 2 ² + D ₁ × 2 + D ₀ = Dh × 2 ² + Dl (2) In the expression (2), Dh is , Top 8 as shown in FIG.
It is a value indicated by a bit, and Dl is a value indicated by the lower 2 bits. Further, since the value indicated by Dl is at least 3 or less, the equation (2) can be further rewritten as follows.

D = Dh × (4-Dl) + (Dh + 1) × Dl (3) As can be seen from the equation (3), 10-bit data is (4-
It is represented by the sum of Dl) 8-bit data Dh and Dl 8-bit data (Dh + 1). That is, 10-bit data is represented by the sum of four 8-bit data (however,
When all the bits of Dh are at the H level (FFH), Dh + 1 cannot be represented by 8 bits, and in this case, Dl = 0 is treated. Therefore, 1 generated by the CPU 20
The range of 0-bit data D is 0 to 1020).

Therefore, assuming that the period in which the CPU 20 outputs 10-bit data is T, this period T is divided into four equal parts,
One 8-bit data is output to the D / A converter 22 in one section T / 4. That is, 10-bit data is decomposed into the sum of four 8-bit data as shown in the equation (3),
During the period T, these four 8-bit data are output to the D / A converter 22.

Then, as shown in FIG. 1, the D / A converter 2
2 is provided with an integrating circuit 24 in the subsequent stage, and the D / A converter 22
If the signal output from is smoothed (integrated), these 8-bit data are smoothed (integrated), and finally the sum of these 8-bit data, that is, the value indicated by the 10-bit data, is obtained. It can be converted into a proportional voltage signal.

FIG. 2 shows the CPU 20 to the D / A converter 2
2 is an explanatory diagram showing the values to be output to 2 for each value of the lower 2 bits Dl (this figure may be considered to indicate the voltage value output from the D / A converter 22). Incidentally, the numbers 0 to 3 of the counter value in the figure are values indicating the respective sections when the above-mentioned period T is divided into four equal parts, and are shown as 0, 1, 2, 3 in chronological order.

As shown in the figure, when Dl = 0, Dh is output in all sections 0 to 3.
When Dl = 1, Dh is output in a section other than the section 1 and Dh + 1 is output in the section 1. Similarly, when Dl = 2, Dh + 1 is output in the sections 1 and 2, and when Dl = 3, Dh + 1 is output in the sections 1, 2 and 3. That is, Dh + 1 is output from the section 1 to the section indicated by the value of Dl, and Dh is output in other sections.

In FIG. 3, 10-bit data is converted into 8 as shown in FIG.
7 is a flowchart showing a procedure of the CPU 20 for decomposing into the sum of bit data. First, initialization is performed and the counter is set to 0 (step S10). Subsequently, it is determined whether or not the counter is 0 (step S12), and if the counter is 0, 10-bit data to be output to the D / A converter 22 is read from the internal memory of the CPU 20 (step S14). The 10-bit data output to the D / A converter 22 is calculated in advance or during the D / A conversion and is recorded in the internal memory of the CPU 20.

[0022] Loading a 10-bit data in step S14, substitutes the Dh is the upper 8 bits of 10-bit data D _OUT (8-bit data to be output to the D / A converter 22) (step S16). on the other hand,
If the counter is not 0 in step S12,
Next, it is determined whether Dh is FFH (step S
18). If Dh is FFH, Dh is substituted for D _OUT regardless of the value of the counter and the lower 2 bits (step S16). That is, when Dh is FFH, a value larger than this cannot be output to the D / A converter 22, and therefore a value 1020 or more is set to 1020.

In step S18, Dh is not FFH.
If not, then the counter is compared with the value of Dl (step
S20). At this time, when the counter is larger than Dl
Is D _OUTIs substituted with Dh (step S16). on the other hand,
When the counter is less than the value of Dl, D_OUTTo Dh + 1
Substitute (step S22). D as above_OUT
Is set, then D_OUTTo the D / A converter 22
(Step S24). The D / A converter 22
To D_OUTThe output interval is 4 minutes of the period T as described above.
I am trying to be 1.

Then, the counter is incremented by 1 (step S26), and it is determined whether the counter is 4 (step S28). At this time, if the counter is 4, the counter is returned to 0 (step S30), and the next 10-bit data is prepared for D / A conversion. The above steps S12 to S30 are performed until the D / A conversion is completed.

Although the commercially available 8-bit D / A converter is used to form the 10-bit D / A converter in the above embodiment, the resolution of the commercially available D / A converter and the number of divisions of the period T ( In principle, it is possible to construct a D / A converter with an arbitrary resolution by appropriately selecting 4 divisions in the above embodiment. For example, commercially available M-bit D
N-bit D / A converter (N
In the case of configuring <M), assuming that the maximum value represented by (N−M) bits is a, the period T is divided into a + 1 and the lower (NM) bits are divided by the same principle as in the above embodiment. 1 is added to the value of the upper M bits in the section for the value indicated by
Output to the converter.

[0026]

As described above, the D / A according to the present invention
According to the converter, by using the principle of pulse width modulation, a D / A converter having a higher resolution than that of the original commercially available D / A converter can be obtained with a simple circuit.
And it can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a D / A converter according to the present invention.

FIG. 2 is an explanatory diagram showing values input to a D / A converter 22.

FIG. 3 is a flowchart showing a procedure of a CPU 20 for decomposing 10-bit data into a sum of 8-bit data.

FIG. 4 is an explanatory diagram showing upper 8 bits Dh and lower 2 bits Dl of 10-bit data.

FIG. 5 is a circuit diagram showing a circuit configuration of a D / A converter by pulse width modulation (PWM).

[Explanation of symbols]

 20 ... CPU 22 ... 8-bit D / A converter 24 ... Integration circuit 26 ... Buffer circuit

Claims (1)

[Claims] 1. A decomposing the M-bit data so that the sum of 2 ^MN pieces of N-bit data, and processing means for outputting the 2 ^MN pieces of N-bit data sequence chronologically sequentially from the processing unit The output N-bit data is D /
A D / A converter comprising: an N-bit D / A converter that performs A conversion; and an integrating unit that integrates and averages the voltage signals sequentially output from the N-bit D / A converter.