JPH08116221A - Constant current circuit - Google Patents

Abstract

PURPOSE: To provide a constant current circuit whose power consumption is reduced by interrupting an Iref and also setting a bias voltage to zero in the standby state. CONSTITUTION: A current Iref flowing to the constant current circuit is interrupted and a bias voltage output Vbias is set to zero in the standby state in which no signal is received by an operational amplifier by 1st and 2nd switch circuits 3, 4, then bias currents I1,I2 of the operational amplifier and the current Iref are completely set to zero thereby attaining low power consumption. Furthermore, a switch control circuit 5 is used to control the on/off timing of the 1st and 2nd switch circuits 3, 4 to avoid direct connection of a resistor R between a point of a power supply voltage VDD and a ground in the case of changeover between the operating state and the standby state, then flowing of a rush current is avoided at changeover and low power consumption is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current circuit for supplying a bias voltage to an operational amplifier.

[0002]

2. Description of the Related Art FIG. 5 shows a general constant current circuit connected to an operational amplifier. In the figure, 10 is a conventional constant current circuit, and 20 is an operational amplifier. The constant current circuit 10 includes an N-type MOS transistor Mn whose gate is connected to its drain.
1 and a resistor R connected between the drain of the N-type MOS transistor Mn1 and the power supply voltage VDD. The resistor R has a transistor size (gate width and gate length) of the N-type MOS transistor Mn1 and a resistance value of the resistor R. The constant current Iref determined by
Bias voltage Vbias is output from the drain of
It is supplied to the operational amplifier 20. In the operational amplifier 20, the bias voltage Vbias is supplied to the gates of the N-type MOS transistors Mn13 and Mn14, and the N-type MOS transistors Mn13 and Mn14 are supplied with the bias voltage Vbias.
Bias currents I1 and I2 determined by the bias voltage Vbias flow through the transistors Mn13 and Mn14, respectively.

The currents Iref, I1 and I2 are reactive currents in a so-called standby state where no signal is input to the operational amplifier 20, and it is necessary to reduce these currents in order to reduce power consumption. As the method, a constant current circuit 10
The current path between the power supply VDD and the ground of
There is a method for reducing ref (Japanese Patent Laid-Open No. 4-23920).
8).

[0004]

However, since the method described in Japanese Patent Laid-Open No. 4-239208 cannot turn off the N-type MOS transistor Mn1, the bias voltage V
Since bias cannot be made lower than the threshold voltage of the N-type MOS transistor Mn1 and therefore the bias voltage Vbias supplied to the operational amplifier 20 does not become 0 (V), as a result, I1 and I2 can be made completely 0. There is a problem that you cannot do it.

The present invention provides a constant current circuit capable of reducing the current consumption of the constant current circuit and the bias current of the operational amplifier to substantially 0 in the standby state, resulting in low power consumption. With the goal.

[0006]

A constant current circuit according to claim 1, which is configured to achieve the above object, includes a MOS transistor having a gate connected to a drain and the drain serving as a bias voltage output terminal. A resistor whose one end is connected to the drain of the MOS transistor, and a resistor which is connected in series to one end of the resistor and which controls inflow and interruption of current to the resistor, and a resistor of the MOS transistor. A second switch circuit connected to the gate for controlling conduction or non-conduction of the MOS transistor and output or stop of the bias voltage;
And a switch control circuit for controlling the on / off timing of the first and second switch circuits.

A constant current circuit according to claim 2 configured to achieve the above object is the constant current circuit according to claim 1, wherein the MOS transistor has a gate connected to a drain and a source connected to ground. An N-type MOS transistor having the drain as a bias voltage output terminal, and the first switch circuit is a P-type MOS transistor having a source connected to a power supply voltage and a drain connected to one end of the resistor, The second switch circuit has a source connected to the ground and a drain connected to the gate of the N-type MOS transistor.
Type MOS transistor.

A constant current circuit according to claim 3 configured to achieve the above object is the constant current circuit according to claim 1, wherein the MOS transistor has a gate connected to a drain and a source connected to a power supply voltage. A P-type MOS transistor connected to the drain and serving as a bias voltage output terminal, and the first switch circuit is an N-type MOS transistor having a source connected to the ground and a drain connected to one end of the resistor; The second switch circuit has a source connected to the power supply voltage and a drain connected to the gate of the P-type MOS transistor.
Type MOS transistor.

The constant current circuit according to claim 4 configured to achieve the above object is the constant current circuit according to claim 1, wherein the first and second switch circuits output the bias voltage. When turning off the second switch circuit, the first switch circuit is turned on, and when stopping the output of the bias voltage, the first switch circuit is turned off and then the second switch circuit is turned on. Thus, the switch control circuit controls the on / off timing.

[0010]

According to the constant current circuit of the present invention configured as described above, the constant current circuit is configured by turning off the first switch circuit in a standby state in which no signal is input to the operational amplifier. The current to the resistor is cut off and the output of the bias voltage of the constant current circuit is stopped by turning on the second switch circuit, and the bias current flowing to the operational amplifier is cut off.

Further, when outputting the bias voltage, the first and second switch circuits turn off the second switch circuit and then turn on the first switch circuit to stop the output of the bias voltage. In this case, the switch control circuit controls the on / off timing so that the second switch circuit is turned on after the first switch circuit is turned off. There is no direct connection between the grounds and the generation of rush current when the first and second switch circuits are turned on and off is prevented.

[0012]

First Embodiment FIG. 1 shows a diagram in which a constant current circuit according to a first embodiment of the present invention is connected to an operational amplifier. In the figure, 1 is a constant current circuit of the present invention, and 20 is an operational amplifier. The constant current circuit 1 of the present invention is an N-type M in which the gate is connected to the drain.
OS transistor Mn1 and Mn1 at the drain of Mn1
Is a constant current part 2 made up of a resistor R connected in series, a first switch circuit 3 made up of a P-type MOS transistor connected to one end of the resistor R, and an N-type MOS transistor Mn.
N-type MOS transistor Mn2 connected to the gate of 1
Second switch circuit 4 and a signal S for controlling the on / off timing of the first and second switch circuits
The switch control circuit 5 outputs cnt1 and Scnt2.

Next, the operation will be described. Operational amplifier 2
In an operating state in which a signal is input to 0, the P-type MOS transistor Mp1 of the first switch circuit 3 is in the conductive state and the N-type MOS transistor M of the second switch circuit 4 is in the conductive state.
The switch control circuit 5 controls n2 to be in a non-conductive state. This causes a current to flow into the resistor R,
A constant current Iref determined by the transistor size (gate width and gate length) of the N-type MOS transistor Mn1 and the resistance value of the resistor R flows, and the bias voltage Vbias is supplied to the operational amplifier 20. As a result, the bias currents I1 and I2 flow through the operational amplifier 20, and the operational amplifier 20 is in the operating state.

On the other hand, in the standby state where no signal is input to the operational amplifier 20, the P-type MOS transistor Mp1 of the first switch circuit 3 is in the non-conducting state and the second switch circuit 4 is in the non-conductive state.
The N-type MOS transistor Mn2 is controlled by the switch control circuit 5 so that it becomes conductive. As a result, the current Iref flowing through the resistor R is cut off, and the N-type MO
The gate of the S transistor Mn1 is the second switch circuit 4
Since the N-type MOS transistor Mn2 is short-circuited to the ground, the N-type MOS transistor Mn1 becomes non-conductive and the bias voltage Vbias is 0.
(0V). As a result, the N-type MO of the operational amplifier 20
The S transistors Mn13 and Mn14 are turned off, and the bias currents I1 and I2 of the operational amplifier 20 are completely zero.

Next, the timing of switching between the operating state and the standby state will be described. In the constant current circuit of FIG.
When the operational amplifier 20 is operating, the P of the first switch circuit 3 is
When the type MOS transistor Mp1 is in the conductive state and the N-type MOS transistor Mn2 of the second switch circuit 4 is in the non-conductive state, the resistor R has a potential difference of VDD-Vbias,

[0016]

## EQU1 ## A constant current of Iref = (VDD-Vbias) / R flows. From this operating state, the P-type MOS transistor Mp1 of the first switch circuit 3 is in the non-conducting state,
N-type MOS transistor Mn2 of the second switch circuit 4
Is switched to a conductive state, the P-type MOS transistor Mp1 of the first switch circuit 3 and the N-type MOS transistor Mn2 of the second switch circuit 4 become conductive at the same time, and the resistor R turns on. If there is a direct connection between the voltage VDD and the ground, Mp1, M
Since the conduction resistance of n2 is designed to be sufficiently smaller than the resistance R, instantaneously,

[0017]

[Equation 2] The rush current flows to the resistor R and the consumption current increases.
In the constant current circuit of the present invention, the switch control circuit 5 is used to control the switching timing of the first and second switch circuits 3 and 4 so that such a rush current at the time of switching does not occur.

FIG. 2A shows a switch control circuit configuration 1
As an example, a timing chart of the output signal is shown in FIG. 2 (a) and 2 (b), 51 to 54 are inverter circuits, and 55 is a capacitor. When an input signal CNT for switching between the operating state and the standby state is input, FIG.
As shown in (b), the voltage at point a via the inverter circuits 51 and 52 rises and falls with a time constant determined by the output current capability of the capacitor 55 and the inverter circuit 52. If the threshold voltages of the inverter circuits 53 and 54 are Vt53 and Vt54, Vt53 <Vt54
Which constitutes the inverter circuits 53 and 54 so that
Determine the transistor size of the S-transistor.

In the switch control circuit 5 thus configured, when the input signal CNT for switching between the operating state and the standby state changes from the low level to the high level and the standby state is switched to the operating state, first, the second state. The signal Scnt2 for controlling the N-type MOS transistor Mn2 of the switch circuit 4 changes from high level to low level,
The N-type MOS transistor Mn2 becomes non-conductive and becomes N
Type MOS transistor Mn1 is turned on, and then the first
The signal Scnt1 for controlling the P-type MOS transistor Mp1 of the switch circuit 3 changes from the high level to the low level to bring the P-type MOS transistor Mp1 into the conductive state, and the current flows into the resistor R. Similarly, the operating state,
When the input signal CNT for switching the standby state changes from the high level to the low level and switches from the operating state to the standby state, first, the signal Scnt1 for controlling the P-type MOS transistor Mp1 of the first switch circuit 3 changes from the low level. It changes to the high level and the P-type MOS transistor M
The current flowing through the resistor R is cut off by making p1 non-conductive,
Next, the N-type MOS transistor M of the second switch circuit 4
The signal Scnt2 controlling n2 changes from the low level to the high level, the N-type MOS transistor Mn2 becomes conductive, the N-type MOS transistor Mn1 becomes non-conductive, and the bias voltage output Vbias becomes 0 (0V). . By controlling the switching timings of the first and second switch circuits 3 and 4 in this manner, the resistor R is not directly connected between the power supply voltage VDD and the ground, and as a result, the operating state and the standby state are switched. Sometimes rush current does not occur.

As described above, according to the constant current circuit of the present invention, the current Iref flowing through the constant current circuit is controlled by the first and second switch circuits 3 and 4 in the standby state where no signal is input to the operational amplifier. Since the bias voltage output Vbias can be set to 0 while being cut off, Ire
f and the bias currents I1 and I2 of the operational amplifier are completely zero.
Therefore, low power consumption can be achieved. In addition, the switch control circuit 5 controls the on / off timing of the first and second switch circuits 3 and 4, so that the resistor R is not directly connected between the power supply voltage VDD and the ground when switching between the operating state and the standby state. Therefore, rush current does not flow at the time of switching, and power consumption is further reduced.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention. FIG. 3 shows a P-type MOS transistor Mp2 as a MOS transistor forming the constant current portion 2, and an M forming a first switch circuit 3 for cutting off the current flowing through the resistor R.
N-type MOS transistor Mn3 as an OS transistor
Is an example in which a P-type MOS transistor Mp3 is used as a MOS transistor that constitutes the second switch circuit 4 that controls conduction and non-conduction of the P-type MOS transistor Mp2.

Also in the second embodiment, in the operating state in which a signal is input to the operational amplifier 20, the N-type MOS transistor Mn3 of the first switch circuit 3 becomes conductive,
P-type MOS transistor Mp3 of the second switch circuit 4
Are controlled by the switch control circuit 5 so as to be non-conductive. As a result, a current flows into the resistor R, a constant current Iref determined by the transistor size (gate width and gate length) of the P-type MOS transistor Mp2 and the resistance value of the resistor R flows, and the bias voltage Vbias is supplied to the operational amplifier 20. . As a result, the bias currents I1 and I2 flow through the operational amplifier 20, and the operational amplifier 20 is in the operating state.

On the other hand, in the standby state in which no signal is input to the operational amplifier 20, the N-type MOS transistor Mn3 of the first switch circuit 3 is in the non-conductive state, and the second switch circuit 4 is in the non-conductive state.
The P-type MOS transistor Mp3 is controlled by the switch control circuit 5 so that it becomes conductive. As a result, the current Iref flowing through the resistor R is cut off, and the P-type MO
The gate of the S transistor Mp2 is the second switch circuit 4
Power supply voltage VDD by the P-type MOS transistor Mp3 of
P type MOS transistor Mp2
Becomes non-conductive and the bias voltage Vbias
Is 0 (VDD). As a result, the P-type MOS transistors Mp23 and Mp24 of the operational amplifier 20 are turned off, and the bias currents I1 and I2 of the operational amplifier 20 are completely zero.

Next, the timing of switching between the operating state and the standby state will be described. Also in the second embodiment, the switch control circuit 5 is used to prevent the generation of the rush current at the time of switching, and the first and second switch circuits 3 and 4 are used.
The switching timing of is controlled. FIG. 4A shows an example of the configuration of the switch control circuit, and FIG. 4B shows a timing chart of its output signal. In FIG. 4, 61 to 6
3 is an inverter circuit, and 65 is a capacitor. When the input signal CNT for switching between the operating state and the standby state is input, the voltage at the point a via the inverter circuit 61 is a time constant determined by the output current capability of the capacitor 65 and the inverter circuit 61 as shown in FIG. 4B. Rising and falling are rounded. If the threshold voltages of the inverter circuits 62 and 63 are Vt62 and Vt63, then Vt62 <Vt63
To configure the inverter circuits 62 and 63 so that
Determine the transistor size of the S-transistor.

In the switch control circuit 5 configured as described above, when the input signal CNT for switching between the operating state and the standby state changes from the low level to the high level and the standby state switches to the operating state, first, The signal Scnt2 for controlling the P-type MOS transistor Mp3 of the switch circuit 4 changes from low level to high level,
The P-type MOS transistor Mp3 is turned off, and then the N-type MOS transistor Mn3 of the first switch circuit 3 is turned on.
The signal Scnt1 for controlling the signal changes from the low level to the high level to bring the N-type MOS transistor Mn3 into the conductive state, and a current is supplied to the resistor R. Similarly, the operating state,
When the input signal CNT for switching the standby state changes from the high level to the low level and switches from the operating state to the standby state, first, the signal Scnt1 for controlling the N-type MOS transistor Mn3 of the first switch circuit 3 changes from the high level. It changes to low level, and N-type MOS transistor M
n3 is made non-conductive to cut off the current flowing through the resistor R,
Next, the P-type MOS transistor M of the second switch circuit 4
The signal Scnt2 controlling p3 changes from the high level to the low level to make the P-type MOS transistor Mp3 conductive, the P-type MOS transistor Mp2 non-conductive, and the bias voltage output Vbias to 0 (VDD). By controlling the switching timings of the first and second switch circuits 3 and 4 in this manner, the resistor R is not directly connected between the power supply voltage VDD and the ground, and as a result, the resistor R No rush current is generated during switching.

In the first and second embodiments, the constant current section 2
A MOS transistor is used as the resistor forming
The conduction resistance may be used. Further, although the first and second embodiments have been described using the MOS transistor, it goes without saying that the same effect can be obtained even when the bipolar transistor is used.

[0027]

According to the constant current circuit of the first aspect of the present invention configured as described above, the switch circuit for controlling the flow and interruption of the current to the resistor forming the constant current circuit, and the bias supplied to the operational amplifier. A switch circuit that controls conduction and non-conduction of a MOS transistor that outputs a voltage and a switch control circuit that controls the switch circuits are provided. Then, in the standby state, the current of the constant current circuit and the bias current of the operational amplifier can be substantially zero, and as a result, a constant current circuit capable of reducing power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a constant current circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a switch control circuit in the constant current circuit of FIG.

FIG. 3 is a diagram illustrating a constant current circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a switch control circuit in the constant current circuit of FIG.

FIG. 5 is a diagram illustrating a conventional constant current circuit.

[Explanation of symbols]

 1 Constant Current Circuit 2 Constant Current Section 3 First Switch Circuit 4 Second Switch Circuit 5 Switch Control Circuit 10 Conventional Constant Current Circuit 20 Operational Amplifier 51-54 Inverter Circuit 61-63 Inverter Circuit 55, 65, C1 Capacitor R Resistors Mp1 to Mp3 P-type MOS transistors Mp11 to Mp13 P-type MOS transistors Mp21 to Mp24 P-type MOS transistors Mn1 to Mn3 N-type MOS transistors Mn11 to Mn14 N-type MOS transistors Mn21 to Mn23 N-type MOS transistors Scnt1, Scnt2 Switch control circuit Output signal Iref Current flowing in constant current circuit I1, I2 Bias current flowing in operational amplifier Vbias Bias voltage output of constant current circuit Vi−, Vi + Input terminal of operational amplifier Vo Output of operational amplifier Child

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H03K 17/687 (72) Inventor Haruyasu Sakishita 1-1, Showa-cho, Kariya city, Aichi prefecture Nidec Within the corporation

Claims (4)

[Claims] 1. A gate is connected to a drain, and
A MOS transistor having the drain as a bias voltage output terminal, a resistor whose one end is connected to the drain of the MOS transistor, and the resistor which is connected in series to one end of the resistor are configured to connect and disconnect a current to the resistor. A first switch circuit for controlling, and a gate of the MOS transistor,
A second switch circuit which controls conduction or non-conduction of the S transistor and output or stop of the bias voltage; and a switch control circuit which controls ON / OFF timing of the first and second switch circuits. A constant current circuit characterized in that 2. The MOS transistor is an N-type MOS transistor in which a gate is connected to a drain and a source is connected to ground, and the drain serves as a bias voltage output terminal. The first switch circuit has a source connected to a power supply voltage. P-type MO with the drain connected to one end of the resistor
The constant current circuit according to claim 1, wherein the constant current circuit is an S transistor, and the second switch circuit is an N-type MOS transistor having a source connected to the ground and a drain connected to the gate of the N-type MOS transistor. . 3. The MOS transistor is a P-type MOS transistor in which a gate is connected to a drain, a source is connected to a power supply voltage, and the drain serves as a bias voltage output terminal, and the first switch circuit has the source grounded. N-type MO with its drain connected to one end of said resistor
The constant current according to claim 1, wherein the constant current is an S transistor, and the second switch circuit is a P-type MOS transistor having a source connected to a power supply voltage and a drain connected to a gate of the P-type MOS transistor. circuit. 4. When outputting the bias voltage, the first and second switch circuits turn off the second switch circuit and then turn on the first switch circuit to stop the output of the bias voltage. 2. The constant current circuit according to claim 1, wherein the switch control circuit controls the on / off timing so that the first switch circuit is turned off and then the second switch circuit is turned on. .