JPH08115261A - Address conversion circuit - Google Patents

Abstract

PURPOSE: To generate a correct actual address corresponding to the page size of a hit entry in an address conversion circuit for storing plural address conversion pairs corresponding to the plural kinds of the page sizes. CONSTITUTION: Information relating to the page size stored in mask cells 12 and 14 in the entry which hit a virtual address inputted to a register 1, 4-1 for instance, is read to bit line groups B5 and B6 by hit signals R1 outputted by a sense amplifier 5 and transmitted to multiplexers 8 and 9. Thus, a value to be stored in the fields 7-2 and 7-3 of the register 7 for storing the actual address is appropriately switched to a part of the virtual address or a part of the address conversion pair.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion circuit using an associative memory, and more particularly to an address conversion circuit suitable when a plurality of page sizes are mixed in a virtual memory of an electronic computer.

[0002]

2. Description of the Related Art In recent years, the main storage capacity of electronic computers has been increasing due to the development of highly integrated semiconductor memory technology. Along with this, the range of storage capacity used by programs also increases, and small programs that can be executed with a very small storage capacity to huge programs that require a very large storage capacity are mixed in the same computer system. Started to run. In response to this, in order to improve the use efficiency of the main memory, a method in which a plurality of page sizes are mixed in the virtual memory has been adopted. In order to realize this method, it is necessary to change the range of address signals used for associative according to the page size, and a full associative associative memory that enables this has already been proposed. Specific examples of this type of technology include, for example, the technology disclosed in Japanese Patent Laid-Open No. 5-282877 and the technology disclosed in Japanese Patent Laid-Open No. 6-89588.

[0003]

As is well known, in an address conversion circuit for generating a real address from a virtual address, a virtual page number and an in-page offset ( The virtual page number is converted into a real page number using an associative memory, and the real address is generated by concatenating the converted real page number and the above-mentioned intra-page offset. In order to allow a plurality of page sizes to be mixed, information about the page size is stored in each entry of the associative memory, and the range of the virtual page number in the virtual address is determined based on this information and the associative search is performed. As a technique therefor, there is the above-mentioned conventional technique. However, in the above-mentioned conventional technique, a problem occurs when trying to connect the value read from the associative memory and the page offset in the virtual address. This is because the information about the page size of the virtual page that contains the input virtual address is in the entry that was hit in the associative search, and there is no method for extracting this information to the outside in response to the hit. . Therefore, it is difficult to realize an architecture in which a plurality of page sizes are mixed in order to improve the use efficiency of the main memory of the electronic computer only with the above-mentioned conventional technique. An object of the present invention is to provide an address conversion circuit that can generate a real address even when a plurality of page sizes are mixed when converting a virtual address into a real address.

[0004]

The above object of the present invention is to provide each entry with a different range of association by a virtual address according to the page size information corresponding to the entry, and the input virtual page number corresponds to the entry. In the address conversion circuit configured by using the associative memory that outputs the real page number stored in the data section of the entry in response to the coincidence signal indicating that the virtual page number stored in the tag section of the A means for outputting page size information in response to the match signal generated by the entry, and a bit in the real address to be generated which is a page offset or a page number depending on this page size information. In order to determine the group, the part of the data output from the associative memory that corresponds to this bit group or the address change A portion corresponding to the bit group of the virtual address input to the circuit is accomplished by providing means for selecting in response to the page size information that is output by the.

[0005]

In the address conversion circuit according to the present invention, the page size information stored in the entry hit in the associative search under the control of the page size information causes the virtual page of the virtual address corresponding to this entry to be detected. It is possible to know the size of each of the part that is the number and the part that is the offset within the page. Therefore, it is possible to know whether to assign the value read from the associative memory or the value input as the virtual address to each bit in the real address that should be generated, and correctly generate the real address. can do.

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.
Will be explained. FIG. 1 is a diagram showing the configuration of an address conversion circuit according to the first embodiment of the present invention. In FIG. 1, reference numerals 1, 2, and 6 are registers. The register 1 is composed of fields 1-1, 1-2, 1-3, 1-4 having a width of 12 bits, 4 bits, 4 bits and 12 bits, respectively. Register 2
Is composed of fields 2-1 and 2-2 each having a width of 1 bit. The register 6 is composed of fields 6-1, 6-2 and 6-3 each having a width of 12 bits, 4 bits and 4 bits. 3 is a decoder. Further, 4-1 to 4-n (n is a natural number) are entries for storing an address translation pair in the address translation circuit of the present invention, and 5 is an entry 4-.
A sense circuit (sense amplifier) for determining the result of the association in 1 and 7 are registers. The register 7 is composed of fields 7-1, 7-2, 7-3 and 7-4 having widths of 12 bits, 4 bits, 4 bits and 12 bits, respectively. 8 and 9 are multiplexers.

Further, in FIG. 1, 10, 11, and 13 in entry 4-1 are associative cell groups, 12 and 14 are maxcells for designating the associative range in entry 4-1, 15, 16, and Reference numerals 17 and 17 are memory cell groups, and 18 is an OR circuit. Line W1 is entry 4-1
Associated cell groups 10, 11, 13 and mask cell 1
2 and 14 are word lines for writing, line S1 is a sense line reflecting the association result in the associative cell group 10, 11, 13 of entry 4-1, and lines B1 to B3 and B5 to B9 are bit line groups. , RW1 are memory cell groups 15, 16,
17 is a word line for reading and writing. M1 and M2 are mask lines for transmitting the contents of the mask cells 12 and 14. R1 is the mask cells 12 and 14
Is a word line for reading the contents of

FIG. 2 is a diagram showing the internal structure of the mask cell 12 shown in FIG. W1, M1, R1 in FIG.
Are the word line W1 and the mask line M in FIG.
1 corresponds to the word line R1. Also, B5-P and B5
-N is a complementary bit line, and these are collectively shown as a bit line group B5 in FIG. Also, 101,
102, 105, 106 are NMOS transistors, 10
3 and 104 are inverters. The internal structure of the mask cell 14 has the same internal structure as the mask cell 12. Although the internal structure of the entry 4-1 has been described above as an example, the structures of the other entries also have the same internal structure as that of the entry 4-1.

Next, the address translation architecture in this embodiment will be described. The virtual address of the computer using the address conversion circuit shown in this embodiment is 32bi.
has a width of t. The page size, which is the unit for allocating virtual space to real memory, is 4KB, 64KB, and 1MB.
Are possible and these selections are possible on a page-by-page basis. Therefore, each entry of the address translation table provided in the main memory stores the information about the page size as well as the address translation pair for the page corresponding to the entry, and the address translation pair in the entry of the address translation table is stored. When is written in the address conversion circuit, information related to this page size is also written. The page size information above is encoded in a 2-bit value as follows: 11: 4KB 10: 64KB 00: 1MB 01: Do not use The high-order bit and low-order bit of the encoded value are
Mask cells 12 and 14 in this entry respectively
Is held.

Next, the operation of the address conversion circuit of FIG. 1 will be described. First, the write operation to this address conversion circuit will be described. In writing to the address conversion circuit, first, an entry designating signal for designating an entry to be written is input to the decoder 3 via the line L1. Then, the decoder 3 decodes the entry designating signal and asserts, for example, the word line W1. The entry designating signal can be easily generated by a conventional technique related to an electronic computer. At the same time, as the data regarding the address translation pair to be written into the designated entry 4-1, the virtual address is stored in the register 1 and the page size encoded into 2 bits is stored in the register 2 as described above. information,
A real address is set in the register 6. As a result, the bit line groups B1 to B9 are supplied with data relating to the address translation pair to be written in the entry. It should be noted that the generation of data relating to the address translation pair can be easily carried out by the conventional technology relating to electronic computers.

When the word line W1 is asserted, the contents of the fields 1-1, 1-2, and 1-3 of the register 1 in the associative cell groups 10, 11, and 13 in the entry 4-1, respectively, are bit It is written via the line groups B1 to B3. Associative cell groups 10, 11, 13 that perform such operations
Can be easily implemented in the prior art. Also, the mask cell 1
2 and 14 are the fields 2-1 and 2-2 of register 2 respectively.
Are written via the bit line groups B5 and B6, respectively. As a specific operation, for example, in the mask cell 12 shown in FIG.
Since the MOS transistors 101 and 102 are turned on, the signals applied to the bit lines B5-P and B5-N are stored in the loop including the inverters 103 and 104.

When the word line W1 is asserted, the OR circuit 18 in FIG. 1 asserts the word line RW1. Therefore, the memory cell groups 15, 16 and 17 have fields 6-1 and 6-2 of the register 6 respectively. , 6-3 are stored via the bit line groups B7, B8, B9, respectively.
The memory cell groups 15 to 17 which operate in this way are
It can be easily implemented with conventional techniques. Although information indicating whether the value written in the entry is valid or invalid is recorded in each of the entries 4-1 to 4-n of the address conversion circuit of the present embodiment, the associative memory of the prior art is used. Since it can be managed in the same way as above, it is not shown for simplicity.

Next, the address conversion operation in the address conversion circuit according to the present embodiment will be described by taking entry 4-1 as an example. In address translation, first, a virtual address to be translated is set in the register 1. The contents of the register 2 and the value of the register 6 may be arbitrary, but the contents are those of the mask cells 12 and 14 and the memory cell group 1.
It should be electrically disconnected from 5, 16 and 17.
Further, the entry designating signal is not input to the decoder 3, and therefore, no word line is asserted. As described above, the bit line groups B1, B2, and B3 are supplied with the signals corresponding to the virtual addresses stored in the fields 1-1, 1-2, and 1-3 of the register 1, respectively.

At this time, in the associative cell group 10, the stored content and the content of the signal input from the bit line group B1 are 1
If the bits are different, the sense line S1 is grounded. Also,
In the associative cell group 11, the stored content and the content of the signal input from the bit line group B2 are different by 1 bit or more,
In addition, when the stored content of the mask cell 12 transmitted to the associative cell group 11 through the mask line M1 is "1", the sense line S1 is grounded. Further, regarding the associative cell group 13, as in the case of the associative cell group 11, the stored content and the content of the signal input from the bit line group B3 differ by 1 bit or more, and the associative cell group on the mask line M2. When the stored content of the mask cell 14 transmitted to the memory cell 13 is "1", the sense line S1 is grounded. Associative cell group 1
In at least one of 0, 11, and 13, the sense line S
When 1 is grounded, the sense amplifier 5 outputs the value “0” indicating that the address translation pair corresponding to the input virtual address does not exist in the entry 4-1 on the line R1. To do. On the contrary, if the conditions for the sense circuit 5 to output “1” are summarized in consideration of the interpretation of the page size information stored in the mask cells 12 and 14,
One of the following: In the following, this condition will be referred to as a “condition for hitting in this entry”. (1) When the page size corresponding to the entry is 4 KB The upper 20 bits of the input virtual address matches the stored contents of the entry (2) When the page size corresponding to the entry is 64 KB The input virtual address Upper 16 bits match the stored content of the entry (3) When the page size corresponding to the entry is 1 MB The upper 12 bits of the input virtual address match the stored content of the entry

Although the associative operation has been described above by taking the entry 4-1 as an example, the same operation is performed for the other entries. Further, as in the prior art, since it is assumed that the address translation pair corresponding to one virtual address is managed so as not to be registered in a plurality of entries of the address translation circuit, the sense line S1 or the like which is not grounded is sensed. There is at most one line. As mentioned above,
The associative memory capable of changing the comparison range of the input virtual address and the value stored in each entry according to the information related to the page size provided in each entry is easily configured by the conventional technology. It Now, in the above description, for example, when the condition for hitting the entry 4-1 is satisfied and the sense circuit 5 outputs the value "1" to the line R1, the OR circuit 18 sends the value "1" to the word line RW-1. As a result, the values stored in the memory cell groups 15, 16 and 17 are output to the bit line groups B7, B8 and B9, respectively. The value output to the bit line group B7 is stored in the field 7-1 of the register 7.

In parallel with this, mask cells 12 and 1
4, a read signal is input via R1. Then, the mask cell 12 becomes the NMOS transistor 1 of FIG.
05 and 106 are turned on, and the inverters 103 and 1
The value stored in the pair 04 is output to bit line group B5 (comprising complementary bit lines B5-P and B5-N). Similarly, the mask cell 14 also stores the stored contents in the bit line group B.
6 is output. The values output to bit line groups B5 and B6 are input to multiplexers 8 and 9, respectively. The multiplexer 8 outputs the value input from the bit line group B8 when the stored content of the mask cell 12 input from the bit line group B5 is “1”, and the mask cell 1
When the stored content of 2 is "0", a part of the virtual address set in the field 1-2 of the register 1 is output via B2. The output value is stored in the field 7-2 of the register 7. In the multiplexer 9, the stored content of the mask cell 14 input from the bit line group B6 is "1".
If it is, the value input from the bit line group B9 is output, and if the storage content of the mask cell 14 is "0", the virtual address set in the fields 1-3 of the register 1 via B3. Output a part of. The output value is stored in the field 7-3 of the register 7. In the field 7-4 of the register 7, the register 1 is connected via the line DD.
Part of the virtual address set in fields 1-4 of is stored.

The values stored in each field of the register 7 by these operations are summarized as follows in consideration of the interpretation of the information about the page size stored in the mask cells 12 and 14. (1) When the page size corresponding to the entry is 4 KB Field 7-1: Stores the value stored in memory cell group 15 Field 7-2: Stores the value stored in memory cell group 16 Field 7 -3: Stores the value stored in memory cell group 17 Field 7-4: Stores the value set in field 1-4 The real address in this case is set in fields 7-1 to 7-3 The value corresponds to the real page number and the value stored in fields 7-4 corresponds to the in-page offset. (2) When the page size corresponding to the entry is 64 KB Field 7-1: Stores the value stored in memory cell group 15 Field 7-2: Stores the value stored in memory cell group 16 Field 7 -3: Store the value set in field 1-3 Field 7-4: Store the value set in field 1-4 The real address in this case is the value set in fields 7-1 to 7-2 Corresponds to the real page number, and the values stored in fields 7-3 to 7-4 correspond to the in-page offset. (3) When the page size corresponding to the entry is 1 MB Field 7-1: Stores the value stored in memory cell group 15 Field 7-2: Stores the value set in field 1-2 Field 7- 3: Stores the value set in fields 1-3 Field 7-4: Stores the value set in fields 1-4 In this case, the real address is the value set in field 7-1 as the real page number. , The values stored in the fields 7-2 to 7-4 correspond to the in-page offset.

Therefore, in either case, the address conversion is correctly performed according to the information about the page size. The above is the description of the first embodiment of the present invention. According to the present embodiment, it is possible to construct an address conversion circuit capable of obtaining a real address from a virtual address even when a plurality of page sizes are mixed, and the object of the present invention is achieved. The associative cell groups 10, 11,
By changing the number of associative cells included in 13, 32
It is obvious that a virtual address other than the bit width and a page size different from that of this embodiment can be easily dealt with.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. Since the second embodiment of the present invention is a modification of the first embodiment of the present invention, the differences will be mainly described. FIG. 3 is a diagram showing the configuration of the address conversion circuit according to the second embodiment of the present invention. In FIG. 3, each component referred to by the same reference numeral as in FIG. 1 has the same configuration and function as in the first embodiment. In FIG. 3, 34-1 through
34-n (n is a natural number) is an entry for storing an address translation pair in the address translation circuit of this embodiment, and corresponds to 4-1 to 4-n in the first embodiment. Reference numerals 23 and 24 denote mask cells. The mask cells shown in FIG.
6, and the signal line R1 input to the mask cell from the sense circuit 5 is deleted. Further, 21 and 22 are 1-bit memory cells, respectively, which may be the same as the memory cells of the prior art. Although the internal structure of the entry 34-1 has been described above, other entries such as the entry 34-n also have the same internal structure as the above-mentioned entry 34-1. The address translation architecture in this embodiment is the same as in the first embodiment.

Next, the operation of the address conversion circuit of the second embodiment will be described. First, the write operation to the address conversion circuit will be described. In writing to the address conversion circuit, first, an entry designating signal for designating an entry to be written is input to the decoder 3 via the line L1. Then, the decoder 3 decodes the entry designating signal and asserts, for example, the word line W1. The entry designating signal is generated by
It can be easily implemented by a conventional technique related to an electronic computer. At the same time, a virtual address is encoded in register 1 and 2 bits in register 2 as data relating to the address translation pair to be written to the designated entry 34-1, as in the first embodiment. The information about the page size is set in the register 6 as a real address.

When the word line W1 is asserted, the contents of the fields 1-1, 1-2, 1-3 of the register 1 are written in the associative cell groups 10, 11, 13 in the entry 34-1 respectively. Further, the contents of the fields 2-1 and 2-2 of the register 2 are written in the mask cells 23 and 24, respectively. Further, when the word line W1 is asserted, the word line RW1 is asserted via the OR circuit 18 in FIG. 1, so that the memory cell groups 15, 16 and 17 have fields 6-1 and 6-2 of the register 6 respectively. , 6-3 are stored via the bit line groups B7, B8, B9, respectively. Furthermore, the memory cell 2 newly provided in the present embodiment
1 and 22 include bit line groups B10 and B, respectively.
Via register 11, fields 2-1 and 2-2 of register 2
Is stored. That is, the same values as the values written in the mask cells 23 and 24 are stored in the memory cells 21 and 22, respectively.

Next, the address conversion operation in the address conversion circuit according to this embodiment will be described by taking the entry 34-1 as an example. In address translation, first, a virtual address to be translated is set in the register 1. Then, in the same manner as in the first embodiment except that the mask cells 23 and 24 operate instead of the mask cells 12 and 14 in the first embodiment, when the sense line S1 is grounded, the sense circuit The (sense amplifier) 5 outputs the value "0" or the value "1" to the line R1 under the same conditions as in the first embodiment. Although the associative operation has been described above by taking the entry 34-1 as an example, the same operation is performed for other entries.

Here, for example, when the condition for hitting the entry 34-1 is satisfied and the sense amplifier 5 outputs the value "1" to the line R1, the OR circuit 18 outputs the word line RW-1.
Send the value "1" to. Thereby, the memory cell groups 15, 1
The values stored in 6 and 17 are the bit line groups B7 and B7, respectively.
It is output to B8 and B9. Further, in this embodiment, the values stored in the memory cells 21 and 22 at the same time are output to the bit line groups B10 and B11, respectively. The values output to the bit line groups B10 and B11 are
Input to multiplexers 8 and 9, respectively. The multiplexer 8 outputs the value input from the bit line group B8 when the storage content of the mask cell 12 input from the bit line group B10 is "1", and the storage content of the mask cell 12 is "0". In this case, a part of the virtual address set in the field 1-2 of the register 1 is output via the bit line group B2. The output value is stored in the field 7-2 of the register 7. The multiplexer 9 outputs the value input from the bit line group B9 when the storage content of the mask cell 14 input from the bit line group B11 is “1”, and the storage content of the mask cell 14 is “0”. In this case, a part of the virtual address set in the fields 1-3 of the register 1 is output via the bit line group B3. The output value is stored in the field 7-3 of the register 7. The field 7-4 of the register 7 stores a part of the virtual address set in the fields 1-4 of the register 1 via the line DD. Here, the memory cell 21
The values stored in 22 and 22 are mask cells 23 respectively.
Considering that they are the same as the values stored in 24 and 24, it will be easily understood that the values stored in the respective fields of the register 7 by the above operation are exactly the same as those in the first embodiment. Therefore, the address conversion is correctly performed according to the information about the page size.

The above is the description of the second embodiment of the present invention. According to the present embodiment, in addition to the effect of the first embodiment, the present invention can be realized without using a special memory cell (illustrated in FIG. 2) necessary for realizing the first embodiment. The effect is that the purpose can be achieved. Note that associative cell group 1
By changing the number of associative cells included in 0, 11, and 13, it is possible to easily cope with virtual addresses other than the 32-bit width and page sizes different from this embodiment, as compared with the first embodiment. It is the same.

[0025]

According to the present invention, when converting a virtual address into a real address, it is possible to easily obtain an address conversion circuit capable of generating a real address from a virtual address even if a plurality of page sizes are mixed. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an address conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a mask cell introduced when configuring the address conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an address conversion circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1, 2, 6, 7: Register 3: Decoder 4-1 to 4-n: Entry 5: Sense circuit (sense amplifier) 8 to 9: Multiplexer 10, 11, 13: Associative cell group 12, 14, 23, 24 : Mask cell 15 to 17: memory cell group 18: OR circuit 21, 22: memory cell 101, 102, 105, 106: NMOS transistor 103 to 104: inverter W1, R1: word line S1: sense line RW1: word line B1 B11: Bit line

Claims (4)

[Claims] 1. An address conversion circuit using an associative memory for storing a plurality of entries, associatively searching for a corresponding real address by an inputted virtual address, and transmitting the same, wherein N is an arbitrary integer of 2 or more, J is an integer not less than 2 and not more than N, the virtual address is composed of N + 1 fields from the first to N + 1th, and the real address is composed of N + 1 fields from the first to N + 1. Each entry is composed of a tag part, a data part and a mask part, the tag part is composed of N fields from the first to the Nth, and the data part is composed of N fields from the first to the Nth. The mask part is composed of N-1 bits from the second to the Nth, and in each entry, the first field of the virtual address and the first field of the tag part are included.
The fields are compared, and the J field of the virtual address is compared with the J field of the tag section only when the J bit of the mask section stores a value indicating that the fields are comparable. When a match is detected in all the fields actually compared in the comparison, a match detection signal for the entry is generated, and the values stored in the first to Nth fields of the data part of the entry are changed to An associative memory which is sent as the first to Nth fields of the real address, respectively, and stored in the second to Nth bits of the mask section in response to the match detection signal generated in the entry of each entry. The read values to the outside of the associative memory as second to Nth mask output signals, respectively, and To the Nth to Nth mask output signals, respectively, one of the values of the second to Nth fields of the real address and the values of the second to Nth fields of the virtual address transmitted from the associative memory Selecting means for selecting and outputting as the value of the second to Nth fields of the converted real address; the first field of the real address sent from the associative memory; and the converted after being selected and outputted by the selecting means. An address conversion circuit comprising means for combining the second to Nth fields of a real address and the (N + 1) th field of an inputted virtual address to obtain a real address after translation. 2. The address conversion circuit according to claim 1, wherein the read means is the second to Nth mask sections.
An address conversion circuit comprising a MOS transistor for transmitting the stored content of a bit to a bit line connected to each bit in response to the coincidence detection signal. 3. An address conversion circuit using an associative memory for storing a plurality of entries, associatively searching for a corresponding real address according to an input virtual address, and transmitting the associative memory, wherein N is an arbitrary integer of 2 or more, J is an integer not less than 2 and not more than N, the virtual address is composed of N + 1 fields from the first to N + 1th, and the real address is composed of N + 1 fields from the first to N + 1. Each entry is composed of a tag part, a data part and a mask part, the tag part is composed of N fields from the first to the Nth, and the data part is composed of N fields from the first to the Nth. The mask part is composed of N-1 bits from the second to the Nth, and in each entry, the first field of the virtual address and the first field of the tag part are included.
The fields are compared, and the J field of the virtual address is compared with the J field of the tag section only when the J bit of the mask section stores a value indicating that the fields are comparable. When a match is detected in all the fields actually compared in the comparison, a match detection signal for the entry is generated, and the values stored in the first to Nth fields of the data part of the entry are changed to An associative memory which is sent as the first to Nth fields of the real address, respectively, and the same value as the value stored in the second to Nth bits of the mask section of the entry is stored in the data section of each entry. N + 1 fields from the (N + 2) th to the (N + N) th fields are newly provided, and the (N + 2) th to the (N + N) th fields of the data section are newly provided. N + 2 to N + N for outputting the value stored in the field
Fields are newly added to the output data, and the values of the second to Nth fields of the real address and the second to Nth fields of the virtual address are provided in response to the N + 2 to N + N fields of the output data, respectively. Selection means for selecting and outputting one of the values, the first field of the real address sent from the associative memory, the second to Nth fields of the real address selected and outputted by the selection means, and And a means for combining with the (N + 1) th field of the virtual address to be converted into a real address after conversion. 4. The address conversion circuit according to claim 3, wherein when writing data to the second to Nth bits of the mask section, the (N + 2) th to (N + N) th of the data section are written.
The address conversion circuit is characterized in that the same value is written in each field.