JP2728434B2 - Address translation device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation device for translating a logical address into a physical address, and is particularly suitable for a virtual storage system that handles multitasking in a microcomputer system. The present invention relates to an address translation device.

2. Description of the Related Art Conventionally, in a virtual storage system that handles multitasking in a microcomputer system, address conversion and checking of a memory access right for memory protection are important functions of memory management. Therefore,
The address conversion is to convert a logical address (hereinafter, referred to as a logical address) specified by a certain task being executed into a physical address (hereinafter, referred to as a physical address) on a real memory. Checking memory access rights means that the memory area at that physical address is allocated to that memory area if it is a memory area that is uniquely allocated to other accesses, and therefore should not be accessed by the task. The check is based on the memory protection level and the memory access right level assigned to the task. In a microcomputer, an address translation device that performs both address translation and memory access right checking has already been used. About this, for example, Computer Design, Vol.25, No.19,
October 15, 1986, pages 21 to 30 (Computer Design,
Vol.25, No.19, Oct.15, 1986, pp.21-30).

As described later in detail, in the conventional address translation device, the address translation and the check of the memory access right are sequentially performed.

[Problems to be Solved by the Invention] In the above-described conventional technology, the time required to acquire a valid physical address for the sequential operation is longer than the time required for address translation by the time required for memory access right check.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an address translation device capable of performing address translation and memory access right check in parallel.

[Means for Solving the Problems] For this reason, in the present invention, the address conversion circuit includes a memory (814A) for storing a plurality of physical addresses, and a plurality of signal pairs corresponding to the plurality of physical addresses. Stores a pair of a logical address corresponding to one of the plurality of physical addresses and memory protection level data indicating a memory protection level assigned to a memory location of the one physical address, and performs address conversion. Logical address to be provided, and mask data for indicating whether each bit of the stored memory protection level data is to be searched, and a memory access right level assigned to a program requesting address conversion. And the comparison data to be compared with each of the stored memory protection level data. A signal pair having a logical address that matches the logical address to be dress-converted and memory protection level data that matches the comparison data at the bit position indicated as the hit position to be searched by the mask data. An associative memory (810A) for instructing the memory to search and output a physical address corresponding to the detected signal pair.

[Operation] To check the memory access right for memory protection, the memory access right level assigned to the program (eg, task) is assigned to the memory area of the physical address obtained as a result of the address conversion. It is necessary to determine whether it is below (or above) the protection level. The present invention uses an associative memory to perform this determination using an associative memory. For this reason, in the present invention, by devising the data expression of the data representing the memory protection level and the data representing the memory access right level, one or a plurality of memory protection level data accessible at a certain memory access right level are obtained. All utilize the fact that it has a specific value at a specific bit position determined by the memory access right level.

That is, in the present invention, the associative memory also stores the memory protection level assigned to the memory area of the physical address obtained after the address conversion, and indicates the above position by a mask signal, and the associative memory compares only the bit position. Memory and the memory protection level data stored in advance can be determined, so the associative memory is
A match signal is output for a signal pair of a logical address that matches the input logical address and one of one or a plurality of memory protection level data accessible at the memory access right level. Therefore, it is guaranteed that the memory protection level assigned to the physical address obtained by the address conversion is accessible at the memory access right level assigned to the program being executed. Of course, in the above description, the coincidence detection of the logical address and the coincidence detection of the memory protection level data and the memory access right level data at the bit position of the patent are performed in the same associative memory. You can do it.

[Example] Prior to description of an example, a conventional technique will be described in detail.

In FIG. 8, reference numeral 12 denotes a level register which holds the memory access right level data MAL allocated to the task being executed, 13 denotes an LA register which holds a logical address LA to be converted, and 15 denotes a physical address obtained by the conversion. address
An output register holding PA, 11 is a mask register holding mask data specifying a bit position to be associatively searched for the associative memory 810, 82 is a memory location of a converted physical address, which is accessed by a task being executed. Is a memory access right level check circuit for checking whether the memory access right has an allowable memory protection level. Other elements constitute an address translation buffer (hereinafter referred to as TLB) 81 for translating a physical address into a corresponding logical address.

TLB81 is the upper bits LA-1, LA of multiple logical addresses
-2, ...... LA-n associative memory 810 searching for a logical address that matches the input logical address
And the upper bit portions PA-1, PA-2,..., PA-n of the physical addresses respectively corresponding to the logical addresses.
, And MPL-n, which are memory protection level data MPL-1, MPL-2,..., MPL-n allocated to each physical address.

The associative memory 810 includes a memory unit 812, a decoder 811, a control unit 8
Consists of ten. Each bit (mask bit) of the mask data in the mask register 11 is provided corresponding to each bit of the logical address part LA-u in the LA register 13. If the value of a certain mask bit is 1, the corresponding bit of the upper bit part LA-u of the logical address LA and the stored logical address LA-1, L
A-2,... Are instructed to the associative memory 810, and the value of the mask bit instructs the associative memory 810 to invalidate the comparison and always assume that they match.

In this conventional technique, a bit string “11...” Of value 1 is stored as the mask data. Therefore, in this conventional example, the associative memory 810 is instructed to compare all the bits of the upper bit portion LA-u of the logical address LA.

The decoder 811 outputs the upper bit portion LA-u of the logical address.
., 811-m to which a pair of one of the bits and a corresponding mask bit is input. Each partial decoder stores two signals for search, which change depending on a combination of two input signals, in the memory unit 812.
Give to.

Next, the operation of FIG. 8 will be described with reference to the time chart of FIG. The operation consists of two stages of address conversion and memory access right check as shown in FIG.

(1) Address conversion stage In associative memory 810, upper bit portion L of logical address LA
Search for a logical address that matches Au. 815 is a group of bit lines provided corresponding to each entry of the memory unit 812 of the associative memory 810.

The memory unit 812 stores a logical address, for example, LA-i (i = 1, 2,... Or n) corresponding to the upper bit part LA-u of the logical address.
Is output (hit entry), 1 is output to the hit line corresponding to that entry, and 0 is output to the hit lines corresponding to the other entries.

If there is no hit entry, the signal of the hit line group 815 is input.
18 becomes 1 and this signal is notified to a micro control unit (not shown) of a microcomputer (not shown) as a mishit signal.

If there is a hit entry, the RAM 814 responds to the signal of the value “1” on the hit line corresponding to the entry,
The high-order bit part PA-i of the physical address corresponding to the hit line and the memory protection level MPL-i are output.

(2) Memory access right level check The check circuit 82 checks the memory protection level data MPL-
The memory access right is checked by comparing i with the memory access right level data MAL held in the level register 12 and assigned to the running task that generated the logical address LA.

Prior to the description, the relationship between the memory access right level data and the memory protection level data will be described. The memory access right is divided into several levels, and the memory protection level is also divided into the same number of levels as the memory access right level.

If the total number of each of the memory access right level and the memory protection level is 4, each of them is 10A
As shown in the drawing, the data is represented by any one of binary data 00, 01, 10, and 11. Generally, assuming that the total number of each of the memory access right level and the memory protection level is 2 ^P (P: integer), the memory access right level and the memory protection level take one of the values 0 to 2 ^P −1. It is represented by P-bit binary data. That is, the level data for the level of the number k is 2 having the value k.
Hexadecimal data. The memory access right level is higher as the value is smaller, and a task satisfying memory access right level ≦ memory protection level can have access right to the memory. FIG. 10B shows memory access right level data and memory protection level data that can be accessed by the four levels. In this conventional example, the level number and the value of the level data match.

Therefore, in the check circuit 82, the memory protection level data MPL-i read from the RAM 814 and the level register 1
It is determined whether or not the above condition is satisfied for the memory access right level data MAL held in step 2.If this condition is not satisfied, it is determined that the upper bit portion PA-i of the physical address is inaccessible due to the task. , And outputs an access right check error signal 821 to a micro control unit (not shown). When this signal 821 is not output, the upper bit portion PA-i of the physical address and the lower bit portion LA of the logical address LA held in the LA register 13 are output.
-L is set in the output register 15, and the contents of the register are used as the physical address PA after the address conversion.

In the prior art described above, address translation and memory
Perform access right check sequentially. For this reason, it takes extra time for the memory access right check to acquire a valid physical address. In particular, when the number of entries in the TLB 81 increases, the time required for searching for the logical address LA increases, and one cycle is required only in the address translation stage. Therefore, the memory access right check is 2
Deviated at the cycle, 2 to obtain a valid physical address
Cycle required.

To perform high-speed address translation in a large-scale TLB, the limitations of the conventional method are visible. An object of the present invention is to solve the above problem by simultaneously performing address conversion and memory access right check.

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, with reference to FIG. 2, the internal configuration of a microprocessor 2 incorporating an address translation device 1 according to the present invention will be described. The microprocessor 2 is a coprocessor activated by a signal from a host processor (not shown), and a micro instruction is a basic unit of the instruction. Microprocessor 2 is a micro read only
It comprises a memory (hereinafter referred to as a micro ROM) 21, a micro control unit 22, an arithmetic unit 23, an address conversion device 1, and a bus control unit 24. Internal data bus 16 as internal bus, external address bus as external bus
17, has an external data bus 25. The unit 21 stores a micro program for controlling another unit, and the unit 22 controls the micro program based on information from the other unit. The unit 23 holds in the register file 231 logical addresses to be input to other address translators for executing various operations. Address translation device 1
Performs the address conversion and the memory access right check in parallel, and sends the physical address obtained by the conversion to the external memory 26 via the external address bus 17. The bus control unit 24 is connected to the external address bus 17 and the external data bus.
The bus 25 is controlled. In FIG. 2, the present invention is characterized in that the address translation device 1 is configured to perform the address translation and the memory access right check in parallel in one machine cycle.
Is stored in the register file 231, and the microprogram in the micro ROM 21 performs the address conversion and the memory access right check in the same cycle with the speeding up of the address conversion device 1 described above. That is to do it.

Next, the structure of the address translator 1 will be described with reference to FIG.

In FIG. 1, the same reference numerals as those in FIG. 8 denote the same parts, and the differences between FIG. 1 and FIG. 8 are as follows.

The RAM 814A constituting the TLB81A stores only the upper bit portions PA-1 to PA-n of each of a plurality of physical addresses,
The memory portion 812A of the associative memory 810A constituting the B81A includes upper bits LA-1 to LA-n of a logical address corresponding to each physical address and a memory protection level assigned to each physical address. Data MPL-1 to M
PL-n is stored in pairs. Memory protection level data of the memory unit 812A as a decoder of the associative memory 810A
A decoder 811A is provided for a part storing MPL-1 to MPL-n. This decoder uses the memory protection level MPL-
.. Or MPL-n. Each of the partial decoders 811A-1 to 811A-3 is provided corresponding to each bit position. These partial decoders have the same structure as the partial decoders 811-1 to 811-m in the decoder 811. Each of the partial decoders includes one bit of data in the level register 12 and a mask register 11A newly provided in the present invention.
The corresponding bit in the mask data MSK is input. In the level register, a 3-bit 1 column is set as comparison data regardless of the memory access right level of the task being executed. This mask data MS
K has the same number of bits as the number of bits of the comparison data in the level register 12. When the value of a certain bit of the mask data MSK is 1, the associative memory 810A instructs the associative memory 810A to perform a comparison for a match search for the bit of the comparison data in the level register 12 corresponding to the bit. When the value of the bit is 0, the associative memory indicates that the comparison should not be performed for the bit of the comparison data in the level register corresponding to the bit position, and that a match should be obtained for the bit. 81
Although the mask register 11A is used for the same purpose as the mask data in the mask register 11 in the point of designating 0A, a certain bit of the mask data can be 0 in the present embodiment, unlike the conventional example. That is, this mask data MSK
Is equal to the memory access right level data assigned to the task that has requested the address translation. The memory access right level data and the memory protection level data used in the present invention are different from the conventional example.

Hereinafter, the two level data will be described. No.
As shown in FIG. 3A, when the total number of levels is 4, both the memory access right level data and the memory protection level data have i bits or bit strings of value “1” at the beginning of each at the level number i. 3 bit data. More generally, when the total number of levels is k, each of the above two types of level data has, for level 1, k−1 bits having 1 value “1” or a bit string at the head thereof. Expressed by bit data.

Similar to the conventional example, the memory protection level of a memory area accessible by a certain memory access right level is lower than the former level. Accordingly, the memory protection level data of the memory area accessible by the memory access right shown in FIG. 3A is as shown in FIG. 3B.

That is, the memory protection level data of the memory area accessible by a certain memory access right level data includes a bit position (a bit position circled in FIG. 3B) corresponding to the bit position of the former value “1” and a value 1 The values of the other bit positions may be different from the corresponding data values of the former. In other words, by checking whether the value of a certain memory protection level data is 1 for all bits of the value “1” of a certain memory access right level data, the memory area to which the memory protection level data is given is stored in that memory. It is possible to determine whether or not the access right level data is accessible. According to the same determination method, when the values of all the bits are 0 as in the level data for the memory access right level 0, it can be understood that the level data may access all the memory protection levels.

The embodiment of FIG. 1 utilizes this fact, and sets, as mask data in the mask register 11A, the same data as the memory access right level data allocated to the task which has requested the address translation as mask data. By setting a bit string having a value of "1" in the level register 12, the associative memory 810A stores the level data value in only one or a plurality of bit positions of the memory protection. Level data MPL-1
... MPL-n is determined to match the value “1” in the level register 12, and this determination is not performed for other bit positions. If the memory protection level data MPL-i in which a match is detected at all of the one or more bit positions is detected, it can be determined that the data is accessible with the memory access right level data. .

As is clear from the above, since the data to be set in the level register 12 only needs to be the value 1 for the bit of the value 1 of the mask data MSK, the comparison data in the level register 12 has the same memory access right as the mask data MSK. The level data itself may be used. More generally, it is only necessary to have the value 1 at the same bit position as the bit of each memory access right level data value 1. In this embodiment, a bit string of all "1" is used as the simplest data. This is because this is the simplest data used for any memory access right level data.

As described above, the present invention detects whether or not there is memory coefficient level data that matches at one or more specific bit positions of the memory access right level data, so that the memory access right level data can be accessed. This makes it possible to detect good memory protection level data.

Hereinafter, the operation of the apparatus of FIG. 1 will be described with reference to the time chart of FIG.

In response to the all-ones bit string in the mask register 11, the decoder 811 outputs the logical address LA in the LA register 13.
The decoder 811A sends a signal corresponding to the value of each bit of the upper bit portion of the mask data MSK in the mask register 11A to the level register 12 for the bit of value 1 in the mask data MSK in the mask register 11A. The value of the corresponding bit position in
Is transmitted to the memory unit 812A, and the mask data
For the bit of the MSK value 0, a signal for invalidating the comparison operation is sent to the memory unit 812A regardless of the value (“1”) of the corresponding bit position in the level register 12. Memory unit 812A
Responds to the outputs of the decoders 811, 811A,
The logical address upper bit part LA-u that matches the upper bit part of the logical address LA and the logical address upper bit part LA-u that matches the value 1 in the level register 12 other than the bit position where the signal invalidating the comparison operation is input When there is an entry having the memory protection level data MPL-i having the corresponding bit, "1" is output to one of the hit line groups 815 corresponding to the entry, and the RAM 814A stores the entry corresponding to this hit line. Output the physical address PA-i. this is,
Combined with the logical address lower bit portion LA-L in the LA register 13, it is set in the output register 15 as a physical address PA and sent to the external memory 26 via the external address bus 17. If there is no hit entry, the gate 813 outputs a mishit signal to the microcontroller 22 unit (FIG. 2). FIG. 5 shows a partial decoder 811A.
-3 and the memory cell 51 are shown. Other partial decoder 811-1
81811-m and 811A-111811A-2 also have the same structure as the partial decoder 811A-3. Other memory cells 51 in the memory unit 812A
Has the same structure as The partial decoder 811A-3 includes an inverter circuit 500 and AND circuits 501 and 502. 121a
Is the number of signals to which one bit ("1") of the level register 12 is input, and 112a is a signal line to which one mask bit of the mask register 11 or 11A is input. 503 is a signal line for inputting the address data enable signal ADE from the control unit 140. When the signal on the signal line 112a is 1, the partial decoder 811A-3 connects to the word lines 145a and 146a,
A signal equal to the signal on the input line 121a and a signal obtained by inverting the signal are output. On the other hand, when the signal on the signal line 112a is 0, the above signals on the word lines 145a and 146a are both set to "0".

The memory cell 51 is a circuit composed of an nMOS transistor, and is connected to a word line 145a, a two-stage circuit 505 connected to a hit line 149a provided corresponding to the memory cell, and a word line 146a and a hit line 149a. 2
It comprises a latch composed of inverter circuits 507 and 508 connected to the stage circuit 506 and the two-stage circuits 505 and 506. In this memory cell, a signal is stored in the signal line 511, and the potential value of the signal line 511 corresponds to the value of the stored data.

Hereinafter, a case where the memory cell 51 holds the least significant bit of the memory protection level data MPL-1 in the uppermost entry of the memory unit 812A will be described with reference to FIGS. 6A to 6c. Will be described. The operation of the memory cell is as follows: (a) the case where the information of the memory cell is compared with the signal of the signal line 121a, the result is a match; (b) the case where the comparison is invalidated; It consists of three cases.

(A) Case where the result of comparison is a match (Fig. 6A) This case is the case where the mask data M in the mask register 11A is
This occurs when SK is “111” and the memory protection level data in the memory unit 812A is “111”. That is, in this case, the signal line 112a is “1” and the memory protection level data MPL-
This occurs when the signal value of the signal line 511 having the signal level indicating the least significant bit of 1 is “1”.

The first hit lines 149a, charge is accumulated from the power supply 153 before the cycle T ₃ through T ₄ address conversion cycle. This is called precharge. Next, when the signal ADE503 becomes “1” in the address translation cycle from T _{1 to} T ₂ , the signal line 112
Since both a and 121a are “1”, the word line 145a connected to the output of the AND circuit 501 becomes “1”. The word line 146a that has not been connected to the output of the AND circuit 502 becomes “0” because the output of the inverter 500 becomes “0”. At this time, the nMOS two-stage circuit 50
5,506 becomes non-conductive and the charge of the hit line 149a is maintained. The nMOS two-stage circuit 505 becomes non-conductive because
Since the signal on the signal line 511 is “1”, the nMOS gate input line 514
Is "0" and the ground-side nMOS becomes non-conductive. Similarly, in the nMOS two-stage circuit 506, the nMOS gate input line 515 becomes '0', and the nMOS on the hit line 149a side becomes non-conductive, so that the non-conductive state is established. Since the nMOS two-stage circuits 505 and 506 are turned off, the hit line 14 shown in FIG.
9a was kept at '1', indicating that the comparison was consistent.

(B) Case where comparison is invalidated (Fig. 6B) This case is the mask data MSK of the mask register 11A.
Is '110' and the memory protection level data MPL-
Occurs when 1 is '110' or '111'. That is, in this case, the signal line 112a for inputting the least significant bit of MSK is '0'
This occurs when the memory content signal line 511 indicating the least significant bit of the memory protection level becomes “0” or “1”. Regardless of whether the signal line 511 is “0” or “1”, the result of the comparison is considered to be consistent.

The case and the hit lines 149a in the same manner as in (a) pre-charged to the previous cycle T ₃ through T ₄ of the address translation is performed. Since the signal line 112a is '0', the word lines 145a, 146a
Are both '0'. Therefore, the nMOS two-stage circuits 505 and 506 in which the nMOS gate input lines 513 and 515 are both “0” are in the non-conductive surface state, and the charge of the hit line 149a is maintained. As a result, as shown in FIG. 6B, the hit line 149a is kept at “1”, and the result of the comparison is considered to be the same.

(C) Case where the comparison results in a mismatch (FIG. 6C) This case corresponds to the mask data M in the mask register 11A.
SK is '111' and memory protection level data in memory unit 812A
Occurs when MPL-1 is '110'. That is, the signal line 112a for inputting the least significant bit of the mask data MSK is “1”, and this occurs when the in-memory signal line 511 indicating the least significant bit of the memory protection level data MPL-1 is “0”. . Case (a) as shown in FIG. 6, the precharge is performed to the preceding cycle T ₃ through T ₄ address conversion similar to (b). Signal T ₁ through T ₂ address translation cycle ADE5
When 03 becomes "1", the outputs 145a and 146a of the AND circuits 501 and 502 become "1" and "0", respectively, as in the case of (a). Therefore, both nMOS gate input lines 513 and 514 become '1' and n
The MOS two-stage circuit 505 becomes conductive and the charge of the hit line 149a flows to the ground. As a result, as shown in FIG. 6C, the hit line 149a becomes “0”, indicating that the comparison result is inconsistent.

The operation of the memory cell described above is common to all bits in the memory unit 812A. The hit line 149a remains "1" when the comparison result of all the bits of a certain entry matches, and the hit line 149a becomes "0" if the comparison result does not match even with one bit. That is, whether a valid entry has been searched can be determined based on the value of the hit line of each entry.

If there is no hit entry, the output of gate 813, 818
Becomes '1', which is transmitted to the micro control unit 27 (FIG. 2) as a mishit signal.

Hereinafter, the microprocessor processing in this case will be described.

When receiving the mishit signal, the micro control unit 22 activates the inconsistency processing micro program stored in the micro ROM 21. The microprogram first determines whether the cause of the mismatch is LA1 mismatch or a memory access right check error, and performs each error processing. FIG. 7 shows a flowchart of the micro program of this determination processing.

First, the internal data bus 1
'000' is set to the MSK of the mask register 11A via 6 (step 71). That is, the comparison of the memory protection level data is invalidated. Next, the memory unit 812A
Is searched for an entry holding the upper bit part LA-u of the logical address (step 72). It is determined whether there is a hit entry as a result of the search (step 73). If there is a hit entry and the mishit signal 818 is not output,
Unmatched memory access right check error processing 74
And there is no hit entry and the mishit signal 818
Is output, it can be determined that there is no entry holding the logical address equal to the upper bit part LA-u of the logical address, and the processing at this time is performed (step 75). Step 7
The processing of 4,75 is the same as that of the prior art, and is omitted here.

In the above, the data shown in FIG. 3A is used as the memory protection level data and the memory access right data, but the present invention is not limited to this and includes various modifications within the scope of the claims. .

[Effects of the Invention] According to the present invention, address conversion and memory access right check, which are conventionally performed sequentially, can be performed simultaneously. For this reason, the time for checking the memory access right, which was required in addition to the address conversion time in the related art, is not required. A high-speed memory management unit having a built-in memory protection function can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an address translation device according to the present invention, FIG. 2 is a system configuration diagram of a microprocessor including the address translation device of FIG. 1, and FIG. 3A is a memory protection used in the device of FIG. FIG. 3B is a diagram showing level data and memory access right data, FIG. 3B is a diagram showing memory protection level data accessible by each memory access right level data using the device of FIG. 1, and FIG. 4 is a diagram of the device of FIG. 5 is a detailed circuit diagram of a partial decoder and a memory cell used in the device of FIG. 1, FIGS. 6A to 6C are operation timing charts of the device of FIG. 5, and FIG. Flow chart of mismatch processing in the apparatus shown in FIG.
FIG. 9 is a schematic block diagram of a conventional address translation device, FIG. 9 is a time chart of the operation of the device of FIG. 8, and FIG.
FIG. 3 is a diagram showing memory access right level data and memory protection level data used in the device shown in FIG.

Continuing from the front page (72) Inventor Shunpei Kawasaki 1450 Kamisumihonmachi, Kodaira-shi, Tokyo Inside Musashi Plant of Hitachi, Ltd. Within the Development Laboratory (72) Inventor Kimio Oe 1479, Kamizuhoncho, Kodaira-shi, Tokyo Within Hitachi Microcomputer Engineering Co., Ltd. (56) References JP-A-61-156347 (JP, A)

Claims (1)

(57) [Claims] 1. A logical address supplied from an arithmetic unit and 0 to n indicating a higher memory access right as the value is smaller.
An address translation device for outputting a physical address corresponding to mask data which is an integer value of (n is a natural number) or less, wherein a logical address and a memory protection level value of a physical address corresponding to the logical address are A memory unit for holding an entry consisting of a set of memory protection levels, which are n-bit data in which the first bit to the m-th bit are 1 and the remaining bits are 0 when m is an integer from 0 to n; A search for an entry in the memory unit that holds the logical address supplied from the arithmetic unit, and the n-bit data supplied from the arithmetic unit is represented as n-bit data in which the first to i bits are 1 and the rest are 0. Search for an entry having a memory protection level of at least 1 from the beginning to the i-th bit is 1 for the mask data set A RAM that holds a physical address corresponding to each entry of the memory unit, further comprising an associative memory having search means for extracting an entry corresponding to the logical address and the mask data supplied from the arithmetic unit; A means for outputting a physical address corresponding to the entry held in the RAM in response to the search means extracting the corresponding entry; and a mishit in response to the search means not being able to extract the entry. Means for outputting a signal.