JPH08111069A - Data identification device - Google Patents

Abstract

PURPOSE: To eliminate a RAM in which operation speed is lowered, and to make a data identification device suitable to be turned to a high speed IC by outputting the identified result of the data based on a present data decision signal, a present data identified result signal and an updating signal. CONSTITUTION: In a unit circuit (PATH) of a first stage, FIX(k-i)=0, DATA (k-i)=0 are assumed since on data from the prestage exists. Since the identified result is decided when the updating signal UPDATE from a comparison operation part (METRIC) is 0., a /UPDATE inverting the updating signal UPDATE is supplied to a FIX(k). An identification signal DEC is supplied to a DATA(k). By such a manner, the already decided identified result is succeeded to a next stage, and the identified result not decided is replaced by the DATA(k), and at this time, when the updating signal UPDATE=1, the DATA(k) is succeeded to the next stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data identification device suitable for use in a Viterbi decoder of a digital VTR, for example.

[0002]

2. Description of the Related Art Conventionally, in a VTR, recording signals have been coded, that is, channel coding has been performed. Channel coding refers to converting the code into a form suitable for the characteristics of the recording / reproducing system. Specifically, in order to record a digital code having a low frequency component in a magnetic recording / reproducing system that cannot reproduce a direct current or a low frequency component, the low frequency component of the digital code is suppressed.

A number of VTR channel coding methods have been proposed. Among them, the NRZI code and the interleaved NRZI code are particularly called partial response code. In recent years, it has been attempted to apply a partial response (PR) developed in the communication field, particularly a partial response class 4 (PR4).

The PR equalization method is PR (1, -1)
And PR (1,0, -1) are known. PR (1,
-1) corresponds to the NRZI code, and PR (1,0, -1)
Corresponds to the interleaved NRZI code. PR
Both (1, -1) and PR (1, 0, -1) have a ternary waveform at the detection point during reproduction. Here, the integers shown in parentheses represent the coefficients of the FIR filter as a digital filter that constitutes the PR equalizer.

When PR (1, -1), that is, the NRZI code is used as the equalization method, DC and low frequency components are small, and high-pass frequency characteristics are exhibited. PR (1,-
The frequency characteristic of 1) is (1-D) (where D represents a delay operator of the bit period T), and intersymbol interference having a value of -1 occurs after the isolated pulse.

On the other hand, as an equalization method, PR (1,0,-
1) That is, when the interleaved NRZI code is used, both the high frequency component and the low frequency component are small, and the band pass type frequency characteristic is exhibited. Frequency characteristic of PR (1, 0, -1) is, (1-D ²⁾ a and, intersymbol interference occurs with a value of -1 to 2 bits after the isolated pulse.

As described above, the application of the partial response is intended to shape the reproduction frequency at the detection point by positively utilizing the intersymbol interference. In particular, the interleaved NRZI code, that is, PR (1,0,
Since -1) is close to the magnetic recording characteristic, it has been attempted to be applied to the conventional digital VTR, and the video signal has been efficiently reproduced.

PR (1,0, -1) frequency characteristics (1-
D ² ) can be decomposed into (1-D) · (1 + D). (1-
The D) characteristic can be substituted by the differential characteristic during reproduction, and the (1 + D) characteristic can be realized by performing 1-bit analog delay and addition processing. If "1" and "-1" of the ternary waveform after (1 + D) conversion are identified as "1" and "0" as "0", the original code can be decoded. The timing signal can be extracted from the waveform including the high frequency signal after the (1-D) conversion.

A signal processing system to which a partial response code is applied generally has a pre-code for converting input data into an intermediate sequence, a magnetic recording system, and a multilevel discriminating circuit in order to avoid propagation of a code error at the time of decoding, The input data is multivalued and decoded. A specific example will be described below.

FIG. 7 is a block diagram of a conventional PR4 reproducing / decoding apparatus. A digital video signal processing device using this PR4 reproducing / decoding device has a recording system for recording data on a magnetic tape and a reproducing system for reproducing data recorded on the magnetic tape.

Since the recording system records the video signal on the magnetic tape, the A / D converter (not shown), the shuffle and band compression circuit and the parity addition circuit, and the 1 / (1-D ² ) pre-recorder as the PR4 pre-coder 100 are used. It has a code circuit and a recording head 101.

The reproducing system has a circuit configuration opposite to that of the recording system,
The video signal recorded on the magnetic tape 102 is reproduced.
Therefore, as the reproducing head 103 and the PR4 equalizer 104 (1
-D ²) Decoding circuit and Viterbi decoder 105
Error detection and correction circuit not shown, band expansion and deshuffling
And a D / A converter.

PR4 precoder 100 for recording system
As, with those having a 1 / (1-D ²⁾ characteristics, as a decoding circuit in the reproducing system, the use of those having a (1-D ²⁾ characteristics, the digital video signal processing apparatus, partial response class 4 (PR4) is applied to the digital video signal processing device.

The digital video signal processing device configured as described above operates as follows. In the recording system, an input video signal is quantized by an A / D converter (not shown) and converted into a digital video signal. This digital video signal is shuffled by subjecting it to discrete cosine transform or Huffman coding in predetermined block units in a shuffle and band compression circuit (not shown). Parity for error correction is added to the shuffled digital video signal in a parity addition circuit (not shown). The digital video signal to which the parity for error correction is added is supplied as a recording signal to the PR4 precoder 100, and the partial response class 4 (P
R4) precoded. The precoded digital video signal is passed through the recording head 101 to the magnetic tape 1.
02 is recorded.

In the reproducing system, the video signal recorded on the magnetic tape 102 is reproduced by the reproducing head 103, the reproduced high frequency signal is supplied to the PR4 equalizer 104, and the partial response class 4 (PR4) is equalized. Be converted. The equalized data is supplied to the Viterbi decoder 105 and is Viterbi decoded. Viterbi decoding is a decoding method for obtaining reproduction data by searching for a state transition pattern having the highest possibility from all state transition patterns for a reproduction signal. The Viterbi-decoded reproduction data is supplied to an error detection / correction circuit (not shown) for error detection and error correction. The error-detected and error-corrected data is supplied to band extension and deshuffle not shown,
Band extension and deshuffle are performed. The band-expanded and deshuffled data is supplied to a D / A converter (not shown) and converted into an output video signal.

In the magnetic recording / reproducing apparatus such as the digital VTR, the partial response class 4 is used.
Decoding of reproduction data equalized to (PR4) is performed by NRZI
It is becoming more common to connect two simplified Viterbi decoders for use in parallel. FIG. 8 shows the conventional N
It is a circuit diagram of a Viterbi decoder for RZI. FIG. 8 is the 83rd part of “Digital Video Recording Technology” published by Nikkan Kogyo Shimbun.
This is described on the page as an example of a Viterbi decoder for NRZI. FIG. 8 is a widely known Ferguson circuit.

The circuit diagram of the conventional NRZI Viterbi decoder shown in FIG. 8 is configured as follows. In FIG.
The reproduction signal input to the reproduction signal input terminal 110 is supplied to the addition input of the adder 112 and also to the sample hold circuit 111. Sample hold circuit 11
The reproduced signal sampled by 1 is supplied to the subtraction input of the adder 112. The output of the adder 112 is the comparator 1
Is supplied to the subtraction input of 13 and the other comparator 114
Is supplied to the summing input of. Depending on the selection of the switch 118, the addition input of the one comparator 113 is “+2” or “−”.
2 "is supplied. “0” is supplied to the subtraction input of the other comparator 114.

The output of one comparator 113 and the output of the other comparator 114 are one exclusive OR circuit 11.
5 to the exclusive OR circuit 115 on one side.
Update signal UPDAT indicating that the current value has been confirmed from
Output E. The output of the other comparator 114 is supplied to the β register 117. The selection of the switch 118 is made based on the output of the β register 117. The value of β is “+1”
Or "-1". The output of the other comparator 114 and β
The output of the register 117 is supplied to the other exclusive OR circuit 116, and the other exclusive OR circuit 116 outputs the discrimination result signal DEC of the Kth data. The update signal UPDATE is supplied to each clock input as a clock of the sample hold circuit 111 and the β register 117.

The update signal UPDATE is sent to the switch 119.
And the switch 119 is selected to supply the identification result signal DEC as the input D _I to the RAM 123 and to the switch 120.
Select Whether the output K of the address counter 121 is supplied to the switch 120 according to the selection of the switch 120,
Alternatively, the output P of the pointer register 122 is the switch 12
0 is supplied. A clock is supplied to the clock input of the address counter 121, and an update signal UPDATE is supplied to the clock input of the pointer register 122.
The update signal UPDATE and the identification result signal DEC are used to specify the address and pointer of the RAM 123 and output the reproduction data D _O to the reproduction data output terminal.

The conventional NRZI Viterbi decoder thus configured operates as follows. In FIG.
First, the past data YK of the K address of the RAM 123 is read. Next, one comparator 113 and the other comparator 1
14, the exclusive OR circuit 115 on one side and the exclusive OR circuit 116 on the other side allow YK-
Check whether YP is between "0" and "-2β" or otherwise.
If YK-YP is between “0” and “−2β”, the update signal UPD from one exclusive OR circuit 115.
The switch 119 is selected by the ATE, the switch 120 is selected by the update signal UPDATE, and "0" as the identification result signal DEC is set to the address counter 1
21 of the current address P is designated and P of the RAM 123 is designated.
Write in the address.

If Y _K -Y _P is not between "0" and "-2β", the switch 119 is selected by the update signal UPDATE from one exclusive OR circuit 115 and the other exclusive circuit is selected. [−β * sgn (Y _K − as the discrimination result signal DEC from the OR circuit 116.
Y _P )] is written in the P address of the RAM 123. here,
sgn (Y _K -Y _P) refers to the sign of (Y _K -Y _P).

Further, the sample hold circuit 111 is
Hold Y _P at Y _K based on the instruction update line by the update signal UPDATE. Y _P is data that was not previously determined. The output P of the pointer register 121 is set to K
Change to. The pointer register 121 indicates the pointer of the RAM 123 of the address of the unfixed data. Then, the count value of the address counter 121 is incremented from K to K + 1. The above operation is repeated.

That is, by writing the information as to whether or not it has been decided and the identified result in the RAM 123, the data decided at that time is written at the current address, and the data not decided is not decided before. However, after being confirmed, the now confirmed result will be written to the address that was not previously confirmed.

The actual circuit diagram of the conventional NRZI Viterbi decoder shown in FIG. 9 represents the actual circuit configuration of the configuration of the conventional NRZI Viterbi decoder of FIG. In FIG. 9, Y [0: 7] represents an 8-bit reproduction signal. AMP [0: 7] indicates an 8-bit set value. ZERO [0: 7] indicates an 8-bit “0” signal. The METRIC constitutes the comparison calculation unit 130. Y
[0: 7], AMP [0: 7] and ZERO [0:
7] are respectively supplied to the corresponding Y [0: 7] terminal, AMP [0: 7] terminal and ZERO [0: 7] terminal of the comparison operation unit 130 (METRIC). Comparison calculation unit 13
An update signal UPDATE is output from the UPDATE terminal of 0 (METRIC). Comparison operation unit 130 (MET
The identification result signal DEC is output from the DEC terminal of RIC).

The MEM constitutes the memory unit 131. The update signal UPDATE and the identification result signal DEC respectively correspond to the UPDATE corresponding to the memory unit 131 (MEM).
It is supplied to the terminal and the DEC IN terminal. The identification result signal DEC OUT is output from the DEC OUT terminal of the memory unit 131 (MEM). In addition, the memory unit 13
1 (MEM) clock terminal CLK has a clock signal C
LK is supplied.

Here, the settings are changed as follows. The place where β in FIG. 8 is “+1” or “−1” is set to “1” or “0” in FIG. 9. FIG.
The amplitude reference value “+2” or “−2” in FIG. 9 is “+ AMP” or “−AM” in FIG.
P ". The switch immediately before the RAM 123 in FIG. 8 is replaced with an AND circuit in FIG.

FIG. 10 is a diagram showing an actual circuit of a comparison operation unit (METRIC) of a conventional NRZI Viterbi decoder. In FIG. 10, AMP [0: 7] is the inverting circuit 1
It is supplied to the A [0: 7] input terminal of 40 and is supplied to one A [0: 7] input terminal of the 2-input selector 142. B from the B [0: 7] output terminals of the inverting circuit 140
The inverted output having the relationship of = -A is the 2-input selector 142.
Of the B [0: 7] input terminals.

Y _K of Y [0: 7] is supplied to the D [0: 7] input terminal of the 8-bit D latch 141 and also to one A [0: 7] input terminal of the subtractor 143. To be done. The latch output YP is output from the Q [0: 7] output terminal of the 8-bit D-latch 141 to the other B [0:
7] It is supplied to the input terminal.

OUT [0: 7] of the 2-input selector 142
The selector output is supplied from the output terminal to one A [0: 7] input terminal of one comparator 144, and C of the subtractor 143 is supplied.
[0: 7] The subtraction output from the output terminal is one of the comparators 144
Of the B [0: 7] input terminals.

The subtraction output is supplied from the C [0: 7] output terminal of the subtractor 143 to one A [0: 7] input terminal of the other comparator 145, and the ZERO [0: 7] is supplied to the other comparator. It is supplied to the other B [0: 7] input terminal of 145.

The comparison output of the one comparator 144 and the comparison output of the other comparator 145 are supplied to the one exclusive OR circuit 146, and the output of the one exclusive OR circuit 146 becomes the update signal UPDATE. . The other comparison output is supplied to the D input terminal of the 1-bit D latch 148, and the latch output β is output from the Q output terminal of the D latch 148.
Is supplied to the A / B selection terminal of the 2-input selector 142. The 2-input selector 142 switches between A input and B input depending on the value of β. The latch output β is the other comparator 14
It is supplied to the other exclusive OR circuit 147 together with the comparison output of No. 5. The value of β is “0” or “1”.

The output of one exclusive OR circuit 146 and the output of the other exclusive OR circuit 147 are supplied to the AND circuit 149, and the output of the AND circuit 149 becomes the discrimination result signal DEC. Further, the output of one exclusive OR circuit 146 is supplied as a clock to the clock input terminal CK of the 8-bit D latch 141.

FIG. 11 is a diagram showing an actual circuit of a memory unit (MEM) of a conventional Viterbi decoder for NRZI.
In FIG. 11, the clock signal CLK is supplied to the clock terminal CLK of the address counter 150. The address output K of the address counter 150 is the pointer register 1
51 and the one terminal of the switch 152. The pointer output P of the pointer register 151 is supplied to the other terminal of the switch 152. The update signal UPDATE is supplied to the clock terminal CLK of the pointer register 151 as a clock and also serves as a selection signal for the switch 152.

The identification result signal DEC IN is the input signal D _I
Is supplied to the RAM 153 as a result, and the output signal D _O is output as the result identification signal DEC O on the basis of the address output by switching the switch 152 or the address from the pointer output.
Output as UT.

The slave shown in FIG. 10 and FIG.
Comparison operation unit (METR I) of a conventional Viterbi decoder for NRZI
C) and the memory unit (MEM) operate as follows.
I do. First, read the data at address K in RAM 153
You. Then Y_K-Y_PIs "0" and "-AMP * (2β-
1) ”is checked. If within this range, R
Write “0” in the AM 153. If not within this range
For example, "-(2β-1) * sgn (Y_K-Y_P) ”RA
Write to address P of M153. Furthermore, Y_PTo Y _KIn
Shield. Contents of pointer register 151 from P to K
Change to. Then, the address counter 150 from K
Increment to K + 1. The above operation is repeated.
Thus, the conventional NRZI shown in FIG. 10 and FIG.
And operation unit (METRIC) of the Viterbi decoder for video and audio
The molly section (MEM) is for the conventional NRZI shown in FIG.
It operates exactly the same as the Viterbi decoder. Also, here
The force signal is treated as 8 bits, but especially the bit
The number is not limited.

[0036]

However, the conventional NRZ
In the Viterbi decoder for I, the RAM must perform two operations of reading the data at the K address and writing the data at the K address or the P address in one clock. There is an inconvenience that a high-speed RAM that operates twice as fast is required.

Further, when considering the IC of the peripheral circuit of the Viterbi decoder, it is difficult to incorporate a high-speed RAM, and the circuit scale is increased for this purpose.

Further, unless a recording modulation for guaranteeing that the identification result is confirmed within the range of the size of the RAM is performed, a meaningless value due to the output of unconfirmed data is set as the identification result. There was an inconvenience of outputting.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data identification device that can obtain a highly reliable identification result with a small circuit scale.

[0040]

As shown in FIGS. 1 to 6, a data discriminating apparatus according to the present invention has a transmission signal Y [0 precoded in a partial response showing a predetermined bandpass frequency characteristic due to intersymbol interference. : 7] is equalized into a partial response, and the present data finalization signal FIX indicating that the current data of the transmission signal Y [0: 7] is finalized
(K) and the transmission signal Y [0: 7] based on the current data identification result signal DEC indicating the identification result of the current data.
In the data identification device that decodes the transmission signal Y [0:
7] of the past data finalization signal storage latch 10 for storing the finalization signal FIX (ki) of data at least at a predetermined time before the present time, and at least the data before the present time of the transmission signal Y [0: 7]. Identification result signal DATA (k-i)
11 for storing past data identification result signal
A selector 13 for selecting either the present data identification result signal DEC or the past data identification result signal DATA (k-i) output from the past data identification result signal storage latch 11, and the present data confirmation signal FIX (k ) And the past data confirmation signal FIX (k-i) output from the past data confirmation signal storage latch 10 confirms that the present data of the transmission signal Y [0: 7] or at least the data before the present is confirmed. Update signal FIX (k-
i-1) or the OR circuit 12 for detecting the unit circuit 2, 3, 4, and 5 are connected in series in at least a plurality of stages, and the current data determination signal FIX (k), the current data identification result signal DEC, and the update Signal UPDATE and present data identification result signal DEC or past data identification result signal DATA
Based on (k-i), the data identification result DATA (k-i-1) of the transmission signal at a predetermined time is output.

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the equalizer 104 for equalizing the partial response, the unit circuits 2 having a plurality of stages,
3, 4, and 5 are integrated into an integrated circuit.

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the threshold value detector 20 for detecting the transmission signal Y [0: 7] based on the predetermined threshold value, and the threshold value detection result TH of the threshold value detector 20.
The latch 30 for storing D (k) and the unit circuits 2 of a plurality of stages
Data identification result DATA (k−) of the transmission signals Y [0: 7] output from 1, 22, and 23 at a predetermined time.
i) and the threshold detection result TH output from the latch 30
And a selector 13 for selecting any one of D (k-1), and the identification result DATA of the data at a predetermined time of the transmission signal Y [0: 7] by the outputs from the unit circuits 21, 22, 23 of a plurality of stages. When (ki) is not determined, the threshold detection result THD (k-1) output from the latch 30.
Is the identification result of the data of the transmission signal Y [0: 7] at a predetermined time.

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the threshold detector 2
0 is the transmission signal Y [0: 7] and a predetermined set value + AMP /
The first comparator 43 for comparing the transmission signal Y and the transmission signal Y [0:
7] and an inversion signal −AMP / 2 having a predetermined set value, the second comparator 42, and the outputs of the first comparator 43 and the second comparator 42 output a threshold detection result. An OR circuit 44 for controlling the transmission signal Y [0: 7], a predetermined set value + AMP / 2, and an inverted signal −AMP of the predetermined set value.
/ 2 respectively, when the data of the transmission signal Y [0: 7] is larger than the predetermined set value + AMP / 2, and when the data of the transmission signal Y [0: 7] is the predetermined set value + AMP /.
2 and the inversion signal of a predetermined set value-AMP / 2, and the three-value discrimination when the data of the transmission signal Y [0: 7] is smaller than the inversion signal of the predetermined set value-AMP / 2. Is to do.

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the unit circuits 21, 2
2, 23 are connected in series in eight stages, and the transmission signal Y [0: 7] is input to the eight-stage unit circuits 21, 22, 23 and output from the final stage of the eight-stage unit circuits 21, 22, 23. Input transmission signal Y [0: 7] to the threshold detector 20, and the transmission signal Y [0: 7 at the time corresponding to the threshold detection result THD (k−1) of the threshold detector 20. ] 8 unit circuit 2
It is extracted from any one of 1, 22, and 23, and the equalization coefficient of the equalizer 104 for equalizing into a partial response is adjusted based on the time transmission signal Y [0: 7]. .

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the equalizer 104 for equalizing the partial response and the unit circuits 2 having a plurality of stages are provided.
1, 22, 23, threshold detector 20, and latch 30
And the selector 13 are integrated into an integrated circuit.

The data identification device of the present invention is shown in FIG.
As shown in FIG. 6, in the above description, the transmission signal is precoded to the partial response class 4 and then recorded on the magnetic recording medium 102 by the recording means 101, reproduced by the reproducing means 103, and the like in the partial response class 4. It was designed to be transformed.

[0047]

According to the present invention, the finalization signal FI of the data of the transmission signal Y [0: 7] at a predetermined time before at least the present time.
X (k-i) is stored, and the identification result signal DATA (k- of at least the data before the present of the transmission signal Y [0: 7] is stored.
i) is stored, either the present data identification result signal DEC or the past data identification result signal DATA (k-i) is selected, and the transmission signal Y [0: 7 is selected by the past data confirmation signal FIX (k-i). ] The update signal FI indicating that the current data or at least the data before the current is determined.
The unit circuits 2, 3, 4, 5 for detecting X (k-i-1) are connected in series in at least a plurality of stages, and the current data confirmation signal F
Based on IX (k), the current data identification result signal DEC, the update signal UPDATE, and the current data identification result signal DEC or the past data identification result signal DATA (k-i), the predetermined value of the transmission signal Y [0: 7] is determined. Since the data identification result DATA (k-i-1) is output at the time, by connecting the small-scale unit circuits in multiple stages, the RAM whose operation speed is reduced can be omitted, and it is suitable for high-speed IC implementation. Can be

Further, according to the present invention, in the above,
Since the equalizer 104 for equalizing the partial response and the unit circuits 2, 3, 4, 5 of a plurality of stages are integrated into an integrated circuit, the integrated circuit having a specific function can be miniaturized and standardized. .

Further, according to the present invention, in the above,
When the data identification result DATA (k-i) of the transmission signal Y [0: 7] at a predetermined time is not determined by the outputs from the unit circuits 21, 22, 23 of the plurality of stages, the latch 30
Since the threshold detection result THD (k-1) output from is used as the data identification result of the transmission signal Y [0: 7] at a predetermined time, the unit circuit 2 having a finite number of stages is used.
When the identification result is not determined in 1, 22, or 23, or when the reliability of the identification result deteriorates, the identification result at the corresponding time can be output.

Further, according to the present invention, in the above,
The transmission signal Y [0: 7] is compared with the predetermined set value + AMP / 2 and the inverted signal −AMP / 2 of the predetermined set value, respectively, and the data of the transmission signal Y [0: 7] is set to the predetermined set value. When it is larger than + AMP / 2, the transmission signal Y [0: 7]
When the data is in the middle of a predetermined set value + AMP / 2 and an inversion signal of the predetermined set value −AMP / 2, and when the transmission signal Y
The data of [0: 7] is an inverted signal of a predetermined set value-AMP
Since the three-value discrimination is performed when the value is smaller than / 2, it is possible to obtain a highly reliable discrimination result with a small circuit scale.

Further, according to the present invention, in the above,
The transmission signal Y [0: 7] at the time corresponding to the threshold detection result of the threshold detector 20 is transferred to the unit circuits 21, 22 of eight stages,
The transmission signal Y of the time taken from any one of
Since the equalization coefficient of the equalizer 104 for equalizing the partial response is adjusted based on [0: 7],
The equalization coefficient of the equalizer 104 can be adjusted based on the identification result THD (k-1) at any time.

Further, according to the present invention, in the above,
Equalizer 104 for equalizing partial response, unit circuits 21, 22, 23 of a plurality of stages, and threshold detector 20
Since the latch 30 and the selector 13 are integrated into an integrated circuit, the integrated circuit having a specific function can be miniaturized and standardized.

Further, according to the present invention, in the above,
Since the transmission signal Y [0: 7] is precoded to the partial response class 4, it is recorded on the magnetic recording medium 102 by the recording unit 101, reproduced by the reproducing unit 103, and equalized to the partial response class 4.
The reproduced signal equalized to the partial response class 4 can be effectively Viterbi-decoded.

[0054]

1 is a block diagram showing the overall configuration of a Viterbi decoder of an embodiment of a data identification device according to the present invention. The data identification device of the present invention, in this example,
In particular, the Viterbi decoder is characterized in that a plurality of unit circuits are provided in place of the RAM to achieve high speed and small size. The data identification device of this example is used in the conventional PR4 reproducing / decoding device shown in FIG. 7 of the prior art. The configuration of the PR4 reproducing / decoding apparatus shown in FIG. 7 is the same as the conventional one, and therefore its explanation is omitted.

As shown in FIG. 1, the Viterbi decoder of one embodiment of the data identification device according to the present invention is configured as follows. In FIG. 1, a comparison calculation unit (METRIC)
Is the same circuit as the actual circuit of the comparison operation unit (METRIC) of the conventional NRZI Viterbi decoder shown in FIG. 10, and its detailed description is omitted.

In FIG. 1, Y [0: 7], AMP
[0: 7] and ZERO [0: 7] are the corresponding Y [0: 7] terminals of the comparison operation unit (METRIC), A
It is supplied to the MP [0: 7] terminal and the ZERO [0: 7] terminal. UPDATE of comparison operation unit (METRIC)
The update signal UPDATE is output from the terminal. From the DEC terminal of the comparison operation unit (METRIC), the confirmation signal DE
C is output.

The update signal UPDATE is supplied to the FIX (k) terminal of the first-stage unit circuit (PATH) 2 via the inverter 1. The update signal UPDATE is directly transmitted to the second
Unit circuit from the last stage to the last stage and the last stage (PAT
H) 4 and 5 FIX (k) terminals, respectively.
FIX (k) indicates update information of the current kth data.

The confirmation signal DEC is directly supplied to the unit circuits (PATH) of the first stage, the second stage to the last stage and the last stage.
It is supplied to the DEC terminals of 2, 3, 4, and 5. FIX (ki) terminal and D of the unit circuit (PATH) 2 of the first stage
A value of "1" or "0" is supplied to the ATA (k-i) terminal. FIX (k-i) indicates update information of the k-th i data before the present. DATA (k-i) indicates the k-i-th data before the present.

FIX of the unit circuit (PATH) 2 of the first stage
From the (k-i-1) terminal, the second stage unit circuit (PAT
H) 3 FIX (k-i) terminal is supplied with the (k-1) -th update information. First stage unit circuit (PATH) 2
From the DATA (k-i-1) terminal of the second unit circuit (PATH) 3 to the DATA (k-i) terminal of the second stage unit circuit (PATH) 3,
The first data is supplied.

In this way, the unit circuits (PAT
The previous update information and data are supplied over the number n of connection stages of H), and the unit circuit (PA) immediately before the last stage is supplied.
From the FIX (k-i-1) terminal of the TH) 4 to the FIX (k-i) terminal of the unit circuit (PATH) 5 at the final stage, k-
The i- (n-1) th update information is supplied. DATA (k-i-) of the unit circuit (PATH) 4 before the final stage
1) From the terminal to the DA of the unit circuit (PATH) 5 at the final stage
The k-i- (n-1) th data is supplied to the TA (k-i) terminal.

Then, the final stage unit circuit (PATH) 5
From the DATA (k-i-1) terminal of the above, the k-i-n-th data is supplied as DEC OUT. Further, the clock signal CLK is supplied to the clock input terminals CLK of the unit circuits (PATH) 2, 3, 4, 5 of the first stage, the second stage to the last stage and the last stage, respectively.

FIG. 2 is a circuit diagram of a unit circuit (PATH) in place of the RAM of the Viterbi decoder of the embodiment of the data identification device according to the present invention. In FIG. 2, FIX
(Ki) is supplied to the D input terminal of one D latch 10 and output from the Q output terminal. The Q output of one D latch 10 and FIX (k) are supplied to the OR circuit 12,
The output of the OR circuit 12 is FIX (k-i-1).

DATA (k-i) is the other D latch 11
Is supplied to the D input terminal and is output from the Q output terminal.
The Q output of the other D latch 11 is supplied to the other input terminal B of the 2-input selector 13. DEC is supplied to one input terminal A of the 2-input selector 13. The Q output of one D-latch 11 is supplied to the output selection terminal of the 2-input selector 13, and one of the two inputs is output from the OUT terminal to become DATA (k-i-1).

The unit circuit (PATH), which is configured as described above and serves as a substitute for the RAM of the Viterbi decoder of the embodiment of the data identification apparatus according to the present invention, operates as follows. First, in FIG. 2, if FIX (k−i) = 1, DATA (k−i) indicates the confirmed identification result at time k−i, so DATA (k−i) is set to DATA.
Output as (k-i-1). Otherwise, DE
Since C is a candidate for the identification result at time k-i, the identification signal DEC is output as DATA (k-i-1).

Further, in FIG. 2, FIX (k-i) =
If it is 1, FIX (k-i-1) = 1 is output. Otherwise, the update signal UPDATE is set to FIX (k-i
-1) is output.

The Viterbi decoder of one embodiment of the data discriminating apparatus according to the present invention shown in FIG. 1, in which such unit circuits (PATH) are connected in n stages, operates as follows. In FIG. 1, in the unit circuit (PATH) 2 of the first stage, since there is no data from the previous stage, FIX (k−i) = 0, D
ATA (k−i) = 0.

When the update signal UPDATE = 0 from the comparison operation unit (METRIC), the identification result is determined, and therefore FIX (k) is supplied with / UPDATE which is the inverted version of the update signal UPDATE. An identification signal DEC is supplied to DATA (k).

In the second and subsequent stages, F from the previous stage
IX (k-i) and DATA (k-i) are supplied, and FI
X (k) and DATA (k) have a comparison operation unit (METR).
The update signal UPDATE from the IC) and the identification signal DEC are supplied.

By doing this, the already determined identification result is succeeded to the next stage, and the identification result which has not been confirmed is replaced with DATA (k). At this time, if the update signal UPDATE = 1 , This will be inherited to the next stage.

FIG. 3 is a time chart of the Viterbi decoder of one embodiment of the data identification device according to the present invention. In this example, the unit circuits (PATH) are connected in four stages. In this example, a case is shown in which all the identification results are determined by the unit circuits (PATH) of up to 4 stages. In FIG. 3, TIME indicates the number of clocks. TI
When ME = 0, the update signal UPDATE = 0, the current k-th data confirmation signal FIX (k) = 1, and the current data DATA (k) = 0 are displayed in the order of clocks 1, 2, 3, and 4. , FIX (k-1) and DATA (k-1), FIX
(K-2) and DATA (k-2), FIX (k-3) and DATA (k-3), FIX (k-4) and DATA (k
-4) is successively inherited.

When TIME = 2, the update signal UPDAT
When E = 1 and the identification signal DEC = 0, the current k-th data is not fixed, and the k−1-th fixed signal FIX (k−
1) = 1 and data DATA (k−1) = 0 are set to FIX (k−2) and DATA in the order of clocks 2, 3, 4, and 5.
(K-2), FIX (k-3) and DATA (k-3),
It is successively inherited by FIX (k-4) and DATA (k-4).

When TIME = 3, the update signal UPDAT
With E = 1 and the identification signal DEC = 1, the current k-th data is not fixed, and the k−1-th fixed signal FIX (k−
1) = 1 and data DATA (k−1) = 1, FIX (k−2) and DATA in the order of clocks 3, 4, 5, and 6.
(K-2), FIX (k-3) and DATA (k-3),
It is successively inherited by FIX (k-4) and DATA (k-4).

Similarly, TIME = 4, 5, 6, 8, 1
When 1, 12, 13, 17, and 19, update signal UPDA
When TE = 0, the current k-th data confirmation signal FIX (k) =
1 and the current data DATA (k) = 0 are FIX (k−1), DATA (k−1), and FI in the order of clocks.
X (k-2) and DATA (k-2), FIX (k-3)
And DATA (k-3), FIX (k-4) and DATA
(K-4) are successively inherited.

When TIME = 7 and 14, update signal UP
With DATE = 1 and the identification signal DEC = 1, 0, the current kth to k-3th data is not determined, and the k-4th determination signal FIX (k-4) = 1 and the data DATA (k
-4) = 1,0 is FIX (k-4) and DATA (k-
4) inherited.

When TIME = 9, 18, and 20, the update signal UPDATE = 1 and the identification signal DEC = 1 are currently k.
The (k-1) th to (k-1) th data is not determined, and the (k-2) th confirmation signal FIX (k-2) = 1 and the data DATA
(K-2) = 1 is FIX (k-3) in the order of clocks.
And DATA (k-3), FIX (k-4) and DATA
(K-4) are successively inherited.

When TIME = 10, 15, 16, the update signal UPDATE = 1 and the identification signal DEC = 0, 1
At present, the k-th data is not confirmed, and the k-1th confirmation signal FIX (k-1) = 1 and the data DATA (k-
1) = 0, 1 are FIX (k-2) and DATA (k-2), FIX (k-3) and DATA (k
-3), FIX (k-4) and DATA (k-4) are successively inherited.

As described above, the Viterbi decoder of one embodiment of the data identification apparatus according to the present invention shown in FIGS.
In comparison with the conventional example, the RAM, which is an obstacle in terms of operation speed and circuit scale when integrated into an IC, is omitted. Further, in the conventional example, when the RAM was used, it was necessary to read and write during one clock, but according to the circuit of FIG. 3, it is only necessary to perform the latch operation within one clock. Therefore, it can be easily configured.

By doing so, the RAM which becomes an obstacle in terms of speeding up and circuit scale when considering IC implementation
Can be omitted. Further, since the entire circuit can be configured using only the circuit that operates at the clock rate speed, it is easy to increase the speed.

According to the above example, the confirmation signal FI of the data of the transmission signal Y [0: 7] at least at the predetermined time before the present time.
X (k-i) is stored, and the identification result signal DATA (k- of at least the data before the present of the transmission signal Y [0: 7] is stored.
i) is stored, either the present data identification result signal DEC or the past data identification result signal DATA (k-i) is selected, and the transmission signal Y [0: 7 is selected by the past data confirmation signal FIX (k-i). ] The update signal FI indicating that the current data or at least the data before the current is determined.
The unit circuits 2, 3, 4, 5 for detecting X (k-i-1) are connected in series in at least a plurality of stages, and the current data confirmation signal F
Based on IX (k), the current data identification result signal DEC, the update signal UPDATE, and the current data identification result signal DEC or the past data identification result signal DATA (k-i), the predetermined value of the transmission signal Y [0: 7] is determined. Since the data identification result DATA (k-i-1) at the time is output, by connecting the small-scale unit circuits 2, 3, 4, and 5 in multiple stages, the RAM whose operation speed decreases can be omitted. ,
It can be made suitable for high-speed IC.

Further, according to the above example, since the PR4 equalizer 104 for equalizing the partial response and the unit circuits 2, 3, 4, 5 of a plurality of stages are formed as an integrated circuit in the above description, The integrated circuit having the function can be miniaturized and standardized.

However, even with the Viterbi decoder of one embodiment of the data identifying apparatus according to the present invention shown in FIGS. 1 to 3, the identification result may not be fixed within a finite number of clocks. . The identification result output at this time is
It is "1" or "0", but it is a completely meaningless value.
In order to avoid this, for example, there is a method of devising the recording modulation code by, for example, 8-9 conversion or adding additional bits so that the identification result is definitely determined within 8 clocks or within 16 clocks. . However, this method increases the data rate because it requires additional bits. Therefore, a Viterbi decoder that can solve this problem will be described below.

FIG. 4 is an overall block diagram of a Viterbi decoder of another embodiment of the data identification device according to the present invention.
In this example, for the block diagram shown in FIG.
An example in which a threshold detection circuit (THD) 20, an AND circuit 25, and a 2-input selector 24 are added is shown. The unit circuits (PATH) 21, 22, 23 are provided with one D-latch 30 for latching the output of the threshold detection circuit (THD) 20 in addition to that shown in FIG. The comparison operation unit (METRIC) is the same as that shown in FIG. 1 or the related art.

In FIG. 4, Y [0: 7], AMP
[0: 7] and ZERO [0: 7] are the corresponding Y [0: 7] terminals of the comparison operation unit (METRIC), A
It is supplied to the MP [0: 7] terminal and the ZERO [0: 7] terminal. UPDATE of comparison operation unit (METRIC)
The update signal UPDATE is output from the terminal. From the DEC terminal of the comparison operation unit (METRIC), the confirmation signal DE
C is output.

The update signal UPDATE is sent to the FIX (k) of the unit circuit (PATH) 21 of the first stage via the inverter 1.
Supplied to the terminal. The update signal UPDATE is directly sent from the second stage to the last stage unit circuit and the last stage unit circuit (PAT).
H) 22 and 23 are supplied to the FIX (k) terminals, respectively. FIX (k) indicates update information of the current kth data.

The confirmation signal DEC is directly supplied to the unit circuits (PATH) of the first stage, the second stage to the last stage and the last stage.
It is supplied to the 22 and 23 DEC terminals. FIX (ki) terminal and DA of the unit circuit (PATH) 21 of the first stage
A value of "1" or "0" is supplied to the TA (k-i) terminal. FIX (k-i) indicates update information of the k-th i data before the present. DATA (k-i) indicates the k-i-th data before the present.

Here, Y [0: 7] and AMP [0:
7] is supplied to the corresponding Y [0: 7] terminal and AMP [0: 7] terminal of the threshold detection circuit (THD) 20, respectively. From the output terminal OUT of the threshold detection circuit (THD) 20 to the T of the unit circuit (PATH) 21 of the first stage
The threshold detection signal DET is supplied to the HD (k) terminal.

FI of the unit circuit (PATH) 21 of the first stage
From the X (ki-1) terminal, the second stage unit circuit (PAT
H) 22 FIX (k-i) terminal is supplied with the (k-1) -th update information. First-stage unit circuit (PATH)
21 from the DATA (k-i-1) terminal to the DATA (k-i) terminal of the second-stage unit circuit (PATH) 22.
-I-1th data is supplied. From the THD (k-1) terminal of the unit circuit (PATH) 21 of the first stage to the THD (k) terminal of the unit circuit (PATH) 22 of the second stage, k-
The first threshold detection signal is supplied.

In this way, the unit circuits (PAT
H) is supplied with the previous update information and data over the number n of connection stages, and the unit circuit (PAT) before the last stage is connected.
H) 22 FIX (k-i-1) terminal to the final stage unit circuit (PATH) 23 FIX (k-i) terminal, k
-(N-1) th update information is supplied. DATA (k-i-) of the unit circuit (PATH) 22 before the final stage
1) From the terminal to D of the unit circuit (PATH) 23 at the final stage
The k- (n-1) th data is supplied to the ATA (ki) terminal.

Then, the final stage unit circuit (PATH) 2
The FIX (k-i-1) terminal of No. 3 supplies the k- (n-1) th update information to one input terminal of the AND circuit 25, and the other input terminal of the AND circuit 25 receives the switching signal VDEN. Is supplied. The output of the AND circuit 25 is supplied to the select terminal of the 2-input selector 24. From the DATA (k-i-1) terminal of the unit circuit (PATH) 23 at the final stage, the kn-th data is supplied to one data input terminal of the 2-input selector 24. From the THD (k-1) terminal of the unit circuit (PATH) 23 at the final stage, the knth threshold value detection signal is supplied to the other data input terminal of the 2-input selector 24. One data of two inputs from the output terminal OUT of the two-input selector 24 is DECO
It is output as UT. Further, the clock signal CLK is
Clock input terminals C of the unit circuits (PATH) 21, 22, 23 of the first stage, the second stage to the last stage and the last stage
It is supplied to each LK.

FIG. 5 is a circuit diagram of a unit circuit (PATH) which is a substitute for the RAM of the Viterbi decoder of another embodiment of the data identification device according to the present invention. In FIG. 5, FI
X (ki) is supplied to the D input terminal of the first D latch 10 and output from the Q output terminal. First D latch 10
Q output and FIX (k) are supplied to the OR circuit 12, and the output of the OR circuit 12 becomes FIX (k-i-1).

DATA (k-i) is the second D latch 11
Is supplied to the D input terminal and is output from the Q output terminal.
The Q output of the second D latch 11 is supplied to the other input terminal B of the 2-input selector 13. DEC is supplied to one input terminal A of the 2-input selector 13. The Q output of the first D-latch 11 is supplied to the output selection terminal of the 2-input selector 13, and one of the two inputs is output from the OUT terminal to become DATA (k-i-1).

THD (k) is the D of the third D latch 30.
It is supplied to the input terminal and THD (k-1) from the Q output terminal.
Is output as First, second and third D-latch 1
A clock signal C is applied to the clock terminals CK of 1, 12, and 13.
LK is supplied respectively.

FIG. 6 is a threshold value detecting circuit (TH) of a Viterbi decoder of another embodiment of the data discriminating apparatus according to the present invention.
It is a circuit diagram of D). In FIG. 6, AMP [0: 7]
Is supplied to the A [0: 7] terminals of the arithmetic unit 40, and B = A
After the calculation of / 2, it is output from the B [0: 7] terminals. The output from the B [0: 7] terminal of the arithmetic unit 40 is supplied to the A [0: 7] terminal of the inverter 41, and is output from the B [0: 7] terminal after the calculation of B = -A. It

Output from the B [0: 7] terminal of the inverter 41
Is TH One comparator 42 as LOW [0: 7]
Of the A [0: 7] terminal. Y [0: 7] is other
When it is supplied to the A [0: 7] terminals of the other comparator 43,
Is supplied to the B [0: 7] terminals of one comparator 42.
You. The output from the B [0: 7] terminals of the arithmetic unit 40 is TH
As HIGH [0: 7], B of the other comparator 43
It is supplied to the [0: 7] terminal.

The comparison output of one comparator 42 when A> B and the comparison output of the other comparator 43 when A> B are supplied to the OR circuit 44, and the output of the OR circuit 44 becomes the threshold value. It is output as the detection signal DET.

The unit circuit (PATH), which is configured as shown in FIG. 5 and which replaces the RAM of the Viterbi decoder of the embodiment of the data identification apparatus according to the present invention, operates as follows. First, in FIG. 5, if FIX (k-i) = 1, DATA (k-i) indicates the confirmed identification result at time k-i, so DATA (k-i) is DAT.
Output as A (k-i-1). Otherwise D
Since EC is a candidate for the identification result at time k-i, the identification signal DEC is output as DATA (k-i-1).
At this time, the threshold detection signal DET is set to THD (k-1)
Output as

Further, in FIG. 5, FIX (k-i) =
If it is 1, FIX (k-i-1) = 1 is output. Otherwise, the update signal UPDATE is set to FIX (k-i
-1) is output.

Further, the threshold detection circuit (THD) of the Viterbi decoder of the embodiment of the data discriminating apparatus according to the present invention configured as shown in FIG. 6 operates as follows.
In FIG. 6, two comparators 42 and 43 and an OR circuit 44 perform ternary discrimination. That is, Y> TH HI
When GH, DET = 1 and TH LOW <Y <
TH HIGH or Y = TH D when HIGH
ET = 0 and Y <TH When LOW, DET =
The identification result of 1 is output. Here, from the relationship between the amplitude reference value in the Viterbi decoder and the threshold value of the threshold detection circuit, TH HIGH = + AMP / 2, TH LOW =
-It becomes AMP / 2.

A Viterbi decoder of one embodiment of the data identification device according to the present invention shown in FIG. 4, in which such threshold detection circuit (THD) and unit circuit (PATH) are connected in n stages, is as follows. Operate. In the unit circuit (PATH) 21 of the first stage in FIG. 4, since there is no data from the previous stage, FIX (k-i) = 0, DATA (k-i).
= 0.

When the update signal UPDATE = 0 from the comparison operation unit (METRIC), the identification result is confirmed, and therefore FIX (k) is supplied with / UPDATE which is the inverted update signal UPDATE. An identification signal DEC is supplied to DATA (k).

In the second and subsequent stages, F from the previous stage
IX (k-i) and DATA (k-i) are supplied, and FI
X (k) and DATA (k) have a comparison operation unit (METR).
The update signal UPDATE from the IC) and the identification signal DEC are supplied.

By doing so, the already determined identification result is succeeded to the next stage, and the identification result which has not been confirmed is replaced by DATA (k). At this time, if the update signal UPDATE = 1 , This will be inherited to the next stage.

Here, the threshold detection circuit (THD) 20
From the threshold detection signal DET to the unit circuit (PATH)
21 and is delayed by the same number of clocks as the identification signal DEC. Normally, VDEN = 1 and FIX (k- which is the output of the unit circuit (PATH) 23 at the final stage.
If (n) = 1, DATA (k−n) is the confirmed identification result, and is output as DEC OUT.

If FIX (k−n) = 0, then DATA
Since (k−n) is a meaningless value, the unit circuit (PATH) 2 at the final stage is changed from the threshold detection circuit (THD) 20.
Threshold detection signal THD (k-n) output via
Is output. Further, as an additional function, in a situation where the reliability of the identification result of the Viterbi decoder is deteriorated as compared with the threshold detection circuit (THD) 20, such as dropout and vibration fluctuation, VDEN = 0 is set, The threshold detection signal THD (k-n) is forcibly output.

Further, as a modification of the Viterbi decoder of the embodiment of the data identification apparatus according to the present invention shown in FIG. 4, Y [0: 7] before identification is converted into unit circuits (PATH) 21 and 2.
It is also possible to input it to 2, 23, delay this clock by one clock, and finally detect the threshold value. According to this method, the 8-bit D latch 30 is connected to the unit circuit (P
ATH) 21, 22, 23, but when adjusting the equalizer 104 such as changing the equalization coefficient of the equalizer 104, use the input signal at the time corresponding to the identification result. You can

By doing so, there is no possibility of outputting an identification result that has not been determined by the Viterbi decoder, so the reliability of the identification result is increased. Further, the number of stages for storing the identification result can be reduced, and the circuit scale can be reduced. In addition, it is not necessary to use a modulation method in which the identification result is fixed within a certain time.

According to the above example, in the above description, the transmission signals Y [0:
7] Data identification result DATA at a predetermined time
When (ki) is not determined, the threshold detection result THD (k-1) output from the latch 30 is transmitted to the transmission signal Y.
Since the data identification result is obtained at a predetermined time of [0: 7], the unit circuits 21 and 22 having a finite number of stages,
When the identification result is not confirmed in 23, or when the reliability of the identification result deteriorates, the identification result at the corresponding time can be output.

Further, according to the above example, in the above description, the transmission signal Y [0: 7] is compared with the predetermined set value + AMP / 2 and the inverted signal −AMP / 2 of the predetermined set value, and the transmission is performed. Data of signal Y [0: 7] is a predetermined set value + A
When it is greater than MP / 2, when the data of the transmission signal Y [0: 7] is between the predetermined set value + AMP / 2 and the inverted signal −AMP / 2 of the predetermined set value, and when the transmission signal Y [0 :
[7] is used to perform the three-valued discrimination when the data is smaller than the inversion signal −AMP / 2 having the predetermined set value, so that a more reliable discrimination result can be obtained with a small circuit scale.

Further, according to the above example, in the above description, the transmission signal Y [0: 7] at the time corresponding to the threshold detection result THD (k−1) of the threshold detector 20 is divided into eight stages. Since it is taken out from any one of the circuits 21, 22, and 23 and the equalization coefficient of the equalizer 104 for equalizing the partial response is adjusted based on the time transmission signal Y [0: 7], Equalizer 1 based on the identification result at any time
The equalization factor of 04 can be adjusted.

Further, according to the above example, in the above, the equalizer 104 for equalizing the partial response, the unit circuits 21, 22, 23 of a plurality of stages, the threshold detector 20,
Since the latch 30 and the selector 13 are integrated into an integrated circuit, the integrated circuit having a specific function can be miniaturized and standardized.

Further, according to the above example, in the above description, the transmission signal Y [0: 7] is precoded to the partial response class 4 and then recorded on the magnetic recording medium 102 by the recording means 101, and the reproducing means 103. Is reproduced and equalized to the partial response class 4, the reproduced signal equalized to the partial response class 4 can be effectively Viterbi-decoded.

[0112]

According to the present invention, at least a fixed signal of data at a predetermined time before the present of the transmission signal is stored,
The identification result signal of at least data before the present of the transmission signal is stored, and either the present data identification result signal or the past data identification result signal is selected, and the past data confirmation signal and the present data of the transmission signal or at least the present At least a plurality of unit circuits that detect an update signal indicating that the previous data has been confirmed are connected in series, and the current data confirmation signal, the current data identification result signal, the update signal and the current data identification result signal or the past data identification result Since the identification result of the data at the predetermined time of the transmission signal is output based on the signal, the RAM in which the operation speed is reduced by connecting the small-scale unit circuits in multiple stages
Can be omitted to make it suitable for high-speed IC.

Further, according to the present invention, in the above,
Since the equalizer for equalizing the partial response and the unit circuits of a plurality of stages are integrated into an integrated circuit, the integrated circuit having a specific function can be downsized and standardized.

Further, according to the present invention, in the above,
When the data identification result at the predetermined time of the transmission signal is not determined by the output from the unit circuits of multiple stages, the threshold detection result output from the latch is regarded as the data identification result at the predetermined time of the transmission signal. Therefore, when the identification result is not confirmed in the unit circuit with a finite number of stages,
Alternatively, when the reliability of the identification result deteriorates, the identification result at the corresponding time can be output.

Further, according to the present invention, in the above,
The transmission signal is compared with a predetermined set value and an inverted signal of the predetermined set value, respectively, and when the data of the transmission signal is larger than the predetermined set value, and when the data of the transmission signal is the predetermined set value and the predetermined set value. Since the three-value discrimination is performed when the data is in the middle of the inversion signal and when the data of the transmission signal is smaller than the inversion signal of the predetermined setting value, a more reliable discrimination result can be obtained with a small circuit scale. Obtainable.

Further, according to the present invention, in the above,
An equalizer that takes out the reproduction signal at the time corresponding to the threshold detection result of the threshold detector from any of the eight-stage unit circuits and equalizes the partial response based on the reproduction signal at the time. Since the equalization coefficient is adjusted, the equalization coefficient of the equalizer can be adjusted based on the identification result at any time.

Further, according to the present invention, in the above,
An equalizer for equalizing partial response, unit circuits of multiple stages, threshold detector, latch, and selector are integrated into an integrated circuit, so it is miniaturized and standardized as an integrated circuit having a specific function. Can be achieved.

Further, according to the present invention, in the above,
Since the transmission signal is precoded to the partial response class 4, it is recorded on the magnetic recording medium by the recording means, reproduced by the reproducing means, and equalized to the partial response class 4, so that the partial response class 4 is obtained.
It is possible to effectively perform the Viterbi decoding on the reproduction signal equalized to.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a Viterbi decoder of an embodiment of a data identification device of the present invention.

FIG. 2 is a circuit diagram of a unit circuit (PATH) which replaces the RAM of the Viterbi decoder of the embodiment of the data identification device of the present invention.

FIG. 3 is a time chart of the Viterbi decoder of one embodiment of the data identification device of the present invention.

FIG. 4 is an overall block diagram of a Viterbi decoder of another embodiment of the data identification device of the present invention.

FIG. 5 is a unit circuit (PATH) which replaces the RAM of the Viterbi decoder of another embodiment of the data identification device of the present invention.
It is a circuit diagram of.

FIG. 6 is a circuit diagram of a threshold detection circuit (THD) of a Viterbi decoder of another embodiment of the data identification device of the present invention.

FIG. 7 is a block diagram of a conventional PR4 reproducing / decoding device.

FIG. 8 is a circuit diagram of a conventional NRZI Viterbi decoder.

FIG. 9 is an actual circuit diagram of a conventional NRZI Viterbi decoder.

FIG. 10 is an actual circuit diagram of a comparison operation unit (METRIC) of a conventional NRZI Viterbi decoder.

FIG. 11 is an actual circuit diagram of a memory unit (MEM) of a conventional NRZI Viterbi decoder.

[Explanation of symbols]

 1 Inverter 2 Unit Circuit 3 Unit Circuit 4 Unit Circuit 5 Unit Circuit 10 D Latch 11 D Latch 12 OR Circuit 13 2 Input Selector 20 Threshold Detection Circuit 21 Unit Circuit 22 Unit Circuit 23 Unit Circuit 24 2 Input Selector 25 AND Circuit 30 D Latch 40 Computing Unit 41 Inverter 42 Comparator 43 Comparator 44 OR Circuit

Claims (7)

[Claims] 1. A present indicating that the present data of the transmission signal is confirmed after equalizing the transmission signal precoded in the partial response showing a predetermined bandpass frequency characteristic due to intersymbol interference to the partial response. A data identification device that decodes the transmission signal based on a data confirmation signal and a current data identification result signal indicating the identification result of the current data, and stores a confirmation signal of the data at least a predetermined time before the present of the transmission signal. A latch for storing past data confirmation signal, a latch for storing past data identification result signal that stores an identification result signal of at least data before the present transmission signal, and the present data identification result signal or the past data identification result signal Select one of the past data identification result signals output from the storage latch Update signal indicating that the present data of the transmission signal or at least the data before the present is decided by the vector and the past data decision signal output from the past data decision signal storage latch. An OR circuit for detecting the above, and a unit circuit having at least a plurality of stages are connected in series, and the present data confirmation signal, the present data identification result signal, the update signal and the present data identification result signal or the past data identification result A data identification device, wherein a data identification result of the transmission signal at a predetermined time is output based on the signal. 2. The data identification device according to claim 1, wherein the equalizer for equalizing the partial response and the unit circuits of the plurality of stages are integrated into an integrated circuit. 3. The data identification device according to claim 1, wherein a threshold value detector for detecting a predetermined threshold value based on the transmission signal, and a threshold value detection result of the threshold value detector are stored. And a selector for selecting one of a result of data identification at a predetermined time of the transmission signal output from the unit circuits of the plurality of stages and a threshold detection result output from the latch. When the identification result of the data at the predetermined time of the transmission signal is not determined by the output from the unit circuit of a plurality of stages, the threshold detection result output from the latch is used as the data detection result at the predetermined time of the transmission signal. A data identification device characterized in that an identification result is obtained. 4. The data identification device according to claim 3, wherein the threshold detector comprises a first comparator for comparing the transmission signal with a predetermined set value, and the transmission signal with the predetermined setting. The transmission signal includes a second comparator for comparing the inverted signal of the value, and an OR circuit for outputting the threshold value detection result by the outputs of the first comparator and the second comparator. And the predetermined set value and the inversion signal of the predetermined set value are respectively compared, when the data of the transmission signal is larger than the predetermined set value, and when the data of the transmission signal is the predetermined set value. A data discriminating apparatus, which performs ternary discrimination between an intermediate point between the inversion signal of the predetermined set value and data when the data of the transmission signal is smaller than the inversion signal of the predetermined set value. . 5. The data identifying device according to claim 3, wherein the unit circuits are connected in series in eight stages, and the transmission signal is input to the unit circuits in eight stages, from the final stage of the unit circuits in eight stages. The output transmission signal is input to the threshold value detector, and the transmission signal at the time corresponding to the threshold value detection result of the threshold value detector is taken out from any of the eight-stage unit circuits, A data identification device characterized in that an equalization coefficient of an equalizer for equalizing the partial response is adjusted based on a transmission signal at the time. 6. The data identification device according to claim 3, wherein an equalizer for equalizing the partial response, the unit circuits of a plurality of stages, the threshold detector, the latch, and the selector. A data identification device characterized by being an integrated circuit. 7. The data identification device according to claim 1 or 3, wherein the transmission signal is precoded to partial response class 4 and then recorded on a magnetic recording medium by a recording means and reproduced by a reproducing means. A data identification device characterized by being equalized to a partial response class 4.