JPH08110804A - Data processor - Google Patents

Abstract

PURPOSE: To effectively utilize CPU resources by providing a CPU exclusive for normal instructions and a general CPU. CONSTITUTION: When the CPU 1 exclusive for normal instructions reads out a special instruction while reading out a user program, a request flag indicating that the special instruction is read out is set in the flag area, etc., of a work memory 6. A CPU 2 checks the request flag throughout program execution to judge whether or not the request flag is set, and executes the requested special instruction when the request flag is set. After the special instruction is executed, the general CPU 2 sends a report on the completion of processing to the CPU 1 exclusive for normal instruction to make the CPU 1 exclusive for normal operation execute the normal instructions, and it is judged whether or not the program execution is completed by one scan. When the execution has been completed by one scan, peripheral processing is performed successively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a plurality of C programs.
The present invention relates to a data processing device that is executed by a PU and also executes peripheral processing.

[0002]

2. Description of the Related Art In recent years, for the purpose of high-speed processing, as shown in FIG.
Also, a data processing device has been developed which performs peripheral processing and program execution processing in parallel by the CPUs C and D dedicated to peripheral processing.

[0003]

However, in such a data processing apparatus, the peripheral processing dedicated CPUs C and D can operate in parallel because the peripheral processing is easy to perform in parallel, but the program execution processing is usually parallel. When processing cannot be performed and the program execution-dedicated CPU A is operating, the CPU resources are wasted because the program execution-dedicated CPUB is stopped.

Also, since the CPUs A and B dedicated to the program are normally stopped during the peripheral processing, the C
There is a problem that PU resources are wasted.

Therefore, an object of the present invention is to provide a data processing device which can effectively utilize CPU resources.

[0006]

In order to achieve the above object, according to the invention of claim 1, in a data processing device for executing a program consisting of a normal instruction and a special instruction by a plurality of CPUs and executing peripheral processing. A normal instruction dedicated CPU that sequentially reads each instruction from the program, executes the normal instruction when the normal instruction is read, and outputs an execution request of the special instruction when the special instruction is read, While performing the above peripheral processing,
A general-purpose CPU that executes the special instruction when the special instruction execution request is output from the normal instruction dedicated CPU;
It is characterized by including.

According to a second aspect of the present invention, in the data processing apparatus according to the first aspect, the normal instruction dedicated CPU sequentially reads each instruction from the program, and when a special instruction is read, the special instruction is set by setting a flag. The instruction execution request is output, and the general-purpose CPU checks the flag while the program is being executed by the normal instruction-dedicated CPU, executes the special instruction if the flag is set, and after one scan of the program is completed. It is characterized in that peripheral processing is executed.

According to a third aspect of the present invention, in the data processing apparatus according to the first aspect, the normal instruction dedicated CPU sequentially reads out each instruction from the program, and when a special instruction is read out, an interrupt signal is output to output the instruction. The execution request of the special instruction is output, and the general-purpose CPU normally executes peripheral processing,
When a special command execution request is output from the normal command dedicated CPU by outputting an interrupt signal, the special command is received and the special command is executed.

In a fourth aspect of the present invention, a program consisting of ordinary instructions and special instructions is executed by a normal instruction dedicated CPU and a general-purpose CPU, and peripheral processing is performed by a general-purpose C.
In a data processing device executed by a PU and a CPU dedicated to peripheral processing, when a special instruction is read from the program, an execution request of the special instruction is output to the general-purpose CPU or the CPU dedicated to peripheral processing by setting a flag. Or an inference means for inferring and determining, based on a predetermined evaluation item, whether to output the execution request of the special instruction by outputting an interrupt signal, the normal instruction dedicated CPU sequentially outputs each instruction from the program. reading,
When the normal instruction is read, the normal instruction is executed, while when the special instruction is read, the execution request of the special instruction is output by setting a flag or outputting an interrupt signal based on the determination of the inference means. And the above general-purpose CPU
According to the output method of the execution request from the normal instruction dedicated CPU, the flag is checked during execution of the program by the normal instruction dedicated CPU, and if the flag is set, the special instruction is executed to execute the program. Peripheral processing is executed after the completion of one scan, or when peripheral processing is normally executed and a special instruction execution request is output by the above-mentioned normal instruction dedicated CPU, an interrupt signal is received. And executing the special instruction.

In a fifth aspect of the present invention, a program including normal instructions and special instructions is executed by a plurality of CPUs, and when a special instruction is read from the program in a data processing device that executes peripheral processing. Creates a plurality of genes using as a parameter whether to output the execution request of the special instruction by setting a flag or output the execution request of the special instruction by outputting an interrupt signal, and based on the parameters of each gene, the above program and A simulation means for simulating peripheral processing and repeating gene duplication, crossover, and mutation to determine a highly evaluated gene, and each instruction is sequentially read from the above program, and when a normal instruction is read, If the special instruction is read while the normal instruction is executed, CPU for outputting a special instruction execution request by setting a flag or outputting an interrupt signal on the basis of a highly evaluated gene parameter determined by the ration means, and an execution request from the normal instruction dedicated CPU. Depending on the output method, the flag is checked during execution of the program by the CPU dedicated to normal instructions, and if the flag is set, a special instruction is executed and peripheral processing is executed after one scan of the program, or A general-purpose CPU that normally executes peripheral processing and, when a special instruction execution request is output from the normal instruction dedicated CPU by outputting an interrupt signal, receives the interrupt signal and executes the special instruction. It is characterized by having.

[0011]

According to the first aspect of the present invention, a CPU dedicated to normal instructions is used.
Reads each instruction in sequence from the program, executes the normal instruction when the normal instruction is read, outputs an execution request of the special instruction when the special instruction is read, and the general-purpose CPU In addition to executing the processing, when the special command execution request is output from the normal command dedicated CPU, the special command is executed.

According to a second aspect of the present invention, in the data processing apparatus according to the first aspect, the normal instruction dedicated CPU sequentially reads each instruction from the program, and when the special instruction is read, the flag is set by the flag. The execution request of the special instruction is output, and the general-purpose CPU checks the flag while the program is being executed by the normal instruction-dedicated CPU, executes the special instruction if the flag is set, and ends one scan of the program. After that, peripheral processing is executed.

According to a third aspect of the present invention, in the data processing apparatus according to the first aspect, the normal instruction dedicated CPU sequentially reads each instruction from the program, and when a special instruction is read, an interrupt signal is output. The execution request of the special instruction is output, the general-purpose CPU normally executes peripheral processing, and when the execution instruction of the special instruction is output by the output of the interrupt signal from the CPU dedicated to the normal instruction, the interrupt is issued. Receive the signal and execute the special instruction.

According to the fourth aspect of the present invention, first, when a special instruction is read from the program by the inference means provided in the normal instruction dedicated CPU or the general-purpose CPU, an execution request for the special instruction is issued by setting a flag. Output
Alternatively, whether or not to output the execution request of the special instruction is output based on a predetermined evaluation item by the output of the interrupt signal.

Then, the normal instruction dedicated CPU sequentially reads each instruction from the program, executes the normal instruction when the normal instruction is read, and executes the normal instruction when the special instruction is read based on the decision of the inference means. The execution request of the special instruction is output by setting a flag or outputting an interrupt signal. The general-purpose CPU checks the flag while the program is being executed by the normal instruction-dedicated CPU according to the output method of the execution request from the normal instruction-dedicated CPU, executes the special instruction if the flag is set, and executes the program. The peripheral processing is executed after the completion of one scan of the
When a special command execution request is output from U by outputting an interrupt signal, the special signal is executed by receiving the interrupt signal.

In a fifth aspect of the invention, first, the simulation means outputs a request for executing the special instruction by setting a flag or outputs an interrupt signal when the special instruction is read from the program. Generating a plurality of genes with the output of the execution request of the special command as a parameter, simulating the above program and peripheral processing based on the parameters of each gene, repeating duplication, crossover, mutation of each gene to evaluate. Determine high genes.

The CPU dedicated to normal instructions sequentially reads each instruction from the program, executes the normal instruction when the normal instruction is read, and determines the special instruction by the simulation means when the special instruction is read. Is it a set of flags based on the parameters of highly evaluated genes,
Alternatively, an execution request of the special instruction is output by outputting an interrupt signal. The general-purpose CPU checks the flag while the program is being executed by the normal instruction-dedicated CPU according to the output method of the execution request from the normal instruction-dedicated CPU, executes the special instruction if the flag is set, and executes the program. The CPU executes the peripheral processing after the end of one scan of
When the execution request of the special instruction is output by the output of the interrupt signal from, the special instruction is executed in response to the interrupt signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A programmable controller (hereinafter referred to as "PLC") will be described below as an embodiment of a data processing device according to the present invention.
Say. ) Will be described with reference to the drawings.

FIG. 1 shows the configuration of a PLC according to the present invention.

This PLC is a CPU dedicated to normal instructions for reading out a user program and executing normal instructions, which are almost all the instructions in the user program, such as basic instructions.
1 and special instructions in the user program, as will be described later,
For example, a general-purpose CPU 2 that executes application instructions and the like and peripheral processing, CPUs 3 and 4 dedicated to peripheral processing that execute only peripheral processing, a system memory 5, and a work memory 6
A user program memory 7, an I / O memory 8,
It has an I / F 9 to which an external connection device such as an I / O device (not shown) is connected.

Program execution dedicated CPU 1 and general-purpose C
In the first embodiment, the PU 2 is configured to perform a special instruction execution request and an execution process by a polling method described later.

The general-purpose CPU 2 and the peripheral processing dedicated C
Each of the PUs 3 and 4 is configured to execute each peripheral process that is predetermined or selected as necessary according to the contents of each peripheral process.

Next, the operation of each embodiment of the PLC according to the present invention will be described with reference to the drawings.

FIG. 2 shows processing on the side of the general-purpose CPU 2 according to the polling method of the first embodiment.

First, although not shown in this figure, if the normal instruction dedicated CPU 1 reads the special instruction during the reading of the user program, it indicates that the special instruction has been read into the flag area or the like of the work memory 6. Set the request flag.

The general-purpose CPU 2 always checks the request flag during execution of the program (step 10
0), it is judged whether or not the request flag is set (step 110), and when the request flag is set (step 110 “Yes”), the requested special instruction execution process is performed (step 110). Step 120).

After the execution of the special instruction, the general-purpose CPU 2 sends a processing completion notification to the normal instruction dedicated CPU 1 (step 130), causes the normal instruction dedicated CPU 1 to execute the normal instruction, and the program execution is completed for one scan. It is determined whether or not (step 140).

If the execution of the program has not been completed for one scan (step 140 "No"), the above steps 100 to 140 are repeated, while the execution of the program has been completed for one scan. (Step 140 "Yes"), then peripheral processing is performed (step 150), and when this peripheral processing is completed, the processing from step 100 is repeated.

Therefore, according to the first embodiment, the general-purpose C
The PU2 always checks the request flag during the program execution, executes the special command if the request flag is set, and executes the peripheral processing when the program execution is completed. It will be available.

Next, a second embodiment of the present invention will be described.

In the PLC according to the second embodiment, the normal instruction dedicated CPU reads a special instruction from the program and outputs the execution request of the special instruction, unlike the polling method of the first embodiment, which will be described later. It is configured to output the execution request by the (interruption) method.

Since the configuration of the PLC according to the second embodiment is similar to that of the PLC according to the first embodiment shown in FIG. 1, the description thereof will be omitted and the second configuration based on FIG.
The output operation of the execution request by the interrupt method of the embodiment will be described.

FIG. 3 shows execution processing on the side of the general-purpose CPU 2 according to the interrupt method of the second embodiment.

In the case of the second embodiment, a general-purpose CPU is usually used.
If there is no interrupt from the CPU 1 dedicated to the normal instruction (step 200 “No”), the step 2 executes peripheral processing if there is peripheral processing to be processed regardless of the execution of the program (step 210).

Although not shown in this figure, when the normal instruction dedicated CPU 1 reads a special instruction during the reading of the user program, an interrupt signal is sent to the general-purpose CPU 2 as an execution request of the special instruction. .

The general-purpose CPU 2 receives an interrupt from the CPU 1 dedicated to normal instructions (step 200 "Ye").
s "), the special instruction read out by the normal instruction dedicated CPU 1 executes the special instruction (step 220), and after the execution of the special instruction,
A completion notice is sent to the CPU 1 dedicated to normal instructions (step 23
0) and then peripheral processing is performed (step 210).

Therefore, according to the second embodiment, as in the case of the first embodiment, the general-purpose CPU 2 executes not only the special instruction in the user program but also the peripheral processing, so that the CPU resources are saved. It can be used effectively.

Further, in the second embodiment, since the interrupt method by the interrupt signal is adopted as the communication method of the execution request between the normal instruction dedicated CPU 1 and the general purpose CPU 2, the general purpose even during the execution of the user program. Since the CPU 2 can execute the peripheral processing unless the special instruction is executed, the CPU resources can be used more effectively.

The advantages and disadvantages of the polling method according to the first embodiment and the interrupt method according to the second embodiment will be described below.

When the polling method of the first embodiment is adopted, it has an advantage that no interrupt overhead occurs during program execution, but has a disadvantage that the general-purpose CPU 2 cannot execute peripheral processing during program execution. On the contrary, when the interrupt method of the second embodiment is adopted, on the contrary, the general-purpose C is executed during the program execution.
While PU2 has the advantage that it can execute peripheral processing, it has the disadvantage that interrupt (interrupt) overhead occurs during program execution.

Specifically, the approximate cycle time when the polling method and the interrupt method are used as the communication method of the execution request between the CPUs is as follows. For simplification, the flag check time in the polling method, the time by the completion notification, etc. will be ignored in the description.

First, various times are defined as follows.

Overhead due to one interrupt occurrence To (ns) Average execution time of one instruction executed by the CPU 1 dedicated to normal instruction Ta (ns) Average execution time of one instruction executed by the general-purpose CPU 2 Tb (ns) Dedicated to normal instruction Average number of instructions executed by CPU1 in one cycle Na (number) Average number of instructions executed by general-purpose CPU2 in one cycle Nb (number) Average load of peripheral processing processed in one cycle Tp (ns) At this time, polling method The cycle time Tpol and the cycle time Tint of the interrupt method are
Calculated as: However, all peripheral processes can be processed in parallel even during program execution.

Tpol = NaTa + NbTb + Tp Tint = NaTa + Nb (Tb + To) + (Tp-Na
Ta) = NbTb + Tp + NbTo Therefore, it can be seen from the above equation 2 which of the polling method and the interrupt method is superior depending on the magnitude relation between “NaTa” and “NbTo”.

That is, when the overhead To associated with the occurrence of one interrupt is large, or when the average number of instructions Nb executed by the general-purpose CPU 2 in one cycle is large, the cycle time of the polling method becomes small. On the other hand, the average number of instructions N to be executed in one cycle by the normal instruction dedicated CPU 1
When a is large, or when the average execution time Ta of one instruction executed by the normal instruction dedicated CPU 1 is large, that is, when the load on the normal instruction dedicated CPU 1 is large, the interrupt system cycle time becomes shorter.

Therefore, which communication method should be selected cannot be easily determined because a plurality of factors are intricately related to each other.

Therefore, the selection method is as follows: (1) A method of checking a predetermined evaluation item at the time of executing the user program, inferring it based on the evaluation item, and changing to a communication method with a short cycle time.

(2) A method of constructing a communication method with a short cycle time by trial and error by performing a simulation before or during execution.

There are two possible methods, and the method (1) is adopted in the third embodiment described below, and the method (2) is adopted.
This method is adopted in the fourth embodiment described next.

Next, a third embodiment of the present invention will be described.

As described above, in the third embodiment, a predetermined evaluation item is checked at the time of execution, and based on this, the polling method and the second method of the first embodiment, which is a communication method between the normal instruction CPU and the general-purpose CPU. It is configured to change the interrupt method of the embodiment, and is characterized by adopting fuzzy inference as an inference method for changing the communication method and providing a fuzzy inference unit in a general-purpose CPU.

FIG. 4 shows the configuration of the PLC according to the third embodiment.

4 is the same as the PLC of the first embodiment shown in FIG. 1 except for the specific structure of the general-purpose CPU 2, the same reference numerals are given and the description thereof is omitted.
The specific configuration and the operation thereof will be described.

The general-purpose CPU 2 infers a special instruction executing unit 21 for executing a special instruction in a user program, a peripheral processing unit 22 for executing peripheral processing, and a predetermined evaluation item, as will be described later, to infer the program. When a special instruction is read from the inside, the fuzzy inference unit 23 determines whether to output the execution request of the special instruction by setting a flag or output the execution request of the special instruction by outputting an interrupt signal. And have.

When a predetermined evaluation item at the time of fuzzy inference in the fuzzy inference unit 23 is shown by a rule, for example, rule 1; the interrupt method is advantageous when the general-purpose CPU 2 performs many processes in parallel during program execution. Is.

Rule 2: When the performance of peripheral processing is emphasized as a user's request, the interrupt method is advantageous.

Rule 3; General-purpose C in the user program
The polling method is more advantageous when instructions that use PU2 occur frequently.

It becomes

If this is rewritten by the if-then expression, rule 1; if (the processing that the general-purpose CPU 2 can perform in parallel is
Many (evaluation = interrupt method advantageous) Rule 2; if (performance of required peripheral processing = high speed) then (evaluation = interrupt method advantageous) Rule 1; if (requested CPU usage frequency = rare) then (evaluation) = Advantage of interrupt method).

FIGS. 5A to 5C show the rules 1 to 1 above.
3 shows a membership function of 3.

(A) shows the membership function of rule 1, where the horizontal axis indicates the number of processes that can be performed in parallel.
The vertical axis shows the matching degree (0.0
It takes a value between ~ 1.0).

(B) shows the membership function of rule 2, which shows the required performance of peripheral processing. The horizontal axis shows the response speed (seconds), and the vertical axis shows the matching with the interrupt method. I am taking a degree.

(C) shows the membership function of the number of times the general-purpose CPU is used, and the horizontal axis shows the number of times of use (times / time).
Second), and the vertical axis represents the degree of matching with the interrupt method.

Therefore, the fuzzy inference unit 23 determines the superiority of the direct interrupt method (0.0) from the values of the membership functions of the rules 1 to 3 which are evaluation items.
(Value between ~ 1.0) is obtained, so take this average, and if this average is greater than 0.5, use the interrupt method,
If it is smaller than that, the polling method can be decided.

Next, the operation of the third embodiment will be described with reference to the drawings.

FIG. 6 shows a method of determining an inter-CPU execution request by fuzzy inference according to the third embodiment.

In the fuzzy inference unit 23, first, the special instruction execution unit 21 of the normal instruction dedicated CPU 1 or the general purpose CPU 2 executes the user program, or the peripheral processing unit 2 of the general purpose CPU 2 is executed.
2 and the peripheral processing-dedicated CPUs 3 and 4 execute the peripheral processing to obtain the evaluation value of each evaluation item (step 30).
0). In the initial state, the CPU 1 dedicated to normal instructions is used.
It is assumed that the communication method between the CPU and the general-purpose CPU 2 is preset to either the polling method or the interrupt method.

Then, the fuzzy inference unit 23 substitutes the evaluation value into each membership function of the corresponding rules 1 to 3 to perform fuzzy inference, and the inference result, that is, matching of rules 1 to 3. Then, the average of the communication methods is calculated, the communication method such as the interrupt method or the polling method is determined, and the instruction of the determined communication method is sent to the CPU 1 dedicated to the normal instruction (step 310).

Upon receiving the instruction of the communication system, the normal instruction dedicated CPU 1 changes the communication system of the execution request to the general-purpose CPU 2 based on the communication system (step 320).

After that, the CPU 1 for exclusive use of normal instructions sequentially reads out the instructions from the user program. When the normal instructions are read out, the normal instructions are executed, while when the special instructions are read out, the fuzzy inference unit 23 newly creates new instructions. Usually, the execution request is output by the communication method that is most suitable for the user program being executed, such as sending the execution request from the normal instruction dedicated CPU 1 to the general-purpose CPU 2 according to the determined communication method, and reducing the cycle time. Is performed (step 330).

Therefore, according to the third embodiment, it is determined whether the communication method for the execution request between the normal instruction dedicated CPU and the general purpose CPU is the polling method or the interrupt method when the user program is executed. Since the communication method with the smaller cycle time is determined by inferring the fuzzy inference, it is possible to dynamically select the communication method of the execution request with the smaller cycle time that suits the user's needs according to the user program.
CPU resources can be effectively used.

In the third embodiment, the general-purpose CPU 2
Although the fuzzy inference unit 23 is provided in the above description, the fuzzy inference unit 23 may be provided in the peripheral processing dedicated CPU 4 or the normal instruction dedicated CPU 1. However, when the fuzzy inference unit 23 is provided in the normal instruction dedicated CPU 1, the execution speed of the normal instruction by the normal instruction dedicated CPU 1 decreases, so that the general purpose CPU 2 or the peripheral processing dedicated CPU is as much as possible.
The fuzzy inference unit 23 is provided in 3 and 4.

Further, in the third embodiment, the general-purpose CPU 2
However, in the case where there is a plurality of general-purpose CPUs 2 and any general-purpose CPU 2 may execute the special instruction executed by the general-purpose CPU 2, the normal-instruction-dedicated CPU 1 and the general-purpose CPU 2 may be connected to each other. In addition to determining the communication method, it is necessary to determine which general-purpose CPU 2 to select.

For example, in order to determine which general-purpose CPU 2 should be selected when a special instruction is read by fuzzy inference, the following rules 4 to 6 can be considered.
Rule 4: If there is a general-purpose CPU with the lightest processing load at present, that general-purpose CPU is used.

Rule 5: If there is a general-purpose CPU capable of executing the corresponding processing at high speed, the general-purpose CPU is used.

Rule 6; If there is another general-purpose CPU that can execute many other processes, the general-purpose CPU is not used.

If these rules 4 to 6 are represented by membership functions and fuzzy inference is performed based on each rule,
The optimum general-purpose CPU 2 can be selected from among a large number of general-purpose CPUs 2 at that time.

Next, a fourth embodiment of the present invention will be described.

In the fourth embodiment, as described above, by introducing a simulation before or during execution of the user program, a system with a short cycle time is constructed by trial and error, and this is also achieved. In addition, a method for changing the polling method and the interrupt method, which are communication methods for execution requests between CPUs, uses a genetic algorithm (GA) for changing the communication method for execution requests.

FIG. 7 shows the configuration of the PLC according to the fourth embodiment.

The PLC according to the fourth embodiment has two normal instruction dedicated CPUs 1a, which execute different normal instructions.
1b and two general-purpose CPUs 2a and 2b that execute different special instructions and peripheral processing, respectively, and simulate the communication system of execution requests between the CPUs by adopting a genetic algorithm described later. As a result, the simulation device 10 that determines the communication method of the inter-CPU execution request with the smallest cycle time is connected via the interface 9.

The same components as those of the PLC according to the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof is omitted. The peripheral processing dedicated CPU is omitted for convenience. It may be provided.

FIGS. 8A and 8B respectively show a model for applying the genetic algorithm to the execution request communication system between the CPUs, and the genes in this model.

(A) shows a communication system between the CPUs, from the normal instruction dedicated CPU 1a to the normal instruction dedicated CPU.
Communication method of execution request to 1b is Wab, normal instruction dedicated C
The communication method of the execution request from the PU 1a to the general-purpose CPU 2a is Wac, and the communication method of the execution request from the normal instruction dedicated CPU 1a to the general-purpose CPU 2b is Wad.

Further, the communication method of the execution request from the normal instruction dedicated CPU 1b to the normal instruction dedicated CPU 1a is shown by Wba, and the normal instruction dedicated CPU 1b to the general purpose CPU 2a are shown.
Wbc as the communication method of execution request to
The communication method of execution request from U1b to general-purpose CPU2b is W
It is shown by bd.

In (b), gene G is created by using six execution request communication methods Wab to Wbd between the CPUs as parameters, and "0" is the first execution request communication method between the CPUs. This indicates that the polling method of the second embodiment is adopted, and "1" indicates that the interrupt method of the second embodiment is adopted as the communication method of the execution request between the CPUs.

The simulation apparatus 10 stores a plurality of such genes G in a gene pool (not shown), and evolves these genes G by simulation by a genetic algorithm described later to find an optimum gene. It is configured to grow on the gene pool.

Next, the operation of the fourth embodiment will be described with reference to the drawings.

FIG. 9 shows a method of determining a communication system for execution requests between CPUs according to the genetic algorithm of the fourth embodiment.

In the simulation apparatus 10, first, each gene G shown in FIG. 8B in the gene pool (not shown) is duplicated according to the previous evaluation (step 400), and then each of these gene G is reproduced. (Step 41
0), further mutate gene G with a certain probability (step 420) to evolve gene G.

Then, in the simulation device 10,
Simulation of user program execution and peripheral processing execution is performed based on all the genes G in the gene pool, and each gene G is evaluated from the program execution time and the cycle time (step 430, step 440 “N”).
o ”).

When the simulation and evaluation have been completed for all genes G (step 440 “Yes”),
In order for the gene G to evolve, the replication / crossover / mutation of the gene G and the simulation / evaluation processing (steps 400 to 440) for all the genes G are repeated until a sufficient number of times is reached (step 450 "N
o ”), if a sufficient number is reached (step 450
"Yes"), the evolution of genes is terminated, and the gene G, which has the highest evaluation at present, is selected as the one that indicates the optimal communication method of execution requests between CPUs with the smallest cycle time (step 460). ).

Then, based on the gene G selected in this way, for example, when the normal instruction dedicated CPU 1a reads an instruction from the user program and executes the normal instruction for its own CPU, the normal instruction dedicated CPU 1b If the normal instruction for
While the execution request is sent to the normal instruction dedicated CPU 1b by the communication method indicated by b, when the special instruction for the general purpose CPU 2b is read out, the execution request is sent to the general purpose CPU 2b by the communication method indicated by the optimum gene G Wad. Then, each instruction is executed.

Therefore, according to the fourth embodiment, whether the communication method for the execution request between the normal instruction dedicated CPU and the general-purpose CPU is the polling method or the interrupt method is represented by a gene, and before execution of the user program. Alternatively, a program execution and peripheral processing simulation are performed using this gene at the time of execution, and the communication method of the execution request between the CPUs having the smallest cycle time is determined by a genetic algorithm by trial and error. Even when there are a plurality of dedicated CPUs or general-purpose CPUs, it is possible to select an optimal communication method for execution requests between the CPUs and effectively use the CPU resources.

In each of the above embodiments, the PLC is used as an embodiment to describe the data processing device of the present invention. However, the present invention is not limited to the PLC, and can be applied to other general computer data processing devices. Can be applied.

[0096]

As described above, according to the first to fifth aspects of the invention, the general-purpose CPU executes not only the special instruction in the program but also the peripheral processing, so that the CPU resources are effectively used. Available.

Further, according to the third aspect of the invention, since the interrupt method by the interrupt signal is adopted as the communication method of the execution request between the normal instruction dedicated CPU 1 and the general purpose CPU 2, the general purpose even during the execution of the user program. CPU
Since No. 2 can execute peripheral processing if no special instruction is executed, CPU resources can be used more effectively.

According to the fourth aspect of the present invention, whether the communication method of the execution request between the normal instruction dedicated CPU and the general-purpose CPU is the polling method or the interrupt method is a predetermined evaluation item when the user program is executed. Since the communication method with the shorter cycle time is determined by the fuzzy inference, it is possible to dynamically select the communication method for the execution request with the shorter cycle time that meets the user needs according to the user program.

According to the fifth aspect of the present invention, whether the communication method of the execution request between the normal instruction dedicated CPU and the general-purpose CPU is the polling method or the interrupt method is expressed by a gene, and the user program is executed. Before or during execution, this gene was used to simulate program execution and peripheral processing, and the communication method of execution requests between CPUs with the smallest cycle time was determined by trial and error using a genetic algorithm. Even when there are a plurality of instruction-dedicated CPUs and general-purpose CPUs, the optimum communication system for execution requests between the CPUs can be selected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLC according to the present invention.

FIG. 2 is a general-purpose CPU according to a polling method of the first embodiment.
The flowchart which shows the process of the 2nd side.

FIG. 3 is a general-purpose CP according to the interrupt method of the second embodiment.
The flowchart which shows the execution process on the U2 side.

FIG. 4 is a block diagram showing a configuration of a PLC according to a third embodiment.

5A to 5C are explanatory diagrams showing membership functions of rules 1 to 3 in fuzzy inference, respectively.

FIG. 6 is a flowchart showing the operation of the third embodiment.

FIG. 7 is a block diagram showing a configuration of a PLC according to a fourth embodiment.

8A and 8B are explanatory diagrams showing a model for applying a genetic algorithm to a communication system for execution requests between CPUs and genes in the model.

FIG. 9 is a CPU according to the genetic algorithm of the fourth embodiment.
9 is a flowchart showing a method of determining a communication method of execution requests between the two.

FIG. 10 is an explanatory diagram showing parallel processing in conventional data processing.

[Explanation of Codes] 1 CPU for exclusive use of normal instructions 2 General-purpose CPU 3 CPU for exclusive use of peripheral processing 4 CPU for exclusive use of peripheral processing 21 Special instruction execution unit 22 Peripheral processing unit 23 Fuzzy inference unit 1a CPU for exclusive use of ordinary instructions 1b CPU for exclusive use of ordinary instructions 2a General purpose CPU 2b General-purpose CPU 10 Simulation device G gene

Claims (5)

[Claims] 1. In a data processing device for executing a program including a normal instruction and a special instruction by a plurality of CPUs and executing peripheral processing, when each instruction is sequentially read out from the program and the normal instruction is read out, While executing the normal instruction, when the special instruction is read out, the normal instruction dedicated CPU that outputs an execution request of the special instruction, and the peripheral processing, and the normal instruction dedicated CP
A data processing apparatus comprising: a general-purpose CPU that executes a special command when a special command execution request is output from U; 2. The normal instruction dedicated CPU sequentially reads each instruction from the program, and outputs a special instruction execution request by setting a flag when the special instruction is read, and the general-purpose CPU exclusively uses the normal instruction. 2. The program is executed by the CPU, the flag is checked, and if the flag is set, a special instruction is executed, and peripheral processing is executed after one scan of the program is completed. Data processing device. 3. The normal instruction dedicated CPU sequentially reads each instruction from the program, and when the special instruction is read, outputs an execution request of the special instruction by outputting an interrupt signal. The CPU executes the processing, and when the special instruction execution request is output from the normal instruction dedicated CPU by the output of the interrupt signal, the special instruction is received and the special instruction is executed. 1. The data processing device according to 1. 4. A data processing device for executing a program comprising normal instructions and special instructions by a normal instruction dedicated CPU and a general-purpose CPU, and executing peripheral processing by the general-purpose CPU and peripheral-processing dedicated CPU. When a special instruction is read from the program to the dedicated CPU, it is determined whether the execution request of the special instruction is output by setting a flag or the execution request of the special instruction is output by outputting an interrupt signal. An inference means for inferring and determining based on the evaluation item is provided, and the CPU for exclusive use of normal instructions sequentially reads each instruction from the program, and when the normal instruction is read, the normal instruction is executed, while the special instruction is executed. Read, the flag is set or an interrupt is made based on the decision of the above inference means. An execution request for the special instruction is output by outputting a signal, and the general-purpose CPU checks the flag while the program is being executed by the normal instruction-dedicated CPU according to the output method of the execution request from the normal instruction-dedicated CPU. If the above flag is set, a special instruction is executed and peripheral processing is executed after one scan of the program is completed, or normally peripheral processing is executed and special CPU is generated by outputting an interrupt signal from the normal instruction dedicated CPU. A data processing device, which receives an interrupt signal when an instruction execution request is output and executes the special instruction. 5. A data processing device for executing a program comprising a normal instruction and a special instruction by a plurality of CPUs and executing peripheral processing, when the special instruction is read from the program, the flag is set. A plurality of genes are created using as a parameter whether to output the execution request of the special instruction or to output the execution request of the special instruction by outputting the interrupt signal, and the above program and peripheral processing are simulated based on the parameters of each gene. , A simulation means for determining a highly evaluated gene by repeating duplication, crossover, and mutation of each gene, and sequentially reading each instruction from the program, and when the normal instruction is read, the normal instruction is executed. , When the special command is read, the simulation means A normal instruction dedicated CPU that outputs an execution request of the special instruction by setting a flag or outputting an interrupt signal based on the determined highly evaluated gene parameter, and an execution request output method from the normal instruction dedicated CPU Accordingly, during execution of the program by the normal instruction dedicated CPU, the flag is checked, and if the flag is set, a special instruction is executed and peripheral processing is executed after one scan of the program, or normally, A general-purpose CPU that executes processing and receives the interrupt signal to execute the special instruction when a special instruction execution request is output by outputting the interrupt signal from the normal instruction dedicated CPU. A data processing device characterized by: