JPH06250985A - Information processor - Google Patents

Abstract

PURPOSE:To maintain the enough I/O function with external devices without adding its I/O terminal even when an external sub processor is a connectable main processor. CONSTITUTION:For example, when a sub CPU 41 is judged to be not connected by a check signal through external processor connection terminals 23a and 23b of a main CPU 21, the external information I/O and its processing are executed with a system bus 24 from ax integer arithmetic control section 27 through a bus control circuit 31. The external information I/O and its processing are executed with the system bus 24 from an information collection circuit 33 through an information I/O circuit 33. When the external CPU 41 is judged to be connected, the information I/O and its processing between the main CPU 21 and the system bus 24 can be performed from an interface circuit 46 through an information I/O circuit 47 other than the high performance arithmetic processing in the sub CPU 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in a computer system, in which a sub processor is built in a main processor (CPU) and a sub processor dedicated to arithmetic operation can be connected to the outside of the main processor.

[0002]

2. Description of the Related Art FIG. 6 shows a C in which a sub processor (sub CPU) 12 is connected to a main processor (main CPU) 11 outside.
It is a block diagram which shows the structure of the conventional information processing apparatus which has a PU system.

That is, the main processor 11 is usually
A sub-processor that performs data input / output processing and integer arithmetic processing via the system bus based on a preset application program is built-in. In addition to the main processor 11, advanced arithmetic operations such as floating point arithmetic are further performed. The sub-processor 12 for exclusive use only is connected externally to improve the performance of the CPU system.

That is, for example, the main processor 11 reads the command data in the memory 14 on the basis of an instruction from the input / output circuit (keyboard, etc.) 13, and if the content of the instruction is an integer arithmetic processing instruction, it is built in the own processor 11. The sub-processor executes the instruction, and if it is a floating-point arithmetic processing instruction, the external sub-processor 12 executes the instruction. This makes it possible to speed up the advanced arithmetic processing. In this case, the main processor 11
Dedicated connection terminals 12a, 12b, ... For connection with the external sub-processor 12 are provided.

[0005]

However, when the main processor 11 is provided with the connection terminals 12a, 12b, ... Dedicated to the sub processor 12, the main processor 11 is correspondingly provided with the input / output circuit 13 and the memory 14. I / O terminal 11a for connecting to an original external device such as
Since the number of 11b, ... Is limited, high-speed arithmetic processing can be speeded up, but on the other hand, there is a problem that the input / output function with an external device is limited.

Therefore, when the connection terminals 12a, 12b, ... Of the external sub-processor 12 are provided, it is possible to increase the number of input / output terminals 11a, 11b ,. There are problems that the package becomes large and the cost increases.

The present invention has been made in view of the above problems,
An object of the present invention is to provide an information processing device capable of maintaining a sufficient input / output function with an external device without adding an input / output terminal even in a main processor to which an external sub processor can be connected. To do.

[0008]

That is, an information processing apparatus according to the present invention is one in which a sub processor is built in a main processor and the sub processor can be connected to the outside of the main processor. A sub-processor connection terminal that is provided for establishing connection with the external sub-processor, and a sub-processor connection determination that determines whether or not the external sub-processor is connected to the sub-processor connection terminal in the sub-processor inside the main processor Means and the external sub-processor,
The external connection terminal for connecting to an external device and the sub processor connection determining means determines that the external sub processor is not connected to the sub processor connection terminal. The first external information input / output unit for inputting / outputting data to / from an external device, and the sub processor when the sub processor connection determining unit determines that the external sub processor is connected to the sub processor connection terminal. Second external information input / output means for inputting / outputting data to / from the external device from the connection terminal via the external connection terminal of the sub-processor, and the first external information input / output means or the second external information input / output. Means for supplying data from the external device input to the main processor to the internal sub-processor, The processing data from the processor first
The external information input / output means or the information transmission means given to the second external information input / output means.

[0009]

That is, by using the sub-processor connection terminal in the main processor as an input / output terminal with an external device, the function related to, for example, advanced arithmetic processing can be improved while maintaining the input / output function with the external device. It will be.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a single-use configuration of a main processor (main CPU) 21 in the information processing apparatus of the present invention.

The main processor 21 is provided with a plurality of input / output terminals 22a, 22b, ... And external sub-processor connection terminals 23a, 23b ,.
a, 22b, ... Via a system bus 24 including a control bus 24a, an address bus 24b, and a data bus 24c, input / output devices (for example, keyboard, CRT,
Printer 25 and memory devices (eg RAM, ROM,
An external device such as a disk 26 is connected.

Here, a read / write control signal (R / W) for the input / output device 25 and the memory device 26 is transmitted from the main processor 21 to the control bus 24a, and the read / write control signal (R / W) is transmitted to the address bus 24b. Address data indicating the unique address of the write destination is transmitted, and the actual read / write data is transmitted to the data bus 24c.

When the main processor 21 is used alone, the external sub-processor connection terminals 23a, 23b,
The external sub-processor 41 (see FIG. 2) is not connected to the ... And the input / output device 2 via the system bus 24.
5 and an external device such as the memory device 26 are connected.

The main processor 21 includes an integer arithmetic control unit 27, an integer arithmetic register file 28, a floating point arithmetic circuit 29, a register file (1) 30, a bus control circuit 31, an information collecting circuit 32 and a sub CPU interface. / Information input / output circuit 33 is built in.

The integer arithmetic control section 27 analyzes the instruction data given from the memory device 26 via the input / output terminals 22a, 22b, ... And the bus control circuit 31, for example, and carries out four arithmetic operations of integers and comparison processing. In addition to executing logical operation processing, instruction execution control for each built-in block is performed. In this case, the operated data related to the integer operation processing is the integer operation register file 28.
Is stored in the register file 28 for integer operation.

The floating point arithmetic circuit 29 executes a floating point arithmetic up to double precision when a floating point arithmetic instruction is given through the integer arithmetic control unit 27. In this case, the floating point arithmetic processing is performed. The data to be operated on is stored in the register file (1) 30 and the operation result data is stored in the register file (1) 30.

The bus control circuit 31 controls the system bus 24 based on the control signal from the integer arithmetic control unit 27, and controls the data input / output to / from the input / output device 25 and the memory device 26 with respect to the main processor 21. The data input / output information through the bus control circuit 31 is given not only to the integer arithmetic control unit 27 but also to the information collecting circuit 32 and the sub CPU interface / information input / output circuit 33.

The information collecting circuit 32 includes integer operation information and instruction control information in the integer operation control unit 27, floating point operation information in the floating point operation circuit 29, and system bus in the sub CPU interface / information input / output circuit 33. 24, input / output information with other external devices or interface information with the external sub-processor 41 (only when connected), and the bus control circuit 31.
For collecting the data input / output information in the sub-CP.
It is given to the U interface / information input / output circuit 33.

The information collecting circuit 32 collects the operation information in the floating point arithmetic circuit 29 when a quadruple precision floating point arithmetic instruction is given when the external sub-processor 41 is not connected, and collects the integers. Arithmetic control unit 2
A quadruple precision floating point operation is executed by interrupting 7 and the operation information from the floating point operation circuit 29 when the external sub-processor 41 is connected is ignored.

The sub CPU interface / information input / output circuit 33 determines whether or not the external sub processor 41 is connected, and when the external sub processor 41 is not connected, the information via the external sub processor connection terminals 23a, 23b ,. The input / output control is performed and the interface control with the external sub-processor 41 is performed at the time of connection. The external input / output information or interface information in the sub CPU interface / information input / output circuit 33 is
It is given to the information collecting circuit 32.

Here, the sub CPU interface / information input / output circuit 33 is asynchronous with the information obtained from the input / output device 25 under the control of the bus control circuit 31 via the input / output terminals 22a, 22b ,. I / O device 25
Information obtained from the external sub-processor connection terminal 23b
It is input and output via. FIG. 2 is a block diagram showing a configuration in which an external sub processor (sub CPU) 41 is connected to a main processor (main CPU) 21 in the information processing apparatus of the present invention. In FIG. 2, the same components as those of the information processing device in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The sub processor 41 includes main processor connection terminals 42a, 42b, ... And an external information input / output terminal 4.
3a, 43b, ..., The sub-processor 41 is connected to the external sub-processor connection terminals 23a, 23b, ... Of the main processor 21 via its main processor connection terminals 42a, 42b ,. External information input / output terminals 43a, 43b, ... Are connected to the input / output device 25 and the memory device 26 via the system bus 24.

The sub-processor 41 includes a quad precision floating point arithmetic circuit 44 and a register file (2).
45, an interface circuit 46, and an information input / output circuit 47 are incorporated.

The quad precision floating point arithmetic circuit 44 is
Floating point arithmetic processing up to quadruple precision is executed based on an instruction control signal given from the main processor 21 through the interface circuit 46. In this case, the operated data related to the floating point arithmetic processing is It is loaded from the register file (2) 45 based on the load / store control from the interface circuit 46,
The calculation result data is stored in the register file (2) 45.

The interface circuit 46 controls the execution of operations in the quad precision floating point arithmetic circuit 44 based on the instruction signal given from the main processor 21 via the main processor connection terminal 42a, and the register file (2) 45. The load / store execution control of the file data is performed, and the information transmission control between the main processor 21 and the information input / output circuit 47 is performed.
Data input to the information input / output circuit 47 via the system bus 24 or directly from the input / output device 25 is given to the main processor 21 via the interface circuit 46 for processing and is also processed by the main processor 21. The processing data given to the information input / output circuit 47 via 46 is output to the control bus 24 a in the system bus 24. Next, the operation of the information processing apparatus having the above configuration will be described. FIG. 3 is a flowchart showing the initial operation steps of the information processing apparatus.

That is, when the information processing apparatus is started by turning on the system power, for example, first, the external sub-processor connection terminals 23a, 23b,
It is determined whether or not the external sub-processor 41 is connected (step S1).

In other words, when the system power is turned on, predetermined check data is output from the integer arithmetic control unit 27 via the sub CPU interface / information input / output circuit 33 from the external sub processor connection terminals 23a, 23b ,. At this time, if predetermined response data is not input to the sub CPU interface / information input / output circuit 33 via the external sub processor connection terminals 23a, 23b, ... At this time, the external sub processor 41 is connected. If it is determined that there is not, and if predetermined response data is input to the sub CPU interface / information input / output circuit 33, it is determined that the external sub processor 41 is connected.

The connection determination process of the external sub-processor 41 with respect to the main processor 21 is performed by the memory device 26.
The unique data indicating "connected" of the external sub-processor 41 is stored in advance for the fixed address of the integer sub-processor 41, and when the system power is turned on, the integer arithmetic control unit 2 of the main processor 21 is stored.
7 may be instructed to read the data in the fixed address in the memory device 26 via the bus control unit 31, and the determination may be made based on the content of the data read by the integer operation control unit 27.

That is, in the step S1, for example, the sub CPU interface of the main processor 21 /
When the response data is not input to the check data output from the information input / output circuit 33 and it is determined that the external sub-processor 41 is not connected, the external sub-processor connection terminals 23a and 23b of the main processor 21 are connected. ，
As shown in FIG. 1, external devices such as the input / output device 25 and the memory device 26 are connected to the ... FIG. 4 is a flow chart showing the operation of the above information processing apparatus when the external sub-processor 41 is not connected.

When the main processor 21 determines that the external sub-processor 41 is not in the connected state, first, the integer arithmetic control unit 27 causes the bus control circuit 31 to send the instruction data to the memory device 26 via the system bus 24. Is instructed and it is determined whether or not the instruction can be read (step S2).

Here, for example, when the memory device 26 does not perform data access with any other external device and the instruction can be read, it is designated via the bus control circuit 31 and the address bus 24b. Memory device 2
The instruction data stored in the read address of No. 6 is read out via the data bus 24c and read into the integer arithmetic control unit 27 of the main processor 21 (step S
3).

On the other hand, when the memory device 26 makes some data access with another external device and the instruction cannot be read, for example, the bus control circuit 31, the information collecting circuit 32, the sub CPU interface. / When a signal input from an external device is required according to the error cyclic check (ECC) function obtained by the information input / output circuit 33, a signal from the system bus 24 is transmitted via the external sub-processor connection terminals 23a, 23b ,. Sub C above
It is input to the PU interface / information input / output circuit 33 (steps S4 and S5).

Here, an error has occurred in the signal from the external device obtained from the sub CPU interface / information input / output circuit 33 to the information collecting circuit 32, and the ECC is generated.
When the repair is required according to the function, the error signal from the external device is repaired by the information collecting circuit 32, the integer arithmetic control unit 27 and the like, and again as a normal signal the sub CPU interface / information input / output circuit 33. Is output to the control bus 24a via the external sub-processor connection terminal 23a (steps S6 to S9).

On the other hand, in step S3, when the instruction data is read from the memory device 26 into the integer operation control unit 27 of the main processor 21, the content of the instruction is an integer operation instruction, or the load / store of data is performed. It is analyzed whether it is an instruction, and the processing according to the instruction is executed (step S10).

That is, in step S10,
When the instruction data is an integer operation instruction or an integer data load / store instruction, the instruction execution is executed between the integer operation control unit 27 and the integer operation register file 28, and the operation data is also executed. The load / store processing of the etc. is performed from the bus control circuit 31 to the input / output terminals 22a
22b, ... Or from the information collecting circuit 32 via the sub CPU interface / information input / output circuit 13 and the external sub processor connection terminals 23a, 23b ,. (Steps S10 → S11 to S16).

Here, when the processing end instruction is added after the integer operation instruction or the data load / store instruction in the instruction data read by the integer operation control unit 27 in step S3, the main processor 21 The process inside and outside is completed (step S17).

On the other hand, in step S10, when the instruction data read by the integer arithmetic control unit 27 is a floating point arithmetic instruction or a floating point data load / store instruction, the instruction execution is a floating point arithmetic operation. It is executed between the circuit 29 and the register file (1) 30, and the load / store processing of the operation data etc.
From the bus control circuit 31 via the input / output terminals 22a, 22b, ... Or from the information collecting circuit 32 to the sub CPU
This is executed as needed with the system bus 24 via the interface / information input / output circuit 13 and the external sub-processor connection terminals 23a, 23b, ... (Steps S10 → S18 to S23).

Here, when the floating-point operation instruction is a quadruple precision operation instruction, the floating-point operation circuit 29 transmits the operation information to the integer operation control section 27 via the information collecting circuit 32. Then, the activation of software emulation is notified. Then, the integer arithmetic control unit 27 executes the floating point arithmetic instruction by software emulation using a plurality of integer instructions, and then returns to the processing of step S2 and thereafter.

On the other hand, in step S1, for example, predetermined response data is input to the check data output from the sub CPU interface / information input / output circuit 33 of the main processor 21, and the external sub processor 41 is connected. If it is determined that the external sub-processor connection terminals 23a, 23b,
As shown in FIG. 2, the external sub-processor 41 is connected to the ...
External devices such as the input / output device 25 and the memory device 26 are connected to the a and 43b via the system bus 24. FIG. 5 is a flow chart showing the operation of the above information processing apparatus when the external sub-processor 41 is connected.

When the main processor 21 determines that the external sub-processor 41 is in the connection state, first, the integer arithmetic control unit 27 causes the bus control circuit 31 to send instruction data to the memory device 26 via the system bus 24. Is instructed, and it is determined whether or not the instruction can be read (step S24).

Here, for example, when the memory device 26 does not perform data access with any other external device and the instruction can be read, designation is made via the bus control circuit 31 and the address bus 24b. Memory device 2
The instruction data stored in the read address of No. 6 is read out via the data bus 24c and read into the integer arithmetic control unit 27 of the main processor 21 (step S2).
5).

On the other hand, when the memory device 26 makes some data access with another external device and the instruction cannot be read, for example, the bus control circuit 31 and the information collecting circuit on the main processor 21 side. 32, the sub CPU interface / information input / output circuit 33, and the error cyclic check (E) obtained by the interface circuit 46 and the information input / output circuit 47 on the external sub processor 41 side.
When a signal input from an external device is required according to the CC) function, a signal from the system bus 24 is transferred from the information input / output circuit 47 through the external information input / output terminals 43a, 43b, ... Four
6 and is input to the sub CPU interface / information input / output circuit 33 of the main processor 21 (steps S26 and S27).

Here, an error has occurred in the signal from the external device obtained from the sub CPU interface / information input / output circuit 33 to the information collecting circuit 32, and the ECC is generated.
When the repair is required according to the function, the error signal from the external device is repaired by the information collecting circuit 32, the integer arithmetic control unit 27 and the like, and again as a normal signal the sub CPU interface / information input / output circuit 33. From the information input / output circuit 47 to the external information input / output terminal 4
It is output to the control bus 24a via 3a (steps S28 to S31).

On the other hand, in step S25, when instruction data is read from the memory device 26 into the integer operation control unit 27 of the main processor 21, the content of the instruction is an integer operation instruction or integer data executable by the main processor 21. Load / store instruction, a quadruple-precision floating-point operation instruction that can be executed by the sub-processor 41, or its data load / store instruction, and the process according to the instruction is executed (step S32). .

That is, in step S32,
When the instruction data is an integer operation instruction or an integer data load / store instruction, the instruction execution is executed between the integer operation control unit 27 and the integer operation register file 28, and the operation data is also executed. The load / store processing of the etc. is performed from the bus control circuit 31 to the input / output terminals 22a
22b, ... Or from the information collecting circuit 32 to the sub-CPU interface / information input / output circuit 13 and from the interface circuit 46 of the main processor 41 to the information input / output circuit 47, as necessary with the system bus 24. It is executed accordingly (steps S32 → S33 to S).
38).

Here, when the processing end instruction is added after the integer operation instruction or the integer data load / store instruction in the instruction data read by the integer operation control unit 27 in step S25, the main processor is added. 21
The process inside and outside of is ended (step S39).

On the other hand, in step S25, if the instruction data read by the integer arithmetic control unit 27 is a quad precision floating point arithmetic instruction or its data load / store instruction, the execution instruction is the integer. It is transmitted from the operation control unit 27 through the sub CPU interface / information input / output circuit 33 to the quad precision floating point arithmetic circuit 44 from the interface circuit 40 of the sub processor 41, and the quad precision floating point arithmetic circuit 44 and the register file (2 ) 45, and the load / store processing of the operation data and the like is performed from the system bus 24 to the bus control circuit 31 of the main processor 21 and the sub CPU.
Between the interface circuit 46 of the sub processor 41 and the register file (2) 45 through the interface / information input / output circuit 33, or from the register file (2) 45 through the interface circuit 56 and the information input / output circuit 47. And is executed as needed with the system bus 24 (steps S32 → S40).
~ S45). Then, after this, the processing is returned to the processing after the step S24.

Therefore, according to the information processing apparatus having the above configuration, the response signal input / output to / from the sub CPU interface / information input / output circuit 33 via the external sub processor connection terminals 23a, 23b, ... Of the main processor 21. If it is determined that the external sub-processor 41 is not in the connected state, the external device (25, 25) from the integer arithmetic control unit 27 to the system bus 24 via the bus control circuit 31.
26) while executing information input / output and information processing with the system bus 24 from the information collecting circuit 33 via the sub CPU interface / information input / output circuit 33.
Performs information input / output processing and information processing with an external device, and when it is determined that the external sub-processor 41 is in the connected state, the quadruple precision arithmetic execution processing in the sub-processor 41 is executed. Since the interface circuit 46 can perform information input / output between the main processor 21 and the system bus 24 through the information input / output circuit 47 and its processing, the sub-processor connection terminal 23a, Even when the external sub-processor 41 is connected to 23b, ..., It is possible to improve the function related to, for example, advanced arithmetic processing while maintaining the same input / output function with the external device when not connected.

The main processor 2 in the above embodiment
The information input / output processing and the processing thereof between the external processor 1 and the external device, and the information input / output processing and the processing thereof between the main processor 21 and the external device via the sub processor 41 are set uniquely to the instruction program and each processor. It is different depending on the various functions performed, and is not limited to a specific input / output processing or processing.

[0050]

As described above, according to the present invention, the sub processor is built in the main processor, and the sub processor can be connected to the outside of the main processor. A sub-processor connection terminal for connecting with a sub-processor, a sub-processor connection judging means for judging whether or not the external sub-processor is connected to the sub-processor connection terminal in the sub-processor inside the main processor, and the external The sub-processor is provided in the sub-processor, and the sub-processor is connected to an external device, and the sub-processor connection determination means determines that the external sub-processor is not connected to the sub-processor connection terminal. First external information input / output to / from the external device via the connection terminal And force means, if it is determined that the external sub-processor to the sub-processor connection terminals are connected by the sub-processor connection determination means,
Second external information input / output means for inputting / outputting data to / from the external device from the subprocessor connection terminal through the external connection terminal of the subprocessor; and the first external information input / output means or the second external device. The data from the external device input to the main processor by the information input / output means is given to the internal sub-processor, and the processing data from the internal sub-processor is supplied to the first external information input / output means or the second external information. Since it is configured to include the information transmission means for giving to the input / output means, even in the main processor to which the external sub-processor can be connected, the sufficient input / output function with the external device can be maintained without adding the input / output terminals. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a single-use configuration of a main processor (main CPU) according to an embodiment of an information processing apparatus of the present invention.

FIG. 2 is an external sub-processor (sub-CPU) for the main processor (main CPU) according to the embodiment of the information processing apparatus.
The block diagram which shows the structure which connected.

FIG. 3 is a flowchart showing initial operation steps of the information processing apparatus.

FIG. 4 is a flowchart showing an operation in the information processing apparatus in a state where an external sub processor is not connected.

FIG. 5 is a flowchart showing the operation of the information processing apparatus when an external sub-processor is connected.

FIG. 6 is a block diagram showing the configuration of a conventional information processing apparatus having a CPU system in which a sub processor (sub CPU) is connected outside the main processor (main CPU).

[Explanation of symbols]

21 ... Main processor (main CPU), 22a, 22b, ...
Input / output terminals, 23a, 23b, ... External subprocessor connection terminals, 24 ... System bus, 24a ... Control bus, 24b ... Address bus, 24c ... Data bus, 25
Input / output device 26 Memory device 27 Integer control unit 28 Integer register file 29 Floating point arithmetic circuit 30 Register file (1) 31
Bus control circuit, 32 ... Information collecting circuit, 33 ... Sub CPU
Interface / information input / output circuit, 41 ... External sub-processor (sub CPU), 42a, 42b ... Main processor connection terminal, 43a, 43b, ... External information input / output terminal,
44 ... Quadruple precision floating point arithmetic circuit, 45 ... Register file (2), 46 ... Interface circuit, 47 ... Information input / output circuit.

Claims (1)

[Claims] 1. An information processing apparatus comprising a sub processor inside the main processor and capable of connecting the sub processor to the outside of the main processor, wherein the sub processor is provided in the main processor and aims to connect to the external sub processor. A processor connection terminal; subprocessor connection determination means for determining whether or not the external subprocessor is connected to the subprocessor connection terminal in the subprocessor inside the main processor; and an external device provided in the external subprocessor. And an external connection terminal for connecting with the external device via the sub-processor connection terminal when the sub-processor connection determination means determines that the external sub-processor is not connected to the sub-processor connection terminal. A first external information input / output means for inputting / outputting data, When the sub-processor connection determination means determines that the external sub-processor is connected to the sub-processor connection terminal, the sub-processor connection terminal and the external device and data via the external connection terminal of the sub-processor Second external information input / output means for inputting / outputting data from the external device input to the main processor by the first external information input / output means or the second external information input / output means. An information transmission means for giving a processing data from the internal sub-processor to the first external information input / output means or the second external information input / output means, and a sub-processor connection terminal in the main processor. An information processing device characterized in that is also used as an input / output terminal with an external device.